JPS60111398A - Memory system - Google Patents

Memory system

Info

Publication number
JPS60111398A
JPS60111398A JP58219115A JP21911583A JPS60111398A JP S60111398 A JPS60111398 A JP S60111398A JP 58219115 A JP58219115 A JP 58219115A JP 21911583 A JP21911583 A JP 21911583A JP S60111398 A JPS60111398 A JP S60111398A
Authority
JP
Japan
Prior art keywords
analog
digital
stored
value
digital value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58219115A
Other languages
Japanese (ja)
Other versions
JPS633398B2 (en
Inventor
Yoshinori Kameyama
亀山 義典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP58219115A priority Critical patent/JPS60111398A/en
Publication of JPS60111398A publication Critical patent/JPS60111398A/en
Publication of JPS633398B2 publication Critical patent/JPS633398B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To make a memory device simply constituted with one analog memory element by storing and accumulating a digital value to be stored in an analog memory device through a D/A convertor and by regenerating the original digital value through and A/D convertor conversely at the time of regenerating. CONSTITUTION:A digital value 1B to be stored is divided into the appropriate number of digits, and the upper rank digit, inter-mediate rank digit, and the lower rank digit are stored and accumulated in the 1st analog memory element 3A through the 1st D/A convertor 2A, the 2nd analog memory element 3B through the 2nd D/A convertor 2B, and the 3rd analog memory element 3C through the 3rd D/A convertor 2C, respectively. At the time of regenerating, a memory value of the 1st memory element 3A, that of the 2nd memory element 3B, and that of the 3rd memory element 3C are digital-synthesized from the 1st A/D convertor 4 to the upper rank digit of a regenerated digital value 5B, from the 2nd A/D convertor 4B to the intermediate rank digit of the regenerated digital value 5B, and from the 3rd A/D convertor 4C to the lower rank digit of the regenerated digital value 5B, respectively.

Description

【発明の詳細な説明】 に詳しくは、周波数,電圧,電流,電力,利得。[Detailed description of the invention] For details, see frequency, voltage, current, power, and gain.

時間,角度,重量,速度その他の数量を記憶せしめる装
置において、記憶すべき数量をデジタル値で設定し、該
デジタル値をデジタル・アナログ変換器を通して得たア
ナログ値をアナログ記憶装置に記憶蓄積して置き、再現
時には該アナログ記憶装置の記憶値をアナログ・デジタ
ル変換器を通して所要の元のデジタル値を再現すべくし
た記憶方式である。
In a device that stores time, angle, weight, speed, and other quantities, the quantity to be stored is set as a digital value, and the analog value obtained by passing the digital value through a digital-to-analog converter is stored and stored in an analog storage device. This is a storage method in which the values stored in the analog storage device are passed through an analog-to-digital converter to reproduce the required original digital values.

周波数、電圧、電流、電力、利得1時間、角度。Frequency, voltage, current, power, gain 1 hour, angle.

重量、速度等の自然現象を計測して得る表示値は連続し
て変化する量の或′る瞬間における状態を示すアナログ
値である。このアナログ値は現在は10進デジタル表示
されるのが普通であシ、アナログ量自体は無限の情報量
を含んでいるが、表示されるアナログ値は通常10進デ
ジタル表示で現わされておシ、従来の計測器の実用指示
精度は10進2桁あるいは3桁程度である。それで、以
下の説明では量自体をアナログ量、表示される値をアナ
ログ値と区別して記述する。
Display values obtained by measuring natural phenomena such as weight and speed are analog values that indicate the state of continuously changing quantities at a certain moment. These analog values are now usually expressed in decimal digital format, and although the analog quantity itself contains an infinite amount of information, the displayed analog value is usually expressed in decimal digital format. The practical indication accuracy of conventional measuring instruments is about two or three decimal digits. Therefore, in the following explanation, the quantity itself will be described as an analog quantity, and the displayed value will be distinguished from an analog value.

また数値を電気的に記憶蓄積する記憶装置としてはアナ
ログ記憶装置は通常アナログ量を電圧または電荷として
記憶素子中に蓄積して置も、再生時にはこの電圧または
電荷を計測してアナログ値を再現するものであυ、記憶
素子は1個で構成される。ただし、記憶素子中の電圧や
電荷は自然放電によシ徐々に減少するので、これを再生
保持するための各種の対策が考案され、改良が行われて
いる。
Furthermore, as a memory device that stores and stores numerical values electrically, an analog memory device usually stores an analog quantity as a voltage or electric charge in a memory element, and during playback, this voltage or electric charge is measured to reproduce the analog value. It is composed of one memory element. However, since the voltage and charge in the memory element gradually decrease due to natural discharge, various measures have been devised and improved to regenerate and maintain this.

デジタル記憶装置はデジタル値が0と1の2進値である
関係上、記憶自体は比較的簡単で−あるが、デジタル値
の桁数だけ記憶素子が必要である上に同一数値でも2進
数は10進数よシも桁数が多くなるので、例えば10進
1桁の数字を記憶するのにデジタル記憶装置では4個(
4ビツト)の記憶素子を必要とするという問題がある。
Digital storage devices are relatively easy to store because the digital values are binary values of 0 and 1, but they require storage elements equal to the number of digits of the digital value, and even if the same numerical value is a binary number, it is relatively easy to store it. Since decimal numbers have many more digits than decimal numbers, for example, to store a single decimal number, a digital storage device requires 4 digits (
There is a problem that a memory element of 4 bits is required.

そこで本発明においては、記憶すべきデジタル値をデジ
タル・アナログ(以下D/Aと書く)変換器を通して得
たアナログ量をアナログ記憶装置に記憶蓄積して置き、
再現時には逆にアナログ・デジタル(以下いと書く)変
換器を通して元のデジタル値を再現するものである。こ
れにょシ記憶装置は1個のアナログ記憶素子で構成され
る極めて簡単な構造が実現できる利点がある。現在のア
ナログ記憶装置の記憶精度は2桁ないし3桁が限度であ
るが、これに対しデジタル記憶装置では10進数3桁の
数値を記憶するのに12個のデジタル記憶素子が必要で
あることは本発明の有用性を立証するものであ勺、アナ
ログ記憶素子の記憶精度は今後さらに改良改善される過
程にあることを考慮すれば、本発明の将来性はさらに有
望である。
Therefore, in the present invention, an analog value obtained by passing a digital value to be stored through a digital-to-analog (hereinafter referred to as D/A) converter is stored and stored in an analog storage device.
During reproduction, the original digital value is reproduced through an analog-to-digital (hereinafter referred to as ``digital'') converter. This storage device has the advantage that it can have an extremely simple structure consisting of one analog storage element. The storage precision of current analog storage devices is limited to two or three digits, whereas digital storage devices require 12 digital storage elements to store a three-digit decimal number. This proves the usefulness of the present invention, but considering that the memory accuracy of analog memory elements is in the process of being further improved in the future, the future prospects of the present invention are even more promising.

また前に述べたように自然現象を計測して得る表示値は
概してアナログ値であるが、最近の電子式周波数計測器
やデジタル電圧計等では10進数出力のほかに2進数出
カを有するものが多いこと、また2進デジタル値に変換
してプリセット値との加減算を行って局部発振周波数を
計測して受信周波数を表示する等の応用上でデジタル値
の記憶と再現が必要になることが多いものである。この
ような要求に応するために本発明はなされたものである
Furthermore, as mentioned earlier, the displayed values obtained by measuring natural phenomena are generally analog values, but recent electronic frequency measuring instruments, digital voltmeters, etc. have binary outputs in addition to decimal outputs. Furthermore, it is necessary to memorize and reproduce digital values for applications such as converting them to binary digital values, performing addition and subtraction with preset values, measuring the local oscillation frequency, and displaying the received frequency. There are many. The present invention has been made to meet such demands.

本発明によれば前記のように、デジタル記憶装置方式に
比して記憶素子は簡略化されるが、ル偽変換器とめ変換
器が余分に必要となる。しかしながら、これ等の変換器
はIC化にょシボ形・安価で入手容易であシ、従来方式
を採るか、本発明を採用するかは適応分野が異るので、
目的と用途に応じて両立が可能である。
According to the present invention, as described above, the storage element is simplified compared to the digital storage system, but an extra false converter and stop converter are required. However, these converters are IC-based, inexpensive, and easily available, and the field of application differs depending on whether the conventional method or the present invention is adopted.
It is possible to achieve both depending on the purpose and use.

アナログ記憶装置の宿命として記憶可能桁数が少ないの
で、本発明ではこれを補う第1の方法を特許請求の範囲
第2項に提示している。すなわち、特許請求の範囲第1
項の記憶すべきデジタル値の一部桁はデジタル値のまま
デジタル記憶装置に記憶蓄積し、その他の桁の値をD/
A変換器を通して得たアナログ量をアナログ記憶装置に
記憶蓄積して置き、再現時には該アナログ記憶装置の記
憶値をψ変換器を通してデジタル値に復原したのち、デ
ジタル記憶装置に記憶のデジタル値と桁合成して、元の
デジタル値を再現すべくした、特許請求範囲第1項記載
の記憶方式である。以下にその構成例を図示して説明す
る。
Since it is the fate of analog storage devices that the number of digits that can be stored is small, the present invention presents a first method to compensate for this in the second claim. That is, claim 1
Some digits of the digital value to be stored in the term are stored as digital values in the digital storage device, and the values of other digits are stored in the D/
The analog quantity obtained through the A converter is stored in an analog storage device, and when reproducing, the stored value in the analog storage device is restored to a digital value through a ψ converter, and then the stored digital value and digit are stored in the digital storage device. This is a storage method according to claim 1, in which the original digital values are reproduced by synthesizing the data. An example of the configuration will be illustrated and explained below.

第1図は本発明の記憶方式の基本構成例を示し、記憶す
べきデジタル値1をD/A変換器2を通してアナログ記
憶素子3に書込命令31によシ記憶蓄積され、再現時に
は読出命令32によシΦ変換器4を通してデジタル値5
を再現するものであって、原則的にデジタル値1と5と
は一致するべきである。しかしながらアナログ記憶素子
には記憶可能桁数の制限があるため、再現値にも制限を
生ずる。
FIG. 1 shows an example of the basic configuration of the storage system of the present invention, in which a digital value 1 to be stored is stored in an analog storage element 3 through a D/A converter 2 by a write command 31, and when reproduced, a read command is issued. 32 to the digital value 5 through the Φ converter 4
In principle, digital values 1 and 5 should match. However, analog storage elements have a limit on the number of digits that can be stored, and therefore there is a limit on the reproducible value.

第2図は上記の弱点を補正した本発明の適用例であって
、記憶すべきデジタル値IAの下位適消桁をD/A変換
器2を通してアナログ記憶素子3に記憶蓄積し、再現時
にはΦ変換器4を通して復原したデジタル値を下位桁と
し、記憶すべきデジタル値IAの残シの上位適当桁をデ
ジタル記憶器6に記憶蓄積し、再現時にはその記憶出方
を復元したデジタル値の上位桁として、復元した下位桁
とデジタル合成してデジタル値5Aを再現するもので必
シ、第3図は記憶すべきデジタル値IAの上位適尚桁を
D/A変換器2を通してアナログ記憶素子3に記憶蓄積
し、再現時にはφ変換器4を通して復元したデジタル値
を上位桁とし、記憶すべきデジタル値IAの残)の下位
適当桁をデジタル記憶器6に記憶蓄積し、再現時にはそ
の記憶出力を復元したデジタル値の下位桁として、復元
した上位桁とデジタル合成してデジタル値5Aを再現す
るものである。上記のごとく記憶すべきデジタル値の下
位桁をアナログ記憶する第2図と記憶すべきデジタル値
の上位桁をアナログ記憶する第3図の構成のいづれを選
ぶ、かけ、記憶すべきデジタル値IAの全桁数と上位桁
と下位桁の重要度を考慮して決定すべきである。
FIG. 2 shows an application example of the present invention that corrects the above-mentioned weaknesses, in which the lower appropriate digits of the digital value IA to be stored are stored in the analog storage element 3 through the D/A converter 2, and when reproducing, Φ The digital value restored through the converter 4 is used as the lower digit, and the remaining upper digits of the digital value IA to be stored are stored in the digital storage device 6, and when reproduced, the upper digit of the digital value is restored in its memory form. It is necessary to digitally synthesize the restored lower digits and reproduce the digital value 5A, and as shown in FIG. The digital value restored through the φ converter 4 is used as the upper digit when it is stored in memory, and the lower appropriate digits of the remaining digital value IA to be stored are stored in the digital storage device 6, and when it is reproduced, the stored output is restored. The lower digits of the resulting digital value are digitally synthesized with the restored upper digits to reproduce the digital value 5A. As mentioned above, select either of the configurations shown in Figure 2, in which the lower digits of the digital value to be stored are stored in analog form, or the configuration in Figure 3, in which the higher digits of the digital value to be stored are stored in analog form, and multiply by the configuration of the digital value IA to be stored. It should be determined by considering the total number of digits and the importance of the upper and lower digits.

さらにアナログ記憶素子の記憶可能桁数の少ないのを補
う第2の方法を特許請求の範囲M3項に提示している。
Furthermore, a second method for compensating for the small number of digits that can be stored in the analog storage element is presented in claim M3.

すなわち、特許請求の範囲第1項のアナログ記憶装置は
複数のアナログ記憶器よシ成夛、記憶すべきデジタル値
を適当桁に分割してD/A変換したのち、複数のアナロ
グ記憶装置に分散して記憶蓄積し、再現に際してはそれ
ぞれのアナログ記憶値をN小食換したデジタル値を合成
して元のデジタル値を再現すべくした、特許請求の範囲
第1項記載の記憶方式である。第4図にその構成例を図
示する。
In other words, the analog storage device according to claim 1 is composed of a plurality of analog storage devices, divides the digital value to be stored into appropriate digits, performs D/A conversion, and then distributes it to the plurality of analog storage devices. This is a storage system according to claim 1, in which the original digital value is reproduced by synthesizing the digital values obtained by replacing N small amounts of the respective analog stored values when reproducing the analog stored values. FIG. 4 shows an example of its configuration.

第4図において記憶すべきデジタル値IBを適当桁(図
では上位桁・中位桁・下位桁の3分割)罠分割して、上
位桁は第1のD/A変換器2人を通して第1のアナログ
記憶素子3Aに記憶蓄積し、中位桁は第2のD/A変換
器2Bを通して第2のアナログ記憶素子3Bに記憶蓄積
し、下位桁は第3のD/A変換器2cを通して第3のア
ナログ記憶素子3Cに記憶蓄積する。再現に際しては第
1の記憶素子3Aの記憶値は第1のAカ変換器4Aを通
って復元したデジタル値を再現デジタル値5Bの上位桁
に、第2の記憶素子3Bの記憶値はM2の〜小食換器4
Bを通って復元したデジタル値を再現デジタル値5Bの
中位桁に、第3の記憶素子3Cの記憶値は第3のい変換
器4cを通って復元したデジタル値を再現デジタル値5
Bの下位桁にデジタル合成して再現するものである。こ
のように構成することによって、本発明のアナログ記憶
素子に記憶蓄積する方式にょシ、必要桁のデジタル値を
記憶および再現することが可能となるものである。
In Fig. 4, the digital value IB to be stored is divided into appropriate digits (in the figure, it is divided into three parts: upper digit, middle digit, and lower digit), and the upper digit is passed through the first two D/A converters to the first The middle digits are stored in the second analog storage element 3B through the second D/A converter 2B, and the lower digits are stored in the second analog storage element 3A through the third D/A converter 2c. Memory is stored in the analog storage element 3C of No. 3. When reproducing, the stored value of the first storage element 3A is the digital value restored through the first A converter 4A, and the stored value of the second storage element 3B is the upper digit of the reproduced digital value 5B. ~Small meal changer 4
The stored value of the third storage element 3C reproduces the digital value restored through the third digital converter 4c.
The lower digits of B are digitally synthesized and reproduced. With this configuration, it becomes possible to store and reproduce digital values of necessary digits using the storage storage method in the analog storage element of the present invention.

上記の第2図ないし第4図においては、底明を簡略にす
るため、第1図の書込命令および読出命令に相当する回
路および動作は省略した。
In the above-mentioned FIGS. 2 to 4, circuits and operations corresponding to the write command and read command in FIG. 1 are omitted for the sake of clarity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の記憶方式の基本構成例を示すブロック
図、第2図は本発明の適用例を示すブロック図、第3図
は本発明の他の適用例を示すブロック図、第4図は本発
明の別の適用例を示すブロック図である。 1、IA、IB・・・記憶すべきデジタル値、2゜2A
 、 2B 、 2C・・・D/A変換器、3 、3A
 、 3B、、3C・・・アナログ記憶器、4,4A、
4B、4C・・・ん小食換器、5.5A、5B・・・再
現されたデジタル値。 特許出願人 八重洲無線株式会社 第 1 図 第 2 図 第 3 図 第 4 例
FIG. 1 is a block diagram showing an example of the basic configuration of the storage system of the present invention, FIG. 2 is a block diagram showing an example of application of the invention, FIG. 3 is a block diagram showing another example of application of the invention, and FIG. The figure is a block diagram showing another example of application of the present invention. 1, IA, IB...Digital value to be memorized, 2゜2A
, 2B, 2C...D/A converter, 3, 3A
, 3B, , 3C...analog storage, 4, 4A,
4B, 4C... small dish changer, 5.5A, 5B... reproduced digital values. Patent applicant Yaesu Musen Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Example

Claims (3)

【特許請求の範囲】[Claims] (1)周波数、電圧、電流、電力、利得2時間。 角度1重量、速度その他の数量を記憶せしめる装置にお
いて、記憶すべき数量をデジタル値で設定し、該デジタ
ル値をデジタル・アナログ変換器を通して得たアナログ
値をアナログ記憶装置に記憶蓄積して置き、再現時には
該アナログ記憶装置の記憶値をアナログ・デジタル変換
器を通して所要の元のデジタル値を再現すべくした記憶
方式。
(1) Frequency, voltage, current, power, gain 2 hours. In a device for storing angle 1 weight, speed, and other quantities, the quantity to be stored is set as a digital value, and an analog value obtained by passing the digital value through a digital-to-analog converter is stored and stored in an analog storage device, A storage method in which the stored value of the analog storage device is passed through an analog-to-digital converter to reproduce the required original digital value at the time of reproduction.
(2)前記の記憶すべきデジタル値の一部桁はデジタル
値のままデジタル記憶装置に記憶蓄積し、その他の桁の
値をデジタル・アナログ変換器を通して得たアナログ値
をアナログ記憶装置に記憶蓄積して置き、再現時には該
アナログ記憶装置の記憶値をアナログ・デジタル変換器
を通してデジタル値に復原したのち、デジタル記憶装置
に記憶のデジタル値と桁合酸して、元のデジタル値を再
現すべくした、特許請求の範囲第1項記載の記憶方式0
(2) Some digits of the above digital value to be stored are stored as digital values in a digital storage device, and analog values obtained from other digits through a digital-to-analog converter are stored in an analog storage device. To reproduce the original digital value, the stored value in the analog storage device is restored to a digital value through an analog-to-digital converter, and the digits are combined with the digital value stored in the digital storage device to reproduce the original digital value. Storage method 0 according to claim 1
(3)前記のアナログ記憶装置は複数のアナログ記憶器
よシ成り、記憶すべきデジタル値を適当桁に分割してデ
ジタル・アナログ変換したのち、複数のアナログ記憶装
置に分散して記憶蓄積し、再現に際してはそれぞれのア
ナログ記憶値をアナログ・デジタル変換したデジタル値
を合成して元のデジタル値を再現すべくした、特許請求
の範囲第1項記載の記憶方式。
(3) The above-mentioned analog storage device is composed of a plurality of analog storage devices, and after dividing the digital value to be stored into appropriate digits and performing digital-to-analog conversion, the analog storage device is distributed to a plurality of analog storage devices for storage storage, 2. The storage method according to claim 1, wherein upon reproduction, the original digital value is reproduced by synthesizing digital values obtained by analog-to-digital conversion of each analog stored value.
JP58219115A 1983-11-21 1983-11-21 Memory system Granted JPS60111398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58219115A JPS60111398A (en) 1983-11-21 1983-11-21 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58219115A JPS60111398A (en) 1983-11-21 1983-11-21 Memory system

Publications (2)

Publication Number Publication Date
JPS60111398A true JPS60111398A (en) 1985-06-17
JPS633398B2 JPS633398B2 (en) 1988-01-23

Family

ID=16730479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58219115A Granted JPS60111398A (en) 1983-11-21 1983-11-21 Memory system

Country Status (1)

Country Link
JP (1) JPS60111398A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343439A (en) * 1976-09-30 1978-04-19 Nec Corp Memory unit
JPS53138244A (en) * 1977-05-10 1978-12-02 Takeda Riken Ind Co Ltd Digital memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343439A (en) * 1976-09-30 1978-04-19 Nec Corp Memory unit
JPS53138244A (en) * 1977-05-10 1978-12-02 Takeda Riken Ind Co Ltd Digital memory

Also Published As

Publication number Publication date
JPS633398B2 (en) 1988-01-23

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