JPS60110139A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a logic integrated circuit capable of using for a large load by forming power supply wirings to an external output buffer circuit in a zigzag shape. CONSTITUTION:Power supply wirings 9 to an external output buffer are formed in a zigzag shape. The schematic effective direction of a path of a current I flowed to the zigzag wirings 9 becomes as shown by arrow with double lines, the direction of an induced current i' induced in wirings 8' when the zigzag current I varies at timing is different at every part in response to the zigzag direction of the current I, only a vector component directed downward of the drawing contributes to the current I', but a vector component of lateral direction of the drawing becomes eddy current loss in the wirings 8 and is erased. Accordingly, the current i' generated in the wirings 8 becomes smaller than the conventional one, the induced voltage becomes low, and a logic erroneous operation hardly occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic integrated circuit, and more particularly to a logic integrated circuit having a large number of output puff circuits.

As the scale of logic integrated circuits increases, a large number of 2771 external output circuits are mounted on a single chip, and at certain timings in circuit operation, some of them operate simultaneously, so power is supplied to these 7 buffer circuits. A large current-time change (hereinafter abbreviated as di/dt) occurs in the common power supply path line, which causes induced noise in the power supply path line and other wiring that supplies power through mutual inductance, resulting in logic malfunctions. The problem of inviting people has arisen and is becoming increasingly important.

Conventionally, this has been dealt with by devising the measurement program and circuit configuration so that the timing of the operation of the external output 2771 circuit does not match during circuit measurement and use. When driving, it is sometimes necessary to connect multiple external output backs 1 in parallel to reduce the drive impedance.
At this time, it is necessary to operate all of these large number of buffers at the same time due to timing, so the external output back 1 which is connected in parallel is
There was a drawback that the number had to be limited and therefore the size of the load had to be kept below a certain level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic integrated circuit in which the above-mentioned drawbacks are improved and which can be used even under heavy loads.

The present invention provides a logic integrated circuit in which power supply wiring to an internal logic circuit and an external output 2771 circuit are separated from each other, wherein the power supply wiring to the external output 2771 circuit has a meandering shape. It's in the circuit.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing power supply wiring to an external output rose 71 of a conventional logic integrated circuit. In the figure, a power supply pad 2, output terminal pads 3 and 4, and an external output buffer 1 circuit block are provided on the main surface of a chip 1. The pad 3 of this output terminal corresponds to the external output buffer 1 circuit block 5, and the pad 4 corresponds to the circuit block 6.Although it is omitted in the first part, there are several to several of these bears. They are arranged repeatedly.

On the other hand, the power supply line 7 is connected to the external output back 71 circuit.
It is connected to the power supply pad 2, and although it is omitted in Fig. 1, the external output buffer 1 circuit 5.6 is connected to the power supply pad 2. It is connected to the same circuit. Further, the power supply line 8 represents a line different from the power supply line 7 which is laid parallel to the power supply line 7 over a long distance, and is a part of the circuit mounted on the chip l. For example, one of the connection lines constituting the circuit may be a signal line, a constant voltage supply line, or a power supply line.

Now, in FIG. 1, one of the external output back 1 circuits in the upper part of the power supply wiring 7, which is omitted in the figure, changes the output level from, for example, low to high.
)K changes, a current change corresponding to the voltage change occurs due to the termination impedance r outside the chip connected to the same output. Assuming that the current I flows in the direction of the double-lined arrow shown in Figure 1, a magnetic flux φ is generated in a plane perpendicular to the current I, and this current flow is caused by a well-known principle in electromagnetism. As it increases with time, the magnetic flux φ also increases.

For this reason, wiring 8 is provided with a wire that cancels out the increase in magnetic flux φ.

An induced current i is generated in the direction, that is, in the direction of the - double line arrow.

This induced current i appears as a voltage change due to the l impedance connected to the wiring 8.

This changes the internal logic level of chip 1.

This may lead to logical malfunctions. In particular, external exit buff 1
When a large number of circuits operate simultaneously, the time change in the current I shown in FIG. 1 becomes larger, and the voltage change induced in the wiring system 8 also becomes larger, making logic malfunctions even more likely to occur. especially.

In recent years, as logic integrated circuits have become larger and have more pins,
As the number of external output buffer circuits 71 increases, the probability that a plurality of external output buffers 71 make the same logic change at the same time increases, so the above-mentioned logic malfunction is likely to occur.

Figure ts2 is a plan view of an embodiment of the present invention designed to alleviate the occurrence of such logical malfunctions. In Figure 2,
The same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

Now, the most characteristic feature of the present invention is the meandering wiring 9, whose main function is exactly the same as the power supply wiring 7 to the external output capacitor 7 shown in FIG. The approximate effective direction of the flow path of the current I flowing through the meandering wiring 9 is indicated by a meandering double line arrow. When such a meandering electric current changes over time, the direction of the induced current i' induced in the wiring 8' varies depending on the meandering direction of the current I. Only the vector component in the direction contributes to the induced current i', and the vector component in the left and right direction in FIG. 2 becomes an eddy current loss in the wiring 8 and disappears. That is, when the amount of change over time of the electric current shown in FIG. 1 and the current eta shown in FIG. 2 is the same, the induced current i generated in the wiring 8 in FIG. The generated induced current 1' is smaller, and therefore the induced voltage is smaller, making it difficult for logic malfunctions to occur.

As described above, according to the present invention, the power supply wiring to the external output buffer 1 is made to meander.

Since it is possible to reduce the induced current induced in wiring that is close to the power supply wiring over a long distance, effects such as being able to suppress logic malfunctions can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a conventional logic integrated circuit, and FIG. 2 is a plan view showing a logic integrated circuit according to an embodiment of the present invention. In the same figure, 1...chip, 2...
Power supply pad, 3.4... Output pad, 5
, 6...external cover, 7 a block, 7, 9...
...Power supply wiring to Mongolian external output buffer 1 circuit,
8... Another series of wiring adjacent to it. / 蔀I Illustration 2

Claims (1)

[Claims] A logic integrated circuit in which power supply wiring to an internal logic circuit and an external output 7771 circuit are separated from each other, characterized in that the power supply wiring to the external output buffer 1 circuit has a meandering shape.