JPS60109283A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60109283A JPS60109283A JP21687283A JP21687283A JPS60109283A JP S60109283 A JPS60109283 A JP S60109283A JP 21687283 A JP21687283 A JP 21687283A JP 21687283 A JP21687283 A JP 21687283A JP S60109283 A JPS60109283 A JP S60109283A
- Authority
- JP
- Japan
- Prior art keywords
- film
- crystallized
- amorphous
- semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000013078 crystal Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 2
- 238000002425 crystallisation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- BQJCRHHNABKAKU-KBQPJGBKSA-N morphine Chemical compound O([C@H]1[C@H](C=C[C@H]23)O)C4=C5[C@@]12CCN(C)[C@@H]3CC5=CC=C4O BQJCRHHNABKAKU-KBQPJGBKSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- ZPAPCUKKKOSLPZ-UHFFFAOYSA-N morphan Chemical compound C1CNC2CCCC1C2 ZPAPCUKKKOSLPZ-UHFFFAOYSA-N 0.000 description 1
- 229960005181 morphine Drugs 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、゛１′導体装置構造Ｋ ｌｆｌする。[Detailed description of the invention] The present invention provides a ``1'' conductor device structure Klfl.
（ｒ／・Ｋ、ｉ？： 、４ｔ１体ｕ ｉ’７け例えばア
モルファス半導体から成Ｘ）’ｈ ｒ、ｉ体装置：′１
′に；ｂてけ、Ｙモルフ丁ス単層璋１＋＊’、゛ｌ’導
体装置／ｉを形成トろのが油側で力、った、１、か１２
、Ｌ記？Ｆｒ牢技術にすると、γモルファヌ゛Ｉ′導体
％ＪＳ ｌｉ’１″のへ連化に限１”ｆが生じるという
欠点が声・−１な。(r/・K, i?: , 4t1 body u i'7 made of, for example, an amorphous semiconductor X)'h r, i body device: '1
'B, Y morphine single layer 1 + *', 'l' Forming the conductor device/i, the force on the oil side was 1, 12
, L? When using the Fr cell technology, the drawback is that 1"f occurs only when the γ morphan I' conductor is connected to a conductor of 1".
木！７．１１１１ ｔｔ ／ト１Ｊ’ｓ ７−ンに車ｔ
１７？Ｊｒのか占＆ ｔｒビ１ γモ／ｌ−ファス半導
体を用いた半導体装置に於ても高速化が可能な半導体装
ｆＰｔ ｔｉＩｌ造を提供することを目的とする、
１；記目的を達成するための、本発明のｌＳ、木的１．
【構成は、半導体装置に於て、ガラス集４反１−． Ｋ
はｌｌ＋結晶または多結晶から成る結晶イトさｈた”Ｆ
？、’ｆ体月ζ（が形成され、該結晶化さねた半涛体
嘩Ｉ：Ｉ−Ｕ １−／”モルファス半導体すαが形成さ
れて成ることを特徴とするＯ
以下、実施例により本発明を詳述する、第１図６従来技
術を示すＮＯ８ＦＢＴの断面図である。すなわち、ガラ
ス基板１０表面にはアモノトファヌＦｔｊ膜２が形成さ
れ、該アモルファスｇマ’ Ｒには拡散層３．４、ゲー
ト酸化膜５、その上にゲート？ｔｆ榛６が形成されて、
１．イＯ８型ＦＦｊＴを（１”りｈ’２ して成る。wood! 7.1111 tt / 1J's 7-car t
17? To achieve the following objectives, the purpose is to provide a semiconductor device fPttiIl structure that can increase the speed even in semiconductor devices using gamma mo/l-fas semiconductors. The lS of the present invention, tree-like 1.
[The structure is as follows: In a semiconductor device, 4 glass plates 1-. K
is a crystal consisting of ll+crystals or polycrystals.
? , 'f body ζ() is formed, and the crystallized semiconducting body I: I-U 1-/'' is characterized by the formation of amorphous semiconductor α. 6 is a cross-sectional view of NO8FBT showing the prior art, which explains the present invention in detail. That is, an Amonotofanu Ftj film 2 is formed on the surface of a glass substrate 10, and a diffusion layer 3. 4. A gate oxide film 5 and a gate ?tf film 6 are formed thereon.
1. It is made by (1"rih'2) of 08 type FFjT.
第２図は本発明の一実雄例を示す）、Ｊ Ｏｊ”ｊり（
ＩＩ Ｔｌ・ｌ・：゛工゛の断面図である。すなわち、
ガラス基４ｆｉ １１グ）！−面にはプラズマＯＶＤで
形成されたア−Ｆ ／１ ノアクＳｉ膜をレー→ドー・
アニールで多結晶ヤｆｒ ｉ□Ｉ ｌ結晶化した結晶化
Ｓｉ膜１２、その）（ＦプラズマＣＶＤで形成さり、ｆ
ｃアモルファスＳ１：ｌｌＩ＋３の２層半導体膜構令に
は、拡散層ｊｉ！、１５及びゲート酸化脇１６そのｔ二
に形成さｆｌ、 ｐ Ａ’ −ト電１ケ１７から成るテ
゛イープ 〒イブレソションタイプのＭＯ８型ＦＥＴで
ある。Figure 2 shows an example of the present invention);
II Tl.l.: It is a sectional view of the "work". That is,
Glass base 4fi 11g)! - side is coated with A-F/1 Noack Si film formed by plasma OVD.
The crystallized Si film 12 is annealed and polycrystalline.
The two-layer semiconductor film structure of c amorphous S1:llI+3 includes a diffusion layer ji! , 15 and a gate oxidation side 16 and a gate electrode 17 formed on the two sides of the gate oxidation side 16.
本発明の如（、結晶北米導体ｌｌαとアモＡ・ファスゝ
ｒ導体障を２１−にすることにより、キャリアーの移動
度の大Ａい結晶化膜にキャリアーを挿過させて、高速化
を１９することがで＾る効ツがある、According to the present invention (by making the crystalline conductor llα and the amorphous A-fasr conductor barrier 21-21-2, carriers can be inserted into a crystallized film with high carrier mobility, increasing the speed to 19-19). There are some benefits to doing this,
第１図（１１イ′来技術によるＭＯＳハＩＩ Ｆ Ｉｕ
Ｔの断面図、第２１ツ１は本発明による−す雄側を示
す）４０８型Ｆ ｒｌ； ＴのＮ？ｉ面図である。
１．１１ ・・・・・・ガラスＪ４板
２．１３・・・・・・アモルファス半導体＋＋ｉ１２・
・・・・・結晶化半導体嘆
３．４．１１１．１５・・・・・・拡散層５．１６・・
・・・・／ｙ’−ト酸化膜６．１７・・・・・・）ｆ−
）ｆｌｉｆ」す、ト
出願人 株式会社 諏訪精工舎
代理人 弁理士 が−に をン？Figure 1 (11) MOS High II F Iu
408 type F rl; N of T? It is an i-side view. 1.11...Glass J4 plate 2.13...Amorphous semiconductor++i12.
...Crystallized semiconductor layer 3.4.111.15...Diffusion layer 5.16...
.../y'-t oxide film 6.17...) f-
)flif', the applicant Suwa Seikosha Co., Ltd., a patent attorney.
Claims (1)
結晶化さＩ］、 ｆ ？ト導体膜が形成され、該結晶化
された半２．り体膜ｈ Ｋけアモルファス半導体殴が形
成さハて成ろことを特徴とする半導体装置。Crow' 1 Oni/board E 2 is crystallized consisting of φ crystals or polycrystals I], f? A conductive film is formed on the crystallized half 2. 1. A semiconductor device characterized in that an amorphous semiconductor layer is formed in a body film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21687283A JPS60109283A (en) | 1983-11-17 | 1983-11-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21687283A JPS60109283A (en) | 1983-11-17 | 1983-11-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60109283A true JPS60109283A (en) | 1985-06-14 |
Family
ID=16695234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21687283A Pending JPS60109283A (en) | 1983-11-17 | 1983-11-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60109283A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02303167A (en) * | 1989-05-18 | 1990-12-17 | Sanyo Electric Co Ltd | Semiconductor device |
| US4988634A (en) * | 1986-10-08 | 1991-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming FET with a super lattice channel |
| JPH0334457A (en) * | 1989-06-30 | 1991-02-14 | Semiconductor Energy Lab Co Ltd | Field effect semiconductor device |
| JPH0334459A (en) * | 1989-06-30 | 1991-02-14 | Semiconductor Energy Lab Co Ltd | Manufacture of field effect semiconductor device |
-
1983
- 1983-11-17 JP JP21687283A patent/JPS60109283A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4988634A (en) * | 1986-10-08 | 1991-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming FET with a super lattice channel |
| US5008211A (en) * | 1986-10-08 | 1991-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming FET with a super lattice channel |
| JPH02303167A (en) * | 1989-05-18 | 1990-12-17 | Sanyo Electric Co Ltd | Semiconductor device |
| JPH0334457A (en) * | 1989-06-30 | 1991-02-14 | Semiconductor Energy Lab Co Ltd | Field effect semiconductor device |
| JPH0334459A (en) * | 1989-06-30 | 1991-02-14 | Semiconductor Energy Lab Co Ltd | Manufacture of field effect semiconductor device |
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