JPS601079U - Vertical synchronization signal separation circuit - Google Patents
Vertical synchronization signal separation circuitInfo
- Publication number
- JPS601079U JPS601079U JP9235383U JP9235383U JPS601079U JP S601079 U JPS601079 U JP S601079U JP 9235383 U JP9235383 U JP 9235383U JP 9235383 U JP9235383 U JP 9235383U JP S601079 U JPS601079 U JP S601079U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- gate
- synchronization signal
- output
- vertical synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の垂直同期信号分離回路を示す回路図、第
２図は第１図に示す回路の動作を説明する為の信号波形
図、第３図はこの考案に係る垂直同期信号分離回路を示
す回路図、第４図は第３図に示す回路の動作を説明する
為の信号波形図である。
２２・・・同期信号分離部、Ｑ２１〜Ｑ２４・・・トラ
ンジスタ、Ｒ２□〜Ｒ３□・・・トランジスタ、Ｄ２１
．Ｄ２３・・・ダイオード、Ｄ２２・・・ツェナーダイ
オード、Ｃ２１，Ｃ２２・・・コンデンサ。Figure 1 is a circuit diagram showing a conventional vertical synchronization signal separation circuit, Figure 2 is a signal waveform diagram for explaining the operation of the circuit shown in Figure 1, and Figure 3 is a vertical synchronization signal separation circuit according to this invention. FIG. 4 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 3. 22...Synchronization signal separation unit, Q21-Q24...Transistor, R2□-R3□...Transistor, D21
．． D23...Diode, D22...Zener diode, C21, C22...Capacitor.
Claims (1)
力をスライスしてパルス状の垂直同期信号を得る波形整
形手段と、この波形整形手段の出力信号から所定のパル
ス幅以上のノクルス幅を有するパルスを検出するパルス
検出手段と、このパルス検出手段から所定のパルス幅以
上のパルス幅を有するパルスが検出されたら所定のパル
ス幅を有するゲートパルスを発生するゲートパルス発生
手段と、このゲートパルス発生手段から出力されるゲー
トパルスの期間だ前記波形整形手段の出力信号を出力端
子５導ひくゲート手段とを具備した垂直同期信号分離回
路。an integrating means for integrating a video signal; a waveform shaping means for slicing the integrated output of the integrating means to obtain a pulsed vertical synchronizing signal; and a Noculus width greater than a predetermined pulse width from the output signal of the waveform shaping means. pulse detection means for detecting a pulse; gate pulse generation means for generating a gate pulse having a predetermined pulse width when a pulse having a pulse width equal to or greater than a predetermined pulse width is detected by the pulse detection means; and the gate pulse generation means. and gate means for guiding the output signal of the waveform shaping means to an output terminal 5 during the period of the gate pulse output from the means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9235383U JPS601079U (en) | 1983-06-16 | 1983-06-16 | Vertical synchronization signal separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9235383U JPS601079U (en) | 1983-06-16 | 1983-06-16 | Vertical synchronization signal separation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS601079U true JPS601079U (en) | 1985-01-07 |
Family
ID=30222520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9235383U Pending JPS601079U (en) | 1983-06-16 | 1983-06-16 | Vertical synchronization signal separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601079U (en) |
-
1983
- 1983-06-16 JP JP9235383U patent/JPS601079U/en active Pending
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