JPS60107162A - Channel device - Google Patents

Abstract

PURPOSE:To obtain properly detailed information relating to the generation of a fault by detecting the timing of data transmission/reception with a specific input/ output device if the fault is generated at the data transmission/reception with the specific input/output device. CONSTITUTION:If a fault due to a channel device or an input/output interface 5 is generated when a large quantity of transmission/reception of data with plural input/output devices are conducted, the address of a corresponding microprogram instruction is set to a memory comparison address register 11. An address of control information relating to the input/output having a fault is set simultaneously to a comparison address register 13. Then in executing the input/output operation, a timing signal in the inside of the channel device and a signal of the input/output interface 5 are caught in the timing when the addresses of comparator circuits 12, 14 are coincident to obtain detailed information of the fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a channel device that is controlled by a microprogram and can multiplex data exchange with a plurality of input/output devices.

[Prior art]

FIG. 1 is a block diagram showing an example of a computer system configured using a channel device of this type, in which (1) is a central processing unit, (2) is a memory device, and (3) is a central processing unit.
1 is a channel device, (4,a), (4b), (4
(4n) is an input/output device, and (51 is an input/output interface).

FIG. 2 is a block diagram showing an example of a conventional channel device of this type, in which (6) is a channel control circuit;
(7) is a control information storage memory that stores control information for each input/output device i; 8: is a control information storage memory (device address register that holds the address of 71; (9))
is a control memory storing microboo program instructions; 1
0) is a control memory address register that holds the address of the control memory (9), (111 is a control memory/comparison address register in which the address to be compared with the address of the control memory address register is set by external input, and (1)
A is a comparison circuit that compares the addresses of the control memory/address register 10) and the control memory/comparison address register (old).

In a computer system, if any failure occurs due to a channel device or an input/output interface (5), the input/output operation is stopped and the control memory
Set the address of the microprogram instruction that causes the failure in the external input to the comparison address register uIl, execute the input/output operation again, and set the address of the control memory address register 110) to the control memory/comparison address register old). Comparator circuit 02 detects timing that matches the address set in
) The conventional method for obtaining fault information for channel equipment is configured as described above, so it is possible to multiplex data exchange with input/output devices of different orders. If a failure occurs during data exchange with a specific input/output device, it will take a lot of time to analyze and pursue if only the common routine of the microprogram is used. The drawback was that it was time consuming.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional devices as described above. When a failure occurs when multiplexing data exchange with multiple input/output devices, the failure is caused by the failure of a specific input/output device. If the problem occurs during data exchange with a device, a means to detect the timing of data exchange with that specific input/output device can be installed to accurately obtain detailed information about the occurrence of the failure. The purpose is to provide a self-contained device.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention,
In the figure +61, +71, 181, +91
, 101 , Qll , α 埠 indicate parts that are the same as or correspond to the same reference numerals in FIG. 2, and +131 indicates the device.
A device/comparison address register in which an address to be compared with the address of the address register 18) is set by external input; a comparison circuit that compares the address of the device/comparison address register (54: 8) and the device/comparison address register (131); (c) is an and gate.

A failure caused by a channel device or input/output interface (5) occurs when a large amount of data is exchanged with multiple input/output devices;
Set the address of the nucleating microprogram instruction in the control memory/comparison address register (old), and set the address of control information regarding the input/output device that causes a failure when transmitting/receiving data to the device/comparison address register (13). to perform input/output operations,
By capturing the internal timing signal of the channel device and the signal of the human output interface (5) at the timing when the addresses of the comparison circuit 02 and the comparison circuit (14) match, detailed information on the failure can be obtained.

〔Effect of the invention〕

As described above, according to the above invention, the trigger point for failure occurrence when multiplexing data exchange with multiple input/output devices can be set not only at the passing point of the microgram instruction but also at the corresponding input/output device. This has the advantage that it is possible to narrow down the control information of the device to the passing points, accurately obtain detailed information on the failure, and quickly analyze and pursue the failure.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a computer system configured using this Yuzu channel device, Figure 2 is a block diagram showing an example of a conventional Yuzu channel device, and Figure 3 is a block diagram showing an example of a conventional computer system configured using this Yuzu channel device. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, (6) is the control circuit, (7) is the control information storage memory, 18) is the device address register, (9) is the control memory, ll0) is the control memory address register, and (old) is the control Memory/comparison address register, 0o is a comparison circuit, ++31 is a device/comparison address register, 04 is a comparison circuit, α→ is an AND gate. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Procedure amendment band (voluntary) Showa 5 No. 2I = 118th Mr. Commissioner of the Japan Patent Office - 1, Indication of case Patent application No. 1982-214703 3 Make amendments Representative Hitoshi Katayama, Department 4, Agent 5, Subject of amendment (1) On page 3, line 13 of the specification, the phrase ``disability occurs'' is corrected to ``related to disability.'' (2) In the same book, page 6, line 6, ``According to this invention'' is corrected to ``According to this invention''. (that's all)

Claims (1)

[Claims] In a channel device that is controlled by a microprogram and can multiplex data exchange with multiple input/output devices, there is a control memory that stores microprogram instructions, and a control 1 memory that holds the address of this control memory.
Address register, control memory/comparison address register in which the address to be compared with the address of this control memory/address register is set by external input, comparison that compares the address of the above control memory/address register with the address of the above control memory/comparison address register A circuit, a control information storage memory that stores control information for each input/output device of the input/output device for the number of rice grains, a denocent address register that holds the address of this control information storage memory, and an address of this device address register. A channel characterized in that it is equipped with a device/comparison address register in which an address to be compared with is set by an external input, and a comparison circuit that ratios the address of the device/comparison address register and the device/comparison address register. Device.