JPS60106202A - Monolithic microwave integrated circuit - Google Patents

Monolithic microwave integrated circuit

Info

Publication number
JPS60106202A
JPS60106202A JP58214453A JP21445383A JPS60106202A JP S60106202 A JPS60106202 A JP S60106202A JP 58214453 A JP58214453 A JP 58214453A JP 21445383 A JP21445383 A JP 21445383A JP S60106202 A JPS60106202 A JP S60106202A
Authority
JP
Japan
Prior art keywords
line
dielectric layers
semiconductor substrate
semiconductor
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58214453A
Other languages
Japanese (ja)
Other versions
JPH0763121B2 (en
Inventor
Hirotsugu Ogawa
博世 小川
Tetsuo Hirota
哲夫 廣田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58214453A priority Critical patent/JPH0763121B2/en
Publication of JPS60106202A publication Critical patent/JPS60106202A/en
Publication of JPH0763121B2 publication Critical patent/JPH0763121B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H01P11/001Manufacturing waveguides or transmission lines of the waveguide type
    • H01P11/003Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Waveguides (AREA)

Abstract

PURPOSE:To reduce factors such as a discontinuous part which deteriorates high frequency characteristics by forming a semiconductor element and a transmission line on a semiconductor substrate in a plane, further >=1 dielectric layers and arranging a transmission line, and coupling those lines with a semiconductor element. CONSTITUTION:The input signal of an input port 31 is applied to a gate electrode 19 through a microstrip line 4, through hole 27, and coplanar line 25. The conversion from the line 4 to the line 25 is performed through the through hole 27, but the conversion is attained through the through hole having a diameter nearly as large as line width because the dielectric layers 2 and 3 are thin, and the characteristic deterioration of an FET13 due to the conversion is ignored, so that this circuit is applicable to a high frequency band. Further, electrodes 14, 19, and 21 of the FET13 are on the same plane and connected easily. Therefore, a short circuit need not be inserted between a semiconductor projection part and a dielectric layer to eliminate characteristic deterioration due to a discontinuous part.

Description

【発明の詳細な説明】 この発明は半導体素子を含むモノリンツクマイクロ波集
積回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to monolink microwave integrated circuits including semiconductor devices.

〈従来技術〉 従来のモノリシックマイクロ波集積回路は第1図に示す
よう九半導体基板1上に誘電体層2,3が並べて設けら
れ、これらの誘電体層2,3上のみに高周波信号の伝送
路、ここではマイクロストリップ線路4,5が配置され
ている0これらの誘電体層2,3の接地導体6,7は半
導体基板1の接地導体8(誘電体層2,3の形成m1と
反対の而)に側面の接続導体11 、12を通じて接続
されている・半導体素子(第1図では電界効果トランジ
スタ)13は誘電体層2,3の間においてマイクロスト
リップ線路5,6を形成している面と同一平面上におい
て構成されておシ、従って誘電体層2,30間では半導
体基板1が誘電体層2,3の厚味だけ高い突部1aが形
成され、その突部1a上に電界効果トランジスタ13が
形成されている。電界効果トランジスタ(以後、FET
と記す)13のソース電極14を接地するため半導体基
板1の突部1aと誘電体層2.3の間に短絡板15 、
16が挿入され、短絡板15゜16に接続されて突部1
aの表面上に接地導体膜17゜18がFET13を両側
から囲うように形成され、この接地導体膜17 、18
にソース電極14が接続される。
<Prior art> As shown in FIG. 1, a conventional monolithic microwave integrated circuit has dielectric layers 2 and 3 arranged side by side on a semiconductor substrate 1, and high-frequency signals are transmitted only on these dielectric layers 2 and 3. The ground conductors 6, 7 of these dielectric layers 2, 3 are connected to the ground conductors 8 of the semiconductor substrate 1 (opposite to the formation m1 of the dielectric layers 2, 3), in which the microstrip lines 4, 5 are arranged. A semiconductor element (a field effect transistor in FIG. 1) 13 is connected to the conductors 11 and 12 on the side surface, forming microstrip lines 5 and 6 between the dielectric layers 2 and 3. Therefore, between the dielectric layers 2 and 30, a protrusion 1a is formed where the semiconductor substrate 1 is as high as the thickness of the dielectric layers 2 and 3, and an electric field is generated on the protrusion 1a. An effect transistor 13 is formed. Field effect transistor (hereinafter FET)
A short circuit plate 15 is provided between the protrusion 1a of the semiconductor substrate 1 and the dielectric layer 2.3 in order to ground the source electrode 14 of the semiconductor substrate 1 (denoted as ) 13,
16 is inserted and connected to the short circuit plate 15° 16, and the protrusion 1
Ground conductor films 17 and 18 are formed on the surface of a to surround the FET 13 from both sides, and the ground conductor films 17 and 18
A source electrode 14 is connected to.

FET13のゲート電極19は入力側のマイクロストリ
ップ線路4に、ドレイン電(奴21は出力骨]のマイク
ロストリップ線路5にそれぞれ接続されている。
The gate electrode 19 of the FET 13 is connected to the microstrip line 4 on the input side and to the microstrip line 5 of the drain electrode (the electrode 21 is the output bone).

マイクロストリイブ線路4とゲート電極19との接続部
は接地導体膜17 、18とコプレーナ線路22を構成
している。マイクロストリップ線路4,5に接続された
マイクロストリップ線路23 、24は整合用スタブを
形成している。
The connection portion between the microstrive line 4 and the gate electrode 19 constitutes a coplanar line 22 with the ground conductor films 17 and 18. Microstrip lines 23 and 24 connected to microstrip lines 4 and 5 form a matching stub.

このように従来のモノリンツクマイクロ波集積回路では
半導体突部1aと誘電体層2,3との間に短絡板15 
、16を形成する必要があり、これはモノリンツクマイ
クロ波集積回路を製作する製造工程を腹雑にし、この回
路の価格が高くなるという問題があった。捷だ、マイク
ロストリップ線路4からの人力信号はコプレーナ線路2
2に変換されて、1”ET13に印加することになるが
、マイフロストリノブ線路−コグレーナ線路変換部の不
連続部の影ttle KよりFET13の性能、例えば
増幅器としての利?:Iや周波数特性が劣化する問題も
あった。
In this way, in the conventional monolink microwave integrated circuit, the shorting plate 15 is placed between the semiconductor protrusion 1a and the dielectric layers 2 and 3.
, 16, which complicates the manufacturing process for manufacturing a monolink microwave integrated circuit and increases the cost of this circuit. Well, the human signal from microstrip line 4 is coplanar line 2.
However, the performance of FET 13, such as the efficiency as an amplifier, such as I and frequency, is There was also the problem that the characteristics deteriorated.

〈発明の概要〉 この発明の目的は製造が容易なモノリシンタフイク0汲
集積回路を提供することにある。
<Summary of the Invention> An object of the present invention is to provide a monolithic integrated circuit that is easy to manufacture.

この発明によれば半導体基板上に半導体素子が形成され
、その素子とが同一面で半導体基板上に第1の伝送線路
が設けられる。さらにその第1の伝送線路を含み上記半
導体基板上に誘電体層が形成され、その誘電体層上に上
記第1の伝送線路と結合した第2の伝送線路が形成され
る。
According to this invention, a semiconductor element is formed on a semiconductor substrate, and a first transmission line is provided on the semiconductor substrate on the same surface as the element. Further, a dielectric layer is formed on the semiconductor substrate including the first transmission line, and a second transmission line coupled to the first transmission line is formed on the dielectric layer.

〈実施例〉 第2図はこの発明によるモノリシックマイクロ波集積回
路の一例を示し、第1図と対応する部分に同一符号を付
けである。半導体基板1の一面に#導体素子(この例で
はFET ) 13が形成され、とのFET 13の形
成面と同一面で半導体基板1にそのFET13と接続さ
れた伝送線路が形成される。この例ではFET13上を
除いてFET13の形成面に接地導体膜6が形成され、
接地導体膜6は両側の接続導体11 、12を通じて半
導体基板1の接地導体8に接続される。FET13の両
側にゲート電極19.及びノース電極21にそれぞれ一
端が接続されたコプレーナ線路25 、26が接地導体
膜6に形成される。コプレーナ線路25 、26上をそ
れぞれ含み、半導体基板1上に誘電体層2,3がそれぞ
れ形成され、誘電体層2,3上にマイクロストリップ線
路4,5がそれぞれ形成される。マイクロストリイブ線
路4゜5の一端はそれぞれスルーポール27 、28を
通じてコプレーナ線路25 、26の各他端に接続され
る。マイクロストリップ線路4,5の各他端は入力ボー
ト31.出力ポート32にそれぞれ接続される。
<Embodiment> FIG. 2 shows an example of a monolithic microwave integrated circuit according to the present invention, in which parts corresponding to those in FIG. 1 are given the same reference numerals. A # conductor element (FET in this example) 13 is formed on one surface of the semiconductor substrate 1, and a transmission line connected to the FET 13 is formed on the semiconductor substrate 1 on the same surface as that on which the FET 13 is formed. In this example, the ground conductor film 6 is formed on the formation surface of the FET 13 except on the FET 13,
The ground conductor film 6 is connected to the ground conductor 8 of the semiconductor substrate 1 through connection conductors 11 and 12 on both sides. Gate electrodes 19. on both sides of the FET 13. Coplanar lines 25 and 26, each having one end connected to the north electrode 21, are formed on the ground conductor film 6. Dielectric layers 2 and 3 are formed on the semiconductor substrate 1, including the coplanar lines 25 and 26, respectively, and microstrip lines 4 and 5 are formed on the dielectric layers 2 and 3, respectively. One end of the microstrive line 4.degree. 5 is connected to the other end of the coplanar lines 25, 26 through through poles 27, 28, respectively. Each other end of the microstrip lines 4 and 5 is connected to an input boat 31. They are connected to output ports 32, respectively.

入カポ−)31からの人力信号はマイクロストリップ線
路4.スルーポール27.コプレーナ線路25を経てゲ
ート電極19に加えられる。マイクロストリップ線路4
からコプレーナ線路25への変換はスルーホール27を
通して行われるが、誘電体層2゜3のJワさが士分助い
ため線路幅程度の直径を有するスルーホールで変換でき
、不連続成分を十分小さくできる。したがって、この変
換部にょるPET13の特性劣化はlH!(視でき、高
い周波数帯にも適用が目」能である。FET13の電極
14 、19 、21はコプレーナ線路25 、26と
同−乎面内にあるため、これら電イ1り4とコプレーナ
線路との接続は容易に行われる。
The human input signal from the input capo) 31 is transmitted through the microstrip line 4. Through pole 27. It is applied to the gate electrode 19 via a coplanar line 25. Microstrip line 4
The conversion from a coplanar line 25 to a coplanar line 25 is carried out through a through hole 27, but since the J width of the dielectric layer 2°3 is helpful, the conversion can be made with a through hole having a diameter about the width of the line, and the discontinuous component can be made sufficiently small. can. Therefore, the characteristic deterioration of PET 13 due to this conversion section is lH! (The electrodes 14, 19, and 21 of the FET 13 are in the same plane as the coplanar lines 25 and 26. Connection is easily made.

FET13により増幅された入力信号はコノッーナ線路
26.スルーホール28.マイクロストリップ線路5を
経て、出力ポート32から得られる。
The input signal amplified by the FET 13 is sent to the cononner line 26. Through hole 28. It is obtained from the output port 32 via the microstrip line 5.

このようにこの構成では半導体突部と誘電体層との間に
短絡板を挿入する必要が無く、不連続部による特性劣化
は無い。また、コプレーナ線路25゜26はFET 1
3を製作する製造工程で同時に作ることができるため、
FET素子単体と同程度のコストで製作できる利点があ
る。
In this manner, with this configuration, there is no need to insert a shorting plate between the semiconductor protrusion and the dielectric layer, and there is no characteristic deterioration due to the discontinuous portion. Also, the coplanar line 25°26 is FET 1
3 can be made at the same time in the manufacturing process,
It has the advantage that it can be manufactured at a cost comparable to that of a single FET element.

〈他の実施例〉 第3図はこの発明の他の実施例を示し、第2図と対応す
る部分に同一符号を付けである。この例では半導体基板
1上に半導体素子とじてンヨットキバリアダイオード(
以下SBDと記す) 30 、40が形成される。まだ
接地導体膜6にスロット線路33が、5BD30,40
の両名に一端が接近して形成され、更にSBD 30 
、40の配列の両外側にスロット線路34゜35がスロ
ット線路33と反対方向に延長して接地導体膜6に形成
される0スロット線路34. 、35は同一長さとされ
、その他端はスロット線路36で連結される。スロット
線路33の他端は開放とするだめのスロット空洞37に
連結される。スロット線路33の一端の両側の導体膜は
SBD 30 、40のカソード38゜アノード39に
それぞれ延長接続され、513D30,40のアノード
41.カソード42はそれぞれスロット線路34 、3
5の内側の導体膜に延長接続される。スロツ) Lx路
33.スロット空洞37を含み半導体基板1上に誘電体
層2が形成され、スロットa路34 、35゜36を含
み半導体基板1上に誘電体層3が形成される。誘電体層
2,3上にそれぞれ形成されたマイクロストリップ線路
4,5は、誘電体層2,3の板面と直角方向から見て、
一端部がスロツF mA路33 、36とそれぞれ直交
されてスルーホール27 、28を通じて接地導体膜6
に接続される。マイクロストリップ線路5にス) IJ
ツブ導体43を通じて直流バイアス印加端子45に接続
される。
<Other Embodiments> FIG. 3 shows another embodiment of the present invention, in which parts corresponding to those in FIG. 2 are given the same reference numerals. In this example, a semiconductor element and a barrier diode (
(hereinafter referred to as SBD) 30 and 40 are formed. The slot line 33 is still on the ground conductor film 6, but the 5BD30, 40
One end is formed close to both names of SBD 30
, 40, slot lines 34, 35 extend in the opposite direction to the slot lines 33, and are formed on the ground conductor film 6. , 35 have the same length, and the other ends are connected by a slot line 36. The other end of the slot line 33 is connected to an open slot cavity 37. The conductor films on both sides of one end of the slot line 33 are extended and connected to the cathode 38° anode 39 of the SBDs 30 and 40, respectively, and the anodes 41 . The cathodes 42 are connected to the slot lines 34 and 3, respectively.
It is extended and connected to the inner conductor film of 5. Slots) Lx Road 33. A dielectric layer 2 is formed on the semiconductor substrate 1 including the slot cavity 37, and a dielectric layer 3 is formed on the semiconductor substrate 1 including the slot a-way 34, 35° 36. The microstrip lines 4 and 5 formed on the dielectric layers 2 and 3, respectively, when viewed from the direction perpendicular to the plate surfaces of the dielectric layers 2 and 3,
One end is perpendicular to the slot F mA paths 33 and 36, respectively, and is connected to the ground conductor film 6 through the through holes 27 and 28.
connected to. microstrip line 5) IJ
It is connected to a DC bias application terminal 45 through a prong conductor 43 .

入力ポート31からの入力信号はマイクロストリップ線
路4.スルーホール27を通してスロット線路33に変
換結合される0スロツト空$i37は開放条件を与え、
マイクロストリップ線路4からスロット線路33への変
換効率を向上させている。スロット線路33にはSBD
 30 、40が直列に2個接続されており、SBD 
30 、40を0N−OFFすることによって入力信号
はスロット線路34−または35に伝搬することになる
。SBDの0N−OFF信号は端子45からストl)ツ
ブ導体43を通して加えられる。SBD 30がON。
The input signal from the input port 31 is transmitted to the microstrip line 4. The 0 slot empty $i37 which is converted and coupled to the slot line 33 through the through hole 27 provides an open condition,
The conversion efficiency from the microstrip line 4 to the slot line 33 is improved. SBD on slot line 33
Two 30 and 40 are connected in series, and SBD
By turning 30 and 40 ON and OFF, the input signal is propagated to the slot line 34- or 35. The SBD ON-OFF signal is applied from the terminal 45 through the spur conductor 43. SBD 30 is ON.

5BD40がOFFのとき、信号成分はスロット線路3
5を伝搬し、スルーホール28を通してマイクロストリ
ップ線路5に変換結合され、出力がボート32より得ら
れる。逆に5BD30が0FFXSBD40がONのと
きにはスロット線路34を経て出力が得られ、信号の位
相は前の場合と逆になっており、2相位相変調波が得ら
れることになる。
When 5BD40 is OFF, the signal component is sent to slot line 3.
5, is converted and coupled to the microstrip line 5 through the through hole 28, and an output is obtained from the boat 32. Conversely, when 5BD30 and 0FFXSBD40 are ON, an output is obtained via the slot line 34, and the signal phase is reversed from the previous case, resulting in a two-phase phase modulated wave.

このように、半導体基板1上に半導体素子30゜40、
伝送線路33 、34 、35を形成し、更に薄い誘電
体層2,3を形成し、これら誘電体層2,3上に伝送線
路4,5を配置することにより、大幅に小形化された2
相位相変調器を構成できる利点がある。また、寄生素子
を生じさせる不連続部が無いため、高周波帯で動作可能
な位相変調器をも実現できる利点がある。さらに、2個
のSBD 30 、40を形成する領域を非常に狭くで
きるので、半導体素子のバラ付きを小さくでき、再現性
の良い回路を製作できる利点がある。
In this way, semiconductor elements 30° 40,
By forming transmission lines 33, 34, and 35, further forming thin dielectric layers 2 and 3, and arranging transmission lines 4 and 5 on these dielectric layers 2 and 3, the 2
There is an advantage that a phase modulator can be configured. Furthermore, since there are no discontinuities that cause parasitic elements, there is an advantage that a phase modulator that can operate in a high frequency band can be realized. Furthermore, since the area in which the two SBDs 30 and 40 are formed can be made very narrow, there is an advantage that variations in semiconductor elements can be reduced and circuits with good reproducibility can be manufactured.

半導体基板上に形成する誘電体層を多層構造としてもよ
い。また半導体基板上や誘電体層上に形成する伝送線路
としてはマイクロストリップ線路。
The dielectric layer formed on the semiconductor substrate may have a multilayer structure. Microstrip lines are also used as transmission lines formed on semiconductor substrates or dielectric layers.

スロット線路、コプレーナ線路、更だこれら線路の結合
線路を用いてもよい。
A slot line, a coplanar line, or a combination of these lines may be used.

く効 果〉 以上説明したように、この発明によれば半導体基板上に
半導体素子及び伝送線路がほぼ同面で形成され、さらに
1層以上の誘電体層が形成され、この誘電体層に伝送線
路が配置され、これらの線路および半導体素子が結合さ
れてモノリフツクマイクロ波集積回路を形成しているた
めに、回路の高周波特性を劣化させる不連続部等の要因
を少々くでき、寸だ、FET等の半導体素子の製造工程
を適用するととてよる回路の低コスト化を1図ることが
でき、さらに、これまで小形化、再現性等に問題があっ
た回路の大幅な小形化、再現性の向上を図ることができ
る利点がある。
Effect> As explained above, according to the present invention, a semiconductor element and a transmission line are formed on a semiconductor substrate almost on the same plane, and one or more dielectric layers are further formed, and transmission lines are formed on this dielectric layer. Because the lines are arranged and these lines and semiconductor elements are combined to form a monolithic microwave integrated circuit, factors such as discontinuities that degrade the high frequency characteristics of the circuit can be reduced to a small extent. By applying the manufacturing process of semiconductor elements such as FETs, it is possible to reduce the cost of circuits, and it is also possible to significantly reduce the size and reproducibility of circuits that have previously had problems with miniaturization and reproducibility. This has the advantage of improving sexual performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のモノリフツクマイクロ波集積回路を示す
斜視図、第2図及び第3図はそれぞれこの発明の一実施
例を示す頒視[ヌ1である。 1・・半導体基板、2,3・誘電体層、4,5マイクロ
ストリツプ線路、6・接地4)体膜、13・・電界効果
トランジスタ(FET )、14・ ソース電極、19
・・・ゲート電極、21・・ドレイン電極1.25.2
6・・・コプレーナ線路、27 、28・−・スルーホ
・−ル、31・・・入力ポート、32・・・出力ボート
、37・スロット空洞、33〜36・・・スロット線路
、30 、40・・ショットキバリアダイオード(SB
D )。 特許出願人 日本電信電話公社 代 理 人 草 野 卓 オ I 回 オ 2 回
FIG. 1 is a perspective view showing a conventional monolift microwave integrated circuit, and FIGS. 2 and 3 are perspective views showing one embodiment of the present invention, respectively. 1. Semiconductor substrate, 2, 3. Dielectric layer, 4, 5 microstrip line, 6. Ground 4) Body film, 13. Field effect transistor (FET), 14. Source electrode, 19
...Gate electrode, 21...Drain electrode 1.25.2
6... Coplanar line, 27, 28... Through hole, 31... Input port, 32... Output boat, 37. Slot cavity, 33-36... Slot line, 30, 40...・Schottky barrier diode (SB
D). Patent applicant: Representative of Nippon Telegraph and Telephone Public Corporation: Takuo Kusano 1 time 2 times

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板の一面に半導体素子が形成され、その
半導体素子の形成面とほぼ同一面で上記半導体基板に上
記半導体素子と接続された第1の伝送線路が形成され、
その第1の伝送線路を含み上記半導体基板上に誘電体層
が形成され、その防電体層上に上記第1の伝送線路と結
合した第2の伝送線路が形成されてなるモノリンツクマ
イクロ波集積回路。
(1) A semiconductor element is formed on one surface of a semiconductor substrate, and a first transmission line connected to the semiconductor element is formed on the semiconductor substrate on substantially the same surface as the surface on which the semiconductor element is formed;
A monolink microwave in which a dielectric layer including the first transmission line is formed on the semiconductor substrate, and a second transmission line coupled to the first transmission line is formed on the electric shield layer. integrated circuit.
JP58214453A 1983-11-14 1983-11-14 Monolithic microwave integrated circuit Expired - Lifetime JPH0763121B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58214453A JPH0763121B2 (en) 1983-11-14 1983-11-14 Monolithic microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58214453A JPH0763121B2 (en) 1983-11-14 1983-11-14 Monolithic microwave integrated circuit

Publications (2)

Publication Number Publication Date
JPS60106202A true JPS60106202A (en) 1985-06-11
JPH0763121B2 JPH0763121B2 (en) 1995-07-05

Family

ID=16656004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58214453A Expired - Lifetime JPH0763121B2 (en) 1983-11-14 1983-11-14 Monolithic microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPH0763121B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251059A (en) * 1985-04-26 1986-11-08 テクトロニツクス・インコ−ポレイテツド Microwave integrated circuit package
JPH01165203A (en) * 1987-12-21 1989-06-29 A T R Hikaridenpa Tsushin Kenkyusho:Kk Passive circuit device for microwave integrated circuit
FR2636473A1 (en) * 1988-09-14 1990-03-16 Mitsubishi Electric Corp FIELD EFFECT TRANSISTOR FOR MICROBAND MOUNTING AND MICROBAND TYPE TRANSISTOR STRUCTURE
KR100349571B1 (en) * 2000-07-04 2002-08-24 안달 Resonator Using Defected Ground Structure on Dielectric

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128901A (en) * 1979-03-28 1980-10-06 Nippon Telegr & Teleph Corp <Ntt> High frequency circuit device
JPS5672508A (en) * 1979-11-19 1981-06-16 Nippon Telegr & Teleph Corp <Ntt> Microwave transistor circuit device
JPS5873138A (en) * 1981-10-27 1983-05-02 Toshiba Corp Microwave amplifier
JPS5884510A (en) * 1981-10-29 1983-05-20 ワトキンズ・ジヨンソン・コムパニ− Rf amplifying circuit using fet device
JPS58112373A (en) * 1981-12-25 1983-07-04 Toshiba Corp Manufacture of gaas ic

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128901A (en) * 1979-03-28 1980-10-06 Nippon Telegr & Teleph Corp <Ntt> High frequency circuit device
JPS5672508A (en) * 1979-11-19 1981-06-16 Nippon Telegr & Teleph Corp <Ntt> Microwave transistor circuit device
JPS5873138A (en) * 1981-10-27 1983-05-02 Toshiba Corp Microwave amplifier
JPS5884510A (en) * 1981-10-29 1983-05-20 ワトキンズ・ジヨンソン・コムパニ− Rf amplifying circuit using fet device
JPS58112373A (en) * 1981-12-25 1983-07-04 Toshiba Corp Manufacture of gaas ic

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251059A (en) * 1985-04-26 1986-11-08 テクトロニツクス・インコ−ポレイテツド Microwave integrated circuit package
JPH01165203A (en) * 1987-12-21 1989-06-29 A T R Hikaridenpa Tsushin Kenkyusho:Kk Passive circuit device for microwave integrated circuit
FR2636473A1 (en) * 1988-09-14 1990-03-16 Mitsubishi Electric Corp FIELD EFFECT TRANSISTOR FOR MICROBAND MOUNTING AND MICROBAND TYPE TRANSISTOR STRUCTURE
US4996582A (en) * 1988-09-14 1991-02-26 Mitsubishi Denki Kabushiki Kaisha Field effect transistor for microstrip mounting and microstrip-mounted transistor assembly
KR100349571B1 (en) * 2000-07-04 2002-08-24 안달 Resonator Using Defected Ground Structure on Dielectric

Also Published As

Publication number Publication date
JPH0763121B2 (en) 1995-07-05

Similar Documents

Publication Publication Date Title
JPH03145801A (en) High-separative passive switch
US6081006A (en) Reduced size field effect transistor
US4390851A (en) Monolithic microwave amplifier having active impedance matching
US6320476B1 (en) Millimeter-band semiconductor switching circuit
US4423388A (en) RF Amplifier circuit employing FET devices
JP3045074B2 (en) Dielectric line, voltage controlled oscillator, mixer and circuit module
JPS60153602A (en) Converting circuit of coplanar line and slot line
JPS60106202A (en) Monolithic microwave integrated circuit
JP3178598B2 (en) Power amplifier
EP0817275B1 (en) High-frequency FET
JP2654248B2 (en) Coplanar antenna
JP2000031708A (en) Monolithic microwave integrated circuit
JPH0119761B2 (en)
JP2594558B2 (en) Field-effect transistor
JPS6349922B2 (en)
JP2737874B2 (en) Semiconductor line converter
JPS5860575A (en) Transistor
JPH0927594A (en) High-frequency monolithic integrated circuit
JP3493152B2 (en) Semiconductor device
JP2001044717A (en) Microwave semiconductor device
JP2878049B2 (en) High frequency transistor
JPH0419842Y2 (en)
JP3279207B2 (en) High frequency circuit
JP3357715B2 (en) Microwave phase shifter
JPH10335954A (en) Wide-band feedback amplifier