JPS60105279A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60105279A JPS60105279A JP58213504A JP21350483A JPS60105279A JP S60105279 A JPS60105279 A JP S60105279A JP 58213504 A JP58213504 A JP 58213504A JP 21350483 A JP21350483 A JP 21350483A JP S60105279 A JPS60105279 A JP S60105279A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- electrode
- floating
- dirt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000008018 melting Effects 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 229910021332 silicide Inorganic materials 0.000 abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- -1 Arsenic ions Chemical class 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 11
- 230000005684 electric field Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910015861 MSix Inorganic materials 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に浮遊ケ゛−ト型の読み
出し専用メモＩＪ （ＲＯＭ）に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a floating gate type read-only memory IJ (ROM).
いわゆるＳＡＭＯ８（５ｔａｃｋｅｄ ｇａｔｅ Ａｖ
ａｌａｎｃｈｅｉｎｊｅｃｔｉｏｎ ＭＯＳ ）構造の
ＰＲＯＭ （Ｐｒｏｇｒａｍｍａｂｌｅ ＲＯＭ）セル
を第１図を参照して説明する。The so-called SAMO8 (5 tacked gate Av
A PROM (Programmable ROM) cell having an franchise injection MOS (MOS) structure will be explained with reference to FIG.
図中１は例えばｐ型シリコン基板であり、この基板１上
には第１のダートｉ化膜２を介して浮遊ダート電極（第
１のダート電極）３が形成されている。この浮遊ゲート
電極３上には第２のダート酸化膜４を介して制御ケ゛−
ト電極（第２のダート電極）５が形成されている。また
、基板１表面には積層された浮遊ダート電極３及び制御
ダート電極５をマスクとして例えば砒素をイオン注入す
ることによ、９ｎ＋型ソース、ドレイン領域６，７が形
成されている。更に、浮遊ダート電極３及び制御ケ°−
ト電４ｆｉ、５の表面は熱酸化膜８によって佳われてい
る。In the figure, reference numeral 1 denotes, for example, a p-type silicon substrate, on which a floating dart electrode (first dart electrode) 3 is formed with a first dirt i-oxide film 2 interposed therebetween. A control cable is placed on this floating gate electrode 3 via a second dirt oxide film 4.
A dirt electrode (second dirt electrode) 5 is formed. Furthermore, 9n+ type source and drain regions 6 and 7 are formed on the surface of the substrate 1 by ion-implanting, for example, arsenic using the laminated floating dart electrode 3 and control dart electrode 5 as masks. Furthermore, the floating dart electrode 3 and the control case
The surfaces of the electric currents 4fi and 5 are enhanced by a thermal oxide film 8.
上記ＦＲＯＭセルでは書き込みは制御ケゝ−ト電極５に
高い正電圧を印加するとともに、ソース。In the above FROM cell, writing is performed by applying a high positive voltage to the control gate electrode 5, and also applying a high positive voltage to the control gate electrode 5.
ド〈イン領域６．ン間に高電圧を印カルて、逆バイアス
されたドレイン領域７側接合におけるアバランシェ現象
によって発生したホットエレクトロンを第１のダート酸
化膜２を通して浮遊ダート電極３に注入することによシ
行なわれる。In area 6. This is done by applying a high voltage between the electrodes and injecting hot electrons generated by an avalanche phenomenon in the reverse biased drain region 7 side junction into the floating dirt electrode 3 through the first dirt oxide film 2.
また、動作時に制御ゲート電極５に正（例えば５Ｖ）の
電圧を印加すると、浮遊ダート電極３が負に帯電してい
るか否かによるしきい値電圧の違いから、浮遊ケ゛−ト
電極３が負に帯電していないトランジスタは導通するが
、浮遊ダート電極３が帯電していないトランジスタは導
通しないので、トランジスタがオンかオフかで情報の読
み出しを行なう。Furthermore, when a positive voltage (for example, 5 V) is applied to the control gate electrode 5 during operation, the floating dart electrode 3 becomes negatively charged due to the difference in threshold voltage depending on whether the floating dart electrode 3 is negatively charged or not. A transistor whose floating dart electrode 3 is not charged is conductive, but a transistor whose floating dart electrode 3 is not charged is not conductive, so information is read depending on whether the transistor is on or off.
更に、消去はＥＰＲＯＭ （Ｅｒａｓａｂｌｅ ＰＲＯ
Ｍ ）では紫外線照射により電子に浮遊ダート電極３と
第２のｒ−）酸化膜４との界面の１障壁高さよシ高いエ
ネルギーを与えて浮遊ダート電極３から制御ダート電極
５へ電子を放電させることにより行なうｏｆだ、Ｅ ｐ
ＲＯＭ （Ｅｌｅｃｔｒｉｃａｌｌｙ Ｅｒａｓａｂｌ
ｅＦＲＯＭ ）では制御ダート電極５に基板１より非常
に高い電圧を印加し、浮遊ゲート電極から制御ダート電
極５へ電子を放電させることにより行なう。Furthermore, erasing can be done using EPROM (Erasable PRO
In M), ultraviolet irradiation gives electrons energy higher than one barrier height at the interface between the floating dart electrode 3 and the second r-) oxide film 4, and discharges the electrons from the floating dart electrode 3 to the control dart electrode 5. By doing so, E p
ROM (Electrically Erasable
eFROM), this is done by applying a much higher voltage to the control dart electrode 5 than to the substrate 1 and discharging electrons from the floating gate electrode to the control dart electrode 5.
ところで、従来、一般的に浮遊ダート電極３はリン拡散
した多結晶シリコン膜で、また第２のダート電極４は多
結晶シリコンの酸化膜で形成されている。Incidentally, conventionally, the floating dart electrode 3 is generally formed of a phosphorus-diffused polycrystalline silicon film, and the second dirt electrode 4 is formed of a polycrystalline silicon oxide film.
この場合、多結晶シリコン膜と酸化膜との界面における
電子の障壁高さは３．２５ ｅＶと高く、トンネル電流
によシミ子が容易にリークすることはない。このことが
不揮発性を高めているが、逆に消去が困難であるという
ことを意味する。In this case, the electron barrier height at the interface between the polycrystalline silicon film and the oxide film is as high as 3.25 eV, and the smear does not easily leak due to tunnel current. Although this improves non-volatility, it also means that it is difficult to erase.
そこで、浮遊ダート電極３の表面に凹凸を設け、曲率を
持った等電位面の周囲で電界が増強される効果を利用し
て消去効率を高めることも行なわれているが、非常に高
度なプロセス技術を必要とする。Therefore, an attempt has been made to increase the erasing efficiency by providing unevenness on the surface of the floating dart electrode 3 and utilizing the effect of increasing the electric field around the curved equipotential surface, but this method requires a very advanced process. Requires technology.
また、浮遊り°ゞ−ト電極３を通常の高融点金属ケイ化
物、例えばＭｏ Ｓ ｉ２を使用した場合、Ｍｏ Ｓ
ｉ２と酸化膜との界面における電子の障壁高さは約３．
５ｅＶとなるので、浮遊ダート電極３を多結晶シリコン
膜で形成した場合よシも更に電子はリークしにくくなり
、消去は一層困難忙なると考えられる。Furthermore, when the floating electrode 3 is made of an ordinary high melting point metal silicide, for example, MoSi2, MoS
The electron barrier height at the interface between i2 and the oxide film is approximately 3.
Since the voltage is 5 eV, it is considered that the leakage of electrons becomes even more difficult than when the floating dart electrode 3 is formed of a polycrystalline silicon film, and erasing becomes even more difficult and time-consuming.
本発明は上記事情に鑑みてなされたものであシ、書き込
み又は消去を効率よく行ない得るＥＰＲＯＭ又はＥ Ｐ
ＲＯＭ等の半導体装置を提供しようとするものである。The present invention has been made in view of the above circumstances, and is an EPROM or EPROM that can efficiently perform writing or erasing.
The aim is to provide semiconductor devices such as ROM.
本発明の半導体装置はいわゆるＳＡＭＯ８構造において
、第１のデート電極（浮遊ダート電極）をＭＳｉｘ（但
し、Ｍは高融点金属、 Ｘ＞２ ）なる組成、すなわち
シリコンリッチな高融点金属シリサイドとし、第２のダ
ート絶縁膜をこの高融点金属シリサイドの酸化膜で形成
したことを特徴とするものである。The semiconductor device of the present invention has a so-called SAMO8 structure, in which the first date electrode (floating dart electrode) has a composition of MSix (where M is a high melting point metal, X>2), that is, silicon-rich high melting point metal silicide; This structure is characterized in that the dirt insulating film No. 2 is formed of an oxide film of this high melting point metal silicide.
こうした半導体装置では、例えば高融点金属としてＭｏ
を用いた場合について説明すると、Ｍｏ５１ｘからなる
浮遊デート電極から基板へのＩＪ−り電流は非常に高く
、逆方向のリーク電流は低いので、この浮遊ダート電極
から基板への高いリーク電流を利用することによシ、消
去（浮遊ダート電極を負に帯電させる場合）又は書き込
み（浮遊ダート電極を正に帯電させる場合）を極めて容
易に行なうことができる。また、第２のダート絶縁膜と
なるＭｏ Ｓ ｉ Ｘの酸化膜は多結晶シリコンの酸化
膜よりリークも少なく絶縁破壊電界も高いので電荷の保
持特性が優れている。In such semiconductor devices, for example, Mo is used as a high melting point metal.
To explain the case using , the IJ current from the floating date electrode made of Mo51x to the substrate is very high, and the leakage current in the reverse direction is low, so the high leakage current from this floating date electrode to the substrate is utilized. In particular, erasing (if the floating dart electrode is negatively charged) or writing (if the floating dart electrode is positively charged) can be carried out very easily. In addition, the MoS i
なお、こうした半導体装置は従来の製造方法に特別な工
程を付加することなく簡便な工程で製造することができ
る。この場合、第１のダート絶縁膜上にＭｏＳｉｘ膜を
堆積するには同時蒸陪または同時ス・ぐツタ法が望まし
い。Note that such a semiconductor device can be manufactured by a simple process without adding any special process to the conventional manufacturing method. In this case, simultaneous evaporation or simultaneous sputtering is preferably used to deposit the MoSix film on the first dirt insulating film.
以下、本発明の実施例を製造方法を併記して説明する。 Examples of the present invention will be described below along with manufacturing methods.
なお、製造方法の説明は既述した第１図を利用して行な
う。Note that the manufacturing method will be explained using FIG. 1 mentioned above.
まず、ｐ型シリコン基板１表面に図示しないフィールド
酸化膜を形成した後、フィールド酸化膜によって囲まれ
た素子領域表面に厚さ４００又の第１のダート酸化膜２
を形成する。次に、厚さ４０００ＸのＭｏＳｉｘ膜をＸ
が２よシ犬なるような組成、例えばｘ ＝ ２．６でＤ
Ｃマグネトロン同時スパッタ法によシ堆積する。つづい
て、ＭｏＳｉｘ膜の一部を選択的にエツチング除去する
Ｏ次いで、熱酸化を行ないＭｏ５ｉｚ膜表面に厚さ５０
０Ｘの第２のダート酸化膜４を形成する。First, a field oxide film (not shown) is formed on the surface of a p-type silicon substrate 1, and then a first dirt oxide film 2 with a thickness of 400 mm is formed on the surface of the element region surrounded by the field oxide film.
form. Next, a MoSix film with a thickness of 4000X was
For example, when x = 2.6, D
It is deposited by C magnetron co-sputtering method. Next, a part of the MoSix film is selectively etched away with O etching, and then thermal oxidation is performed to form a 50% thick layer on the surface of the Mo5iz film.
A second dirt oxide film 4 of 0x is formed.
つづいて、全面に多結晶シリコン膜を堆積した後、多結
晶シリコン膜、第２のゲート酸化膜４゜Ｍｏ５ｉｚ膜及
び第１のダート酸化膜２を順次・ぐターニングする。こ
の結果、基板１上に第１のダート酸化膜２を介してＭｏ
５ｉｚ膜からなる浮遊ゲート電極（第１０ケ゛−計電極
）３が、更に浮遊ゲート電極３上に第２のゲート酸化膜
４を介して多結晶シリコン膜からなる制御ダート電極（
第２のダート電極）５が形成される。Subsequently, after depositing a polycrystalline silicon film over the entire surface, the polycrystalline silicon film, the second gate oxide film 4°Mo5iz film, and the first dirt oxide film 2 are sequentially turned. As a result, Mo is formed on the substrate 1 through the first dirt oxide film 2.
A floating gate electrode (10th scale electrode) 3 made of a 5iz film is further connected to a control dirt electrode (10th scale electrode) made of a polycrystalline silicon film on the floating gate electrode 3 via a second gate oxide film 4.
A second dart electrode) 5 is formed.
次いで、積層された浮遊ダート電極３及び制御ダート電
極５等をマスクとして例えば砒素をイオン注入した後、
熱処理しくｎ＋型ソース、ドレイン領域６，７を形成す
る。つづいて、熱６ソ化を行ない浮遊ダート電極３及び
制御ダート電極５０表面に熱酸化膜８を形成する。Next, after ion implantation of, for example, arsenic is performed using the stacked floating dart electrodes 3, control dart electrodes 5, etc. as masks,
N+ type source and drain regions 6 and 7 are formed by heat treatment. Subsequently, thermal oxidation is performed to form a thermal oxide film 8 on the surfaces of the floating dart electrode 3 and the control dart electrode 50.
以下、層間絶縁膜、配線等を形成しＦＲＯＭセルを製造
する。Thereafter, an interlayer insulating film, wiring, etc. are formed to manufacture a FROM cell.
上記ＦＲＯＭセルの第１のケ゛−ト酸化膜２を通過する
リーク電流のＩ−Ｖ％性を第２図及び第３図に示す。な
お、いずれも酸化膜厚は約４００又、ダート面積は約０
．１燗２であシ、第２図は浮遊ゲート電極３から基板１
へのリーク電流、第３図は基板１から浮遊ダート電極３
へのリーク電流をそれぞれ示す。FIGS. 2 and 3 show the IV percentage characteristics of the leakage current passing through the first gate oxide film 2 of the FROM cell. In both cases, the oxide film thickness is approximately 400 mm, and the dirt area is approximately 0.
．． Figure 2 shows floating gate electrode 3 to substrate 1.
The leakage current from the substrate 1 to the floating dart electrode 3 is shown in Figure 3.
The leakage current to each is shown.
第２図及び第３図から明らかなように浮遊ケ゛−ト電極
３から基板１へのリーク電流は極めて高いのに対し、基
板１から浮遊ダート電極３へのリーク電流は多結晶シリ
コンダートと同程度に低い。ただし、第２図かられかる
ようにダート電圧−１０Ｖ以下ではリーク電流は極めて
小さいので、使用時のリーク電流は無視できる。As is clear from FIGS. 2 and 3, the leakage current from the floating dirt electrode 3 to the substrate 1 is extremely high, whereas the leakage current from the substrate 1 to the floating dirt electrode 3 is the same as that of polycrystalline silicon dirt. Moderately low. However, as can be seen from FIG. 2, the leakage current is extremely small when the dart voltage is -10V or less, so the leakage current during use can be ignored.
一方、第４図にＭｏＳｉｘの酸化膜からなる第２のゲー
ト酸化膜のオーノエ分析結果の一例を、第５図（ａ）及
び（ｂ）に多結晶シリコンの酸化膜とＭｏ５ｉｚの酸化
膜の耐圧の比較をそれぞれ示す。On the other hand, Fig. 4 shows an example of the Ohnoe analysis results of the second gate oxide film made of MoSix oxide film, and Fig. 5 (a) and (b) show the breakdown voltage of polycrystalline silicon oxide film and Mo5iz oxide film. A comparison of each is shown below.
第４図はダート酸化膜（図中右側）上にＭｏ５ｉｚ膜（
図中中央部）を堆積し、９００℃で７００分間熱酸化を
行ない酸化膜（図中左側）を形成したものである。第４
図から明らかなようにＭｏＳｉｘを酸化した場合、その
酸化膜はほとんどＭｏを含まず、ＳｉＯ２膜とみなして
よい。Figure 4 shows a Mo5iz film (
The oxide film (center part in the figure) was deposited and thermally oxidized at 900° C. for 700 minutes to form an oxide film (left side in the figure). Fourth
As is clear from the figure, when MoSix is oxidized, the oxide film contains almost no Mo and may be regarded as a SiO2 film.
また、第５図（、）は多結晶シリコンの酸化膜（酸化温
度１０００℃、膜厚１１００Ｘ）、同図（ｂ）はＭｏＳ
ｉｘの酸化膜（酸化温度１０００℃。In addition, Fig. 5 (,) is a polycrystalline silicon oxide film (oxidation temperature 1000°C, film thickness 1100X), and Fig. 5 (b) is a MoS
ix oxide film (oxidation temperature 1000°C.
膜厚１０９０Ｘ）の耐圧（ブレークダウン電界強度と確
率との関係）を示すヒストグラムである。なお、図中１
．Ｂ、Ｄ、 （Ｉｎ１ｔｉａｌ Ｂｒｅａｋｄｏｗｎ）
は５ Ｘ １０ Ａ／ｃｍ のリーク電流が流れる初期
破壊電界を、図中Ｆ、Ｂ、Ｄ、は（Ｆｉｎａｌ Ｂｒｅ
ａｋｄｏｗｎ ）は絶縁破壊電界をそれぞれ示す。第５
図（ａ）及び（ｂ）から明らかなように初期破壊電界、
絶縁破壊電界ともにＭｏ Ｓ ｉ Ｘの酸化膜の方が高
電界側に分布があり、耐圧が優れている。This is a histogram showing the breakdown voltage (relationship between breakdown electric field strength and probability) of a film having a thickness of 1090×. In addition, 1 in the figure
．． B, D, (In1tial Breakdown)
is the initial breakdown electric field where a leakage current of 5 x 10 A/cm flows, and F, B, D in the figure are (Final Bre
akdown) respectively indicate the dielectric breakdown electric field. Fifth
As is clear from figures (a) and (b), the initial breakdown electric field,
Both the dielectric breakdown electric field and the MoSiX oxide film have a distribution on the higher electric field side and are superior in breakdown voltage.
上記ＦＲＯＭセルを従来のＥＰ ＲＯＭやＥ２ＰＲＯＭ
と同様に、浮遊ダート電極３を負に帯電させて使用する
場合について説明する。The above FROM cell can be used as a conventional EP ROM or E2PROM.
Similarly, the case where the floating dart electrode 3 is negatively charged and used will be described.
まず、書き込みは従来の装置と同様にアバランシェ注入
によシミ子を浮遊ダート電極３に注入する。この場合、
ＭｏＳｉｘからなる浮遊ダート電極３は負に帯電するが
、第２図に示しだように一１０Ｖ未満の帯電であれば、
浮遊ダート電極３からの電子のリークは問題にならない
。１次に、読み出しは従来の装置と同様に制御ダート電
極５に正の電圧を印加し、トランジスタがオンかオフか
で情報が書き込まれているかどうかを判断する。更に、
消去は第２図に示したようにＭｏＳｉｘからなる浮遊ダ
ート電極３がら基板１へ電子がリークし易いことを利用
して、ＥＰＲＯＭでは紫外線を照射することによシ、ま
たＥ２ＦＲＯＭでは制御ダート電極５に負の高電圧を印
加することにより、それぞれ基板１へ電子を放電させて
行なう。First, for writing, a smear is injected into the floating dart electrode 3 by avalanche injection as in the conventional device. in this case,
The floating dart electrode 3 made of MoSix is negatively charged, but as shown in FIG. 2, if it is charged less than -10V,
Electron leakage from the floating dart electrode 3 is not a problem. First, for reading, a positive voltage is applied to the control dart electrode 5 as in the conventional device, and it is determined whether information has been written based on whether the transistor is on or off. Furthermore,
As shown in FIG. 2, erasing is carried out by irradiating ultraviolet rays in EPROM, taking advantage of the fact that electrons easily leak from the floating dart electrode 3 made of MoSix to the substrate 1, and in E2FROM, by irradiating the control dart electrode 5. Electrons are discharged to the substrate 1 by applying a negative high voltage to the substrate 1.
したがって、上記半導体装置によれば書き込み易さ、安
定した保持及び消去し易さのすべてを満足し、半導体不
揮発性メモリとして極めて良好な特性を有するものであ
る。また、その製造方法は従来の方法に特別な工程を付
方口する必要がなく極めて簡便である。Therefore, the semiconductor device described above satisfies all of the requirements of ease of writing, stable retention, and ease of erasing, and has extremely good characteristics as a semiconductor nonvolatile memory. In addition, the manufacturing method is extremely simple as there is no need to add any special steps to conventional methods.
なお、上記実施例では浮遊ダート電極３を負に帯電させ
て使用する場合について説明したが、浮遊ダート電極３
を正に帯電させて使用することもできる。この場合、書
き込みは個々の制御ゲート電極５を書き込みのために選
択できるようにし、制御ダート電極５に負の高電圧を印
加してＭｏ５ｉＸからなる浮遊ダート電極３から基板１
へ電子を注入することにより行なう。浮遊ダート電極３
を正に帯電させると、現在主流となっているｎチャネル
ＭＯ８技術においては、特に制御ダート電極５に正の電
圧を印加しなくともトランジスタを導通させることがで
き、情報の読み出しを容易に行なうことができる。ただ
し、消去についてはＭｏ Ｓ Ｉ Ｘからなる浮遊ケ９
−ト電極３への電子のリークレベルは第３図に示すよう
に多結晶シリコンの場合と同程度であるので、特にメリ
ットはない。なお、消去は紫外線照射を利用したＥＰＲ
ＯＭ方式でもよいし、従来の装置の書き込みと同様にア
バランシェ注入によシミ子を注入し、浮遊ダート電荷の
正電荷を相殺してもよい。In addition, in the above embodiment, the case where the floating dart electrode 3 is negatively charged and used is explained, but the floating dart electrode 3
It can also be used with a positive charge. In this case, writing is performed by making it possible to select individual control gate electrodes 5 for writing, applying a negative high voltage to the control gate electrodes 5, and moving the floating dart electrodes 3 made of Mo5iX from the substrate 1.
This is done by injecting electrons into the floating dart electrode 3
In the currently mainstream n-channel MO8 technology, by positively charging the transistor, the transistor can be made conductive without particularly applying a positive voltage to the control dart electrode 5, and information can be easily read. I can do it. However, for erasing, the floating case 9 made of MoSI
Since the leakage level of electrons to the negative electrode 3 is about the same as that of polycrystalline silicon as shown in FIG. 3, there is no particular advantage. Note that erasing is done using EPR using ultraviolet irradiation.
The OM method may be used, or a smear may be injected by avalanche injection to cancel out the positive charge of the floating dart charge, similar to writing in a conventional device.
以上詳述した如く、本発明によれば１：き込み又は消去
を効率よく行なうことができ、半導体不揮発性メモリと
して極めて良好な特性を有する半導体装置を提供できる
ものである。As described in detail above, according to the present invention, 1: writing or erasing can be performed efficiently, and a semiconductor device can be provided which has extremely good characteristics as a semiconductor nonvolatile memory.
第１図は従来及び本発明の実施例におけるＦＲＯＭセル
の断面図、第２図は本発明の実施例におけるＦＲＯＭセ
ルの浮遊ダート電極から基板へのリーク電流のＩ−Ｖ特
性図、第３図は同ＦＲＯＭセルの基板から浮遊ダート電
極へのリーク電流のＩ−Ｖ特性図、第４図はＭｏ５ｉｚ
の酸化膜のオージェ分析結果を示す特性図、第５図（ａ
）及び（ｂ）はそれぞれ多結晶シリコンの酸化膜及びＮ
ｏ Ｓ ｉ Ｘの酸化膜の耐圧のヒストグラムである。
１・・・ｐ型シリコン基板、２・・・第１のダート酸化
膜、３・・・浮遊デート電極、４・・・第２０ケ゛−ト
酸化膜、５・・・制御ダート電極、６，７・・・ｎ＋型
ソース、ドレイン領域、８・・・熱酸化膜。
出願人代理人 弁理士 鈴 江 武 彦第２区
第３図
ｍFIG. 1 is a cross-sectional view of the FROM cell in the conventional and embodiment of the present invention, FIG. 2 is an IV characteristic diagram of leakage current from the floating dart electrode to the substrate of the FROM cell in the embodiment of the present invention, and FIG. 3 is the IV characteristic diagram of the leakage current from the substrate to the floating dart electrode of the same FROM cell, and Figure 4 is the Mo5iz
Figure 5 (a) is a characteristic diagram showing the results of Auger analysis of the oxide film of
) and (b) are polycrystalline silicon oxide film and N
It is a histogram of the breakdown voltage of the oxide film of o Si X. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... First dirt oxide film, 3... Floating date electrode, 4... 20th gate oxide film, 5... Control dirt electrode, 6, 7...n+ type source and drain regions, 8...thermal oxide film. Applicant's agent Patent attorney Takehiko Suzue 2nd Ward Figure 3 m
Claims (2)
介して形成されたＮ１のダート電極と、該第１のダート
電極上に第２のダート絶縁膜を介して形成された第２の
ダート電極と、積層された第１及び第２のダート電極の
両側方の基板表面に形成された基板と逆導電型の不純物
領域とを有する半導体装置において、前記第１のダート
電極をＭＳｉｘ（但し、Ｍは高融点金属、 Ｘ＞２ ）
なる組成とし、前記第２のダート絶縁膜をＭＳｉｚの酸
化膜で形成したことを特徴とする半導体装置。(1) - An N1 dirt electrode formed on a conductive type semiconductor substrate via a first dirt insulating film, and a second dirt electrode formed on the first dirt electrode via a second dirt insulating film. In the semiconductor device, the first dirt electrode has a conductivity type opposite to that of the substrate formed on the surface of the substrate on both sides of the laminated first and second dirt electrodes. (However, M is a high melting point metal, X>2)
1. A semiconductor device characterized in that the second dirt insulating film is formed of an MSiz oxide film.
特許請求の範囲第１項記載の半導体装置０(2) Semiconductor device 0 according to claim 1, characterized in that molybdenum is used as M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58213504A JPS60105279A (en) | 1983-11-14 | 1983-11-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58213504A JPS60105279A (en) | 1983-11-14 | 1983-11-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60105279A true JPS60105279A (en) | 1985-06-10 |
Family
ID=16640289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58213504A Pending JPS60105279A (en) | 1983-11-14 | 1983-11-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60105279A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
| JP2007302049A (en) * | 2006-05-09 | 2007-11-22 | Yanmar Co Ltd | Working vehicle |
-
1983
- 1983-11-14 JP JP58213504A patent/JPS60105279A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
| JP2007302049A (en) * | 2006-05-09 | 2007-11-22 | Yanmar Co Ltd | Working vehicle |
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