JPS60105224A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60105224A
JPS60105224A JP21202283A JP21202283A JPS60105224A JP S60105224 A JPS60105224 A JP S60105224A JP 21202283 A JP21202283 A JP 21202283A JP 21202283 A JP21202283 A JP 21202283A JP S60105224 A JPS60105224 A JP S60105224A
Authority
JP
Japan
Prior art keywords
diffusion
impurity
substrate
layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21202283A
Other languages
Japanese (ja)
Inventor
Kiyoto Watari
渡り 清人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21202283A priority Critical patent/JPS60105224A/en
Publication of JPS60105224A publication Critical patent/JPS60105224A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Abstract

PURPOSE:To obtain uniform impurity diffusion region through simplification of impurity coating (solid phase-solid phase) diffusion process and prevention of exfoliation of impurity coated layer by hot diffusion of impurity after forming a mask which prevents external diffusion of impurity on a semiconductor substrate having diffusion source layer pattern. CONSTITUTION:The Sb2O3 layer patterns 2a, 2b having the shape corresponding to the pattern shape of buried diffusion region are formed on a P type Si substrate and the SiO2 layer 3 is then formed thereon by the CVD method. This CVD-SiO2 film 3 presses the Sb2O3 layer patterns 2a, 2b which are the impurity diffusion sources to the substrate surface, preventing exfoliation (floating) of Sb2O3 layer patterns 2a, 2b from the surface of Si substrate 1 by the hot diffusion process. Moreover, this SiO2 film has the function as the mask which suppresses external diffusion of impurity and prevents auto-doping of impurity to the region except the region where diffused region may be formed. The material is then heated under the mixed gas ambient of O2 and N2. Thereby, Sb is hot diffused into the P type Si substrate 1 from the Sb2O3 layer patterns 2a, 2b and the N<+> type buried duffusion regions 4a, 4b are formed.

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の製造方法に係り、特に固相−固相
拡散により不純物拡散領域を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an impurity diffusion region by solid phase-solid phase diffusion.

fb) 従来技術と問題点 例えばバイポーラICの製造工程に於て、−半導体基板
に埋没拡散領域9分離拡散領域等高不純純物拡散領域を
形成する際には、固相−固相・拡散法が用いられる。
fb) Conventional technology and problems For example, in the manufacturing process of bipolar ICs, - When forming high impurity diffusion regions such as buried diffusion regions 9 isolation diffusion regions in a semiconductor substrate, the solid phase-solid phase diffusion method is used. is used.

従来固相−固相・拡散法を用いて半導体基板内に上記埋
没拡散領域1分離拡散領域等の不純物拡散領域を形成す
るに際しては、半導体基板面に不純物をブロックするた
めの例えば厚さ0.4〜0.5〔μm〕程度の熱醸化膜
を形成し、該熱酸化膜に、形成しようとする拡散領域の
平面パターンに対応する開孔を形成し、該熱酸化膜を有
する半導体基板上に不純物拡散源層(n型に於ては酸化
アンチモン5btQ、 l 5酸化燐P、0.等、p型
に於ては酸化硼素B、0. 、窒化硼素BN等ンを塗布
形成し、該基板を窒素等の不活性雰囲気中に於て100
0〜1300(℃〕程度の温度でrJr定の時間加熱し
、該不純物拡散源層から前記不純物ブO,り用酸化膜の
開孔を介して選択的に半導体基板内に不純物を拡散する
方法が行われていた。
When forming an impurity diffusion region such as the above-mentioned buried diffusion region 1 separation diffusion region in a semiconductor substrate using the conventional solid phase-solid phase diffusion method, for example, a thickness of 0.5 mm is formed on the semiconductor substrate surface to block impurities. A semiconductor substrate having the thermally oxidized film is formed by forming a thermally oxidized film of about 4 to 0.5 [μm], forming openings corresponding to the planar pattern of the diffusion region to be formed in the thermally oxidized film. An impurity diffusion source layer (for n-type, antimony oxide 5btQ, l5 phosphorus oxide P, 0.0, etc., for p-type, boron oxide B, 0.0, boron nitride BN, etc.) is coated and formed on top. The substrate was heated for 100 minutes in an inert atmosphere such as nitrogen.
A method of selectively diffusing impurities from the impurity diffusion source layer into the semiconductor substrate through the openings in the impurity oxide film by heating at a temperature of about 0 to 1300 degrees Celsius for a certain period of time. was being carried out.

しかしこの方法に於ては、不純物ブロック用酸化膜の開
孔の側面が急峻に形成されている場合、木ふ由―址鶴υ
礼百Hers執lワ怠なW l−リτ−か朋l 黙lγ
七&7不純物拡散源層の剥がれを生じ、拡散領域の不純
物0度が不均一になるという問題が生ずる。
However, in this method, if the sides of the openings in the impurity blocking oxide film are formed steeply,
Rei 100 Hers is lazy W l-ri τ-ka tomo l silent lγ
A problem arises in that the 7 & 7 impurity diffusion source layer peels off and the impurity 0 degrees in the diffusion region becomes non-uniform.

そのため従来は、耐酸化膜(通常窒化シリコン膜少をマ
スクにして半導体基板面を選択的に熱酸化するいわゆる
選択酸化法を用いて、側面がテーパ状の開孔を有するブ
ロック月収化膜を形成することによって、上記不純物拡
散源層の剥がれ防止がなされていたので、工程が非常に
複雑化していた。
Therefore, in the past, a so-called selective oxidation method was used to selectively thermally oxidize the semiconductor substrate surface using an oxidation-resistant film (usually a silicon nitride film as a mask) to form a block film with tapered openings on the sides. This prevents the impurity diffusion source layer from peeling off, making the process extremely complicated.

(C) 発明の目的 本発明は上記不純物塗布(固相−固相)拡散工程を簡略
化し、且つ不純物塗布層の剥がれを防止して均一な不純
物拡散領域を得る目的でなされたものである。
(C) Purpose of the Invention The present invention has been made for the purpose of simplifying the impurity coating (solid phase-solid phase) diffusion process and preventing peeling of the impurity coating layer to obtain a uniform impurity diffusion region.

(di 発明の構成 即ち本発明は半導体装置の製造方法に於て、不純物拡散
領域を形成するに際して、半導体基板上に拡散領域の平
面形状に対応する不純物拡散源層パターンを形成し、該
拡散源層パターンを有する半導体基板上に不純物の外方
拡散を防止するマスクを形成した後、該拡散源層パター
ンから該半導体基板内に不純物を熱拡散させる工程を有
する0とを特徴とする。
(di) Structure of the Invention That is, the present invention is a method for manufacturing a semiconductor device, in which when forming an impurity diffusion region, an impurity diffusion source layer pattern corresponding to the planar shape of the diffusion region is formed on a semiconductor substrate, and the diffusion source is The present invention is characterized by a step of forming a mask for preventing outward diffusion of impurities on a semiconductor substrate having a layer pattern, and then thermally diffusing impurities from the diffusion source layer pattern into the semiconductor substrate.

(e) 発明の実施例 以下本発明な一実施例について、第1図乃至第8図に示
す工程断面図を用いて詳細に説明する。
(e) Embodiment of the Invention An embodiment of the present invention will be described in detail below using process cross-sectional views shown in FIGS. 1 to 8.

なおこれらの図に於て同一部位は同記号で示しである。Note that the same parts in these figures are indicated by the same symbols.

本発明の方法を用いて例えはnpn型のバイポーラIC
を形成するに際しでは、第1図に示すように、例えば1
0〜30〔Ωづ〕程度の比抵抗を有するp型シリコン(
Sり基板1上にスピンコード法等の塗布手段により例え
ば厚さ0.2〔μm〕程度のn型不純物拡散源である酸
化アンチモン(SL)2(Ja)層を形成し、通常のり
ソグラフィ技術により選択エツチングを行って、該p型
S1基板1上に埋没拡散領域のパターン形状に対応する
形状を有する5b2o、層パターン2 a、2b等を形
成する。
For example, an npn type bipolar IC can be manufactured using the method of the present invention.
For example, as shown in FIG.
P-type silicon (
For example, an antimony oxide (SL) 2 (Ja) layer, which is an n-type impurity diffusion source, with a thickness of about 0.2 [μm] is formed on the S-based substrate 1 by a coating method such as a spin code method, and then by a normal glue lithography technique. Selective etching is performed to form layer patterns 5b2o, layer patterns 2a, 2b, etc. having a shape corresponding to the pattern shape of the buried diffusion region on the p-type S1 substrate 1.

次いで第2図に示すように、上記S b、 U、 J−
パターン2a、2b1kNするSi基板1上に、通常の
化学気相成長(CVD)法を用いて厚さ0,3〔μm〕
程度の例えば二酸化シリコン(SiC,)膜3を形成す
る。このCVI)−8in、膜3は不純物拡散源である
sb、o3層パターン2a、 2b等を基板面に圧接し
て、熱拡散工程による該sb、o、層パターン2a、2
b等のSi基板1面からの剥がれ(浮き上り)を防止し
、且つ不純物の外方拡散を抑えると同時に拡散領域を形
成しようとする場所以外の領域に不純物がオート・ドー
プされるのを阻止するマスク機能を有する。
Next, as shown in FIG. 2, the above S b, U, J-
Patterns 2a and 2b are formed on a Si substrate 1 with a thickness of 0.3 [μm] using a normal chemical vapor deposition (CVD) method.
For example, a silicon dioxide (SiC) film 3 is formed to a certain extent. This CVI)-8 inch, film 3 is formed by pressing the sb, o, 3 layer patterns 2a, 2b, etc., which are impurity diffusion sources, onto the substrate surface, and applying the thermal diffusion process to the sb, o, layer patterns 2a, 2, etc.
Prevents peeling (lifting) from one surface of the Si substrate such as b, suppresses outward diffusion of impurities, and at the same time prevents impurities from being auto-doped in regions other than where the diffusion region is intended to be formed. It has a mask function.

次いで上記基板を例えば醒素uJり:窒素(N2)=2
:10の混合ガス中で1250C℃)程度の温度で所定
の時間加熱し、該sb、o、層パターン2a、2b等か
らp型Si基板1内へsbを熱拡散せしめ、第3図に示
すように該p型Si基板1に例えば1o20(atm/
(+j3程度の表面濃度を有し深さ3〔μm〕程度のn
生型埋没拡散領域4a、4b等を形成する。
Next, the above substrate is subjected to a heating process, for example: Nitrogen (N2) = 2
:10 in a mixed gas at a temperature of about 1250C) for a predetermined period of time to thermally diffuse sb from the sb, o, layer patterns 2a, 2b, etc. into the p-type Si substrate 1, as shown in FIG. For example, 1o20 (atm/
(n with a surface concentration of about +j3 and a depth of about 3 [μm]
Green mold buried diffusion regions 4a, 4b, etc. are formed.

次いで通常のウェットエツチング処理等によりcVD−
8i0.膜3及びsb、o、層パターン2a、2b等を
除去し、第4図に示すように表面部に選択的にn生型埋
没拡散領域4a、4bを有すp型Sl板1が形成される
。なお前記したようにマスク膜の機能により5b2o、
層パターン2a、2b等の剥がれが防止されるので基板
面全域にわたって分散配設されるn→゛型埋没拡散領域
4a、4b等は総て均一な表面不純物濃度に形成され、
且つ埋没拡散領域以外のオート・ドーピングも防止され
る。
Then, cVD-
8i0. The film 3, sb, o, layer patterns 2a, 2b, etc. are removed, and a p-type Sl plate 1 having n-type buried diffusion regions 4a, 4b selectively on the surface is formed as shown in FIG. Ru. As mentioned above, due to the function of the mask film, 5b2o,
Since the layer patterns 2a, 2b, etc. are prevented from peeling off, the n-type buried diffusion regions 4a, 4b, etc., which are distributed over the entire substrate surface, are all formed to have a uniform surface impurity concentration.
Moreover, auto-doping in areas other than the buried diffusion region is also prevented.

次いで第5図に示すように上記埋没拡散層4a。Next, as shown in FIG. 5, the buried diffusion layer 4a is formed.

4b等が形成されたp型Si基板1上に通常のエピタキ
シャル成長法により例えば10〔μm〕程度の厚さのn
型8i工ピタキシヤル層5を形成し、次いで前述したの
と同様な方法で該エピタキシャル層5上に分離拡散領域
のパターンに対応する形状を有し、0.2Cμm〕程度
の厚さを有するp型不純物の拡散源層パターン例えは酸
化硼素CBxO5)層パターン5a、(5b、6c等を
形成し、該B、06層パターン6a、6b、6c等を有
する基板上に厚さo3〔μm〕程度のCVD−8io、
膜7を形成する。
On the p-type Si substrate 1 on which 4b, etc. are formed, an .
A type 8i epitaxial layer 5 is formed, and then a p-type epitaxial layer 5 having a shape corresponding to the pattern of the isolation diffusion region and having a thickness of about 0.2 Cμm is formed on the epitaxial layer 5 in the same manner as described above. Impurity diffusion source layer patterns (for example, boron oxide CBxO5) layer patterns 5a, (5b, 6c, etc.) are formed, and on the substrate having the B, 06 layer patterns 6a, 6b, 6c, etc., a thickness of about 03 [μm] is formed. CVD-8io,
A film 7 is formed.

次いで上記基板なOt:N、=2:10の混合カス中で
例えば1100(’C)程度で所定の時間加熱し、B、
O,層バクーンfia、6b、5c等からBをエヒタキ
ンヤル層5内に拡散せしめ、第6図に示すよう一巧一 に該n型Siエピタキシャル層p→型分離拡散領域8a
、8b、8c等を形成する。なおこの際もC’VI)−
8iU、膜7の働きにより、B2011層パターン6a
Next, the above substrate is heated for a predetermined time at about 1100 ('C) in a mixture of Ot:N, = 2:10, and B,
B is diffused from O, layers 6b, 5c, etc. into the epitaxial layer 5, and as shown in FIG.
, 8b, 8c, etc. are formed. In this case as well, C'VI)-
8iU, due to the action of film 7, B2011 layer pattern 6a
.

6b、6c等の剥がれが防止され均一な不純物濃度を有
する分離拡散領域8 ar 8 b+ 8 c等が形成
され、且つ他領域へのBのオート・ドーピングも防止さ
れる。
Separation diffusion regions 8 ar 8 b+ 8 c and the like having a uniform impurity concentration are prevented from peeling off, and auto-doping of B into other regions is also prevented.

次いで通常のウェットエツチング処理等によりCVD−
8iU、膜7及びB、05層バター76 a r 6 
ba60等を除去し、第7図に示すようにp型Si基板
1上にnl型埋没拡散領域4a、4b等を介してnm5
1:r−ビタキシャル層5が形成され、該エピタキシャ
ル層5がp→型分離拡散領域8a 、 9b 、 8c
等によって複数のトランジスタ形成領域9a、9b等に
分離されてなる被処理基板が形成される。
Next, CVD-etching is performed using normal wet etching treatment.
8iU, membrane 7 and B, 05 layer butter 76 a r 6
ba60 etc. are removed, and a nm5
1: An r-bitaxial layer 5 is formed, and the epitaxial layer 5 has p→ type isolation diffusion regions 8a, 9b, 8c.
A substrate to be processed separated into a plurality of transistor forming regions 9a, 9b, etc. is formed by the above steps.

次いで第8図に示すように、通常のバイポーラトランジ
スタの製造方法に従って各トランジスタ形成領域にn+
型コレクタ・コンタクト領域10a。
Next, as shown in FIG. 8, each transistor formation region is filled with n+
Mold collector contact region 10a.

10b等、pfMヘース領域11a、llb等、n→型
エミッタ領域12a、12b等が順次形成され、以後図
示しないが絶縁膜の形成、電極コンタクBBの形成配線
層の形成等がなされバイポーラICが完成する。
10b, etc., pfM heath regions 11a, llb, etc., n→ type emitter regions 12a, 12b, etc. are sequentially formed, and thereafter, although not shown, an insulating film is formed, an electrode contact BB is formed, a wiring layer is formed, etc., and the bipolar IC is completed. do.

以上の実施例に示したように本発明の方法は、バイポー
ラICに於ける埋没拡散領域や分離拡散領域を形成する
際に特に用いられるが、上記以外の拡散領域な固相−固
相・拡散によって形成する際0こも勿論適用される。
As shown in the above embodiments, the method of the present invention is particularly used when forming a buried diffusion region or a separate diffusion region in a bipolar IC, but it can also be used for solid phase-solid phase diffusion in diffusion regions other than those mentioned above. Of course, 0 is also applied when forming by.

(fl 発明の効果 以上実施例を用いて説明したように、本発明の方法lこ
よれば、半導体基板上lこ不純物の拡散源となる物質を
塗布して、該拡散源から半導体基板内に選択的に不純物
を拡散せしめるに際しで、複雑な工程によって該半導体
基板面にブロック用曖化膜を形成する必要がなく、シか
も拡散源の剥離が防止されるので基板面全域にわたって
均一な不純物濃度を持った拡散領域を分散形成させるこ
とができ、且つ拡散領域以外の基板面への不純物のオー
トドーピングも防止される。
(Effects of the Invention As explained above with reference to the embodiments, the method of the present invention is to apply a substance that serves as a diffusion source for impurities on a semiconductor substrate, and to spread the impurity from the diffusion source into the semiconductor substrate. When selectively diffusing impurities, there is no need to form a blocking film on the semiconductor substrate surface through a complicated process, and the diffusion source is prevented from peeling off, resulting in a uniform impurity concentration over the entire substrate surface. It is possible to disperse and form diffusion regions having the following characteristics, and auto-doping of impurities to the substrate surface other than the diffusion regions is also prevented.

従って本発明はバイポーラIC等の半導体集積回路装置
の品質及び製造歩留まりの向上及び製造1番の短縮rc
対して有効である。
Therefore, the present invention aims to improve the quality and manufacturing yield of semiconductor integrated circuit devices such as bipolar ICs, and to shorten the manufacturing process.
It is effective against

【図面の簡単な説明】 第1図乃至第8図は本発明の一実施例に於ける工程断面
図である。 図に於て、1はp型シリコン基飯、2a12bは酸化ア
ンチモン層パターン、3及び7は化学気相成長三位化シ
リコン膜、4a、4bは口→型埋没拡散領域、5はn型
シリコン・エピタキシャルL 6a。 6b、5cは酸化硼素層パターン、8a18b、8Cは
p→型分離拡散領域を示す。 第1図 第2 図 第3閏 第4Z 第S図 第に図 第77 第g因
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 8 are process cross-sectional views in one embodiment of the present invention. In the figure, 1 is a p-type silicon substrate, 2a and 12b are antimony oxide layer patterns, 3 and 7 are chemical vapor deposition triposition silicon films, 4a and 4b are mouth-to-type buried diffusion regions, and 5 is n-type silicon. -Epitaxial L 6a. 6b and 5c are boron oxide layer patterns, and 8a18b and 8C are p→ type isolation diffusion regions. Figure 1 Figure 2 Figure 3 Leap 4Z Figure S Figure 77 Factor g

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に拡散領域の平面形状に対応する不純物拡
散源層パターンを形成し、該拡散源層パターンを有する
半導体基板上に不純物の外方拡散を防止するマスク膜を
形成し、た後、該拡散源層パターンから該半導体基板内
に不純物を熱拡散させる工程を有することを特徴とする
半導体装置の製造方法。
An impurity diffusion source layer pattern corresponding to the planar shape of the diffusion region is formed on a semiconductor substrate, and a mask film for preventing outward diffusion of impurities is formed on the semiconductor substrate having the diffusion source layer pattern. 1. A method of manufacturing a semiconductor device, comprising the step of thermally diffusing impurities from a diffusion source layer pattern into the semiconductor substrate.
JP21202283A 1983-11-11 1983-11-11 Manufacture of semiconductor device Pending JPS60105224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21202283A JPS60105224A (en) 1983-11-11 1983-11-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21202283A JPS60105224A (en) 1983-11-11 1983-11-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60105224A true JPS60105224A (en) 1985-06-10

Family

ID=16615573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21202283A Pending JPS60105224A (en) 1983-11-11 1983-11-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60105224A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62160718A (en) * 1986-01-08 1987-07-16 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Manufacture of semiconductor device by diffusing dopant intosemiconductor substance from oxide of the dopant
US5126281A (en) * 1990-09-11 1992-06-30 Hewlett-Packard Company Diffusion using a solid state source
JPWO2013180244A1 (en) * 2012-05-31 2016-01-21 富士電機株式会社 Manufacturing method of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810821A (en) * 1981-07-14 1983-01-21 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810821A (en) * 1981-07-14 1983-01-21 Fujitsu Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62160718A (en) * 1986-01-08 1987-07-16 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Manufacture of semiconductor device by diffusing dopant intosemiconductor substance from oxide of the dopant
US5126281A (en) * 1990-09-11 1992-06-30 Hewlett-Packard Company Diffusion using a solid state source
JPWO2013180244A1 (en) * 2012-05-31 2016-01-21 富士電機株式会社 Manufacturing method of semiconductor device

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