JPS6010391A - Image processing system - Google Patents

Abstract

PURPOSE:To reduce remarkably the access time of an image memory by unifying the data shift operation into a serial/parallel conversion or a parallel/serial converting operation. CONSTITUTION:An image data arrangement not subject to shift correction read on a DMA data bus 16 is shown as an example from an image memory in a buffer 9. A 8-1 data selector 17 selects sequentially an output commanded among 8 outputs of the buffer 9 by an output of a counter 18 and outputs it as a video signal of a serial form data. Further, the initial value of the counter 18 is preset by a shift control data transmitted in advance from a main processor and then counts a video transmission clock, is advanced by 1 each from the value and scans sequentially the 8 outputs of the buffer 17. Thus, the data arrangement of the parallel form in the buffer 9 is shifted, e.g., by 2 bits and converted and outputted in the serial form at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Summary of the Invention] The present invention provides an image processing system that uses an image memory that can simultaneously access continuous data in both vertical and horizontal directions in an image space. It relates to an image processing method for speeding up data transfer between an input/output device and an input/output device. - Concerning an image processing method that eliminates the processing time required for data shifting by importing images during parallel conversion operations〇 [Technical Background] First, the principle of image memory, which is the subject of the present invention, will be explained. FIG. 1 shows the image space, that is, the logical space of the image memory. The pixel positions in the 0 space are the row address ε and the column address no with the upper left corner as the origin.

Yo! l) It is expressed as (i,)゛). Note that 0) and ■ in the figure.

(2), . . . are serial numbers when rask scanning is performed on all pixels in the space.

Image memory, in such an image space,
A fixed number of pixels in the row or column direction (for example, 8
or f''116) can be accessed simultaneously.

FIG. 2 shows an example of the configuration of a physical memory that implements the above image memory. In general, in order to enable simultaneous access to a group of pixels located at arbitrary positions in the vertical and horizontal directions, the bits corresponding to those pixels must be distributed and stored on different memory chips in physical memory. It won't happen. This is because only one bit of a memory chip can be accessed at a time.

For this reason, it is necessary to store the data in the image space shown in Figure 1 in each memory chip with a different predetermined shift for each row or column, and also to shift it inversely when reading it out. be.

FIG. 2 shows circular shifts in the column direction for each row of image data, sequentially 0, 1, 2, 3, . ... bit by bit, each chip 1, 2, 3, 4, . It is stored in... As a result, for example, the horizontal pixel columns 0), ■, ■, ... in Fig. 1 are distributed on each chip, as shown by the horizontal solid lines in Fig. 2. can be stored and accessed simultaneously, and the vertical pixel columns ①, 0 . ■,... are shown diagonally surrounded by broken lines in Figure 2,
They are distributed and stored on each chip and can similarly be accessed simultaneously.

However, for this reason, it is necessary to provide a data shift means between the image memory and the data bus, to perform a predetermined data shift when writing, and to perform a data shift for restoration when reading. In FIG. 3, which shows an example of the configuration of a conventional image processing system including an image memory, 1
1 is a main processing unit, 2 is a circular shifter, 3 is an image memory, 4 is a data bar 10 is a parallel/serial conversion circuit, 11 is a serial/parallel conversion circuit, and 12 is a buffer.

The circular shifter 2 performs the above-described data shift operation bidirectionally between the image memory 3 and the data bus 4 in accordance with a shift control signal from the main processing unit engineer. When the image memory and data bus 4 are configured with a width of 8 bits, for example, the shift amount is (1-10))
The remainder of /8 is given by ('+j')/8.

There are eight types of remainders, 0 to 7.

The input/output device adapters 5 and 6 are adapters for controlling DMA transfer and matching data formats between the input/output device and the image memory. The input/output device adapter 5 converts the parallel format data of the data shift 4 into serial format data using the parallel/serial conversion circuit 10.
The image is supplied to an image output device 7 such as a display or a printer. The input/output device adapter 6 converts serial format data outputted from the image input device 8 into parallel format data using a serial/parallel conversion circuit 11 and supplies the parallel format data to the data bus 4 .

In such a system, when performing DMA transfer between the image memory 3 and the input/output device adapter (5 or 6), the memory access time becomes longer due to data shifting in the circular shifter 2, and Since the data conversion operation in the input/output device adapter (5 or 6) is added in series, there is a problem that the transfer speed becomes slow. The purpose is to reduce memory access time when transferring data to and from an output device, and for this reason, we focused on the ability to integrate data shift operations into serial/parallel conversion or parallel/serial conversion operations. This eliminates the need for special time, and the configuration of the present invention furthermore eliminates the need for a group of continuous image data in either the vertical or horizontal direction specified by the row address and column address. An image memory that shifts and stores data in a distributed manner using 10,000 addresses on multiple memory blocks so that it can be accessed simultaneously, an adapter for input/output devices with serial/parallel conversion or parallel/serial conversion functions, and an input/output device. and a processing device, the input/output device adapter is provided with means for simultaneously shifting data during the serial/parallel conversion or parallel/serial conversion process, and the input/output device is connected to the image memory and the input/output device. When data is transferred via the input/output device adapter, data shifting necessary for reading or writing to the image memory is performed in the input/output device adapter.

[Embodiments of the invention]

The details of the present invention will be explained below based on examples.

FIG. 4 is a configuration diagram of a system according to an embodiment of the present invention,
This corresponds to the conventional example shown in FIG. 1, but shows a DMA transfer processing state. In the figure, l is the main processing unit, 2 circular shifters, 3 image memory, 5 and 6 adder for input/output devices, 7 image output devices such as display gray or printers, 8 image input devices, 9 and 12 is a buffer, 13 is a parallel/serial conversion and shift circuit, 14
15 represents a serial/parallel conversion and shift circuit, 15 represents a DMA controller, and 16 represents a DMA data bus.

In this example, parallel/
Serial conversion and shift circuit 13 or serial/parallel conversion and shift circuit #! r14 performs the same function as circular shifter 2 during DMA transfer.

FIG. 5 is a detailed configuration diagram of the parallel/serial conversion and shift circuit 13. In the figure, in the buffer 9, there is an array of unshifted image data read out from the image memory 3 onto the DMA data bus 16.
■■■■■ is exemplified. This data should originally have a ■ bit placed at the top position on the left end. Therefore, it is necessary to perform a 2-bit left circular shifter to restore the data. 1
The zero counter 18 is a 3-bit counter that sequentially selects two outputs and outputs them as a video signal in serial format data. The video sending clock shown in FIG. 6 is counted and the value is incremented by +1, and a scan signal 18CL for sequentially scanning the eight outputs of the buffer 17 is output.

FIG. 6 is a timing diagram of the circuit shown in FIG. 5, showing the counter output in the case of the f image data array illustrated in the fifth method and the output data selected from the buffer 9 by the 8-1 data selector 17. indicates a video signal. In this example, the initial value of the counter 18 is set to "010", so that the parallel format data array in the counter 9 receives the 2-bit left circular shifter and simultaneously receives the serial format data as shown in the figure. , and is output as a corrected data array of ■, ■, . . . , ■.

FIG. 7 is a detailed configuration diagram of the serial/parallel conversion and shift circuit 14 of the input/output device adapter 6 which performs the opposite operation to that of the input/output device adapter 5. In FIG. 0, 19 is an addressable latch circuit. The input data in the serial format is sequentially set in latches addressed by the output value of the counter 20. The figure shows an example of providing a 2-bit right circular shifter.

The counter 20 corresponds to the counter 18 in FIG. The video reception clock is counted from this initial value of 0, which corresponds to a shift amount of 2 bits, and an address signal 20α is output.

The addressable latch circuit 19 is controlled by the counter 20, and distributes the first bit of the serial format input data to an appropriate shift position on the buffer n, and sets it as parallel format data. The data set in the buffer 12 is output in parallel onto the DMA data bus 16 as 2-bit right circular shifted data and written into the image memory 3.

In this way, a circular shifter can be performed simultaneously in a parallel/serial conversion or serial/parallel conversion operation.

〔Effect of the invention〕

As described above, according to the present invention, the shift operation required for writing or reading image memory is carried out in serial/parallel mode when data is transferred between an input/output device that operates using serial format data. During conversion or parallel/serial conversion operations, n1 images are captured and processed simultaneously, which greatly reduces image memory access time and improves DMA transfer speed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an image space, FIG. 2 is an explanatory diagram showing an image arrangement on a physical memory, FIG. 3 is a configuration diagram of an example of a conventional image processing system, and FIG. 4 is an explanatory diagram of an example of a conventional image processing system. A configuration diagram of the embodiment, FIG. 5 is an embodiment diagram of the parallel/serial conversion and shift circuit, FIG. 6 is an operation timing diagram of the circuit shown in FIG. 5, and FIG. 7 is an implementation of the serial/parallel conversion and shift circuit. This is an example diagram. In the figure, ■ is the main processing unit, 2 is a circular shifter, 3 is an image memory, 5 and 6 are adapters for input/output devices, and 7
is an image output device such as a display or printer, 8
9 represents an image input device, 9 represents a buffer, 13 represents a parallel/serial conversion and shift circuit, and 14 represents a serial/parallel conversion and shift circuit. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person)

Claims (1)

[Claims] Shift υ data onto multiple memory chips by 10,000 addresses so that a group of continuous image data in the vertical or horizontal direction specified by the row address and column address can be accessed simultaneously in either direction. In an image processing system equipped with an image memory for distributed storage, an adapter for an input/output device having a serial/parallel conversion function or a parallel/serial conversion function, an input/output device, and a processing device, an adapter for an input/output device is used. A means for simultaneously performing data shifting during serial/parallel conversion or parallel/serial conversion is provided, and when data is transferred between the image memory and the input/output device via the adapter for the input/output device, the image memory An image processing method 0 characterized in that data shifting necessary for reading or writing is performed in an input/output device adapter.