JPS60103453A - Electronic computer device - Google Patents

Abstract

PURPOSE:To improve the efficiency of an electronic computer having a multi-direction branch instruction by decreasing the number of branch destinations described at an operand part of instruction one by one for each comparison of the branch conditions and performing a branching action when the coincidence is obtained with the designated conditions when the number of said branch destination is not zero. CONSTITUTION:An instruction 29 is fed to an instruction register 7 from a memory 17 by a reading action of the instruction. Then the number of branch destinations is supplied to a counter register 8 since the instruction fed next is equal to a multi-direction branch instruction. The contents of the register 8 are compared with ''0'' by a comparator 10. When the result of this comparison is ''0'', a controller 6 finishes the processing of the multi-direction branch instruction and shifts the processing to the next instruction. While the controller 6 feeds the branch instructions to a branch condition comparator 13 when the result of comparison is not ''0''. Then the branch conditions are compared with a general-purpose register 12. When no coincidence is obtained between both values, the contents of the register 8 are reduced by ''1'' by an arithmetic device 9. While the value of the branch address is fed to an arithmetic device 15 from the memory 17 when the coincidence is obtained between both values. The value of said branch address is added to a program counter 16 to obtain the address of the branch destination and to feed it to the counter 16 for branching action.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electronic computer having multi-directional branch instructions for efficiently executing programs written in a high-level language, especially programs that branch in multiple directions. It is.

Conventional configuration and its problems In recent years, PASC has been used for programming electronic computer equipment.
High-level languages such as AL, FORTRAN, and C are often used. Programs written in these languages are converted into machine language or assembly language by a translation program called a compiler and executed, but there is a large difference in ability between the current high-level language instructions and machine language instructions. In many cases, one instruction in a high-level language is translated into multiple machine languages, causing problems such as slow program efficiency and execution speed.

For this reason, the machine JrJ&gr
: Ability to improve the functionality of divider instructions, such as by providing instructions; required.

A conventional electronic computer device will be explained below.

Figure 1 shows the configuration of a conventional electronic computer device.
is a control device, 2 is an instruction register, 3 is a general-purpose register, 4
is an arithmetic unit, and 5 is a storage device.

The operation of the conventional electronic computer device shown in FIG. 1 is to take an instruction from the storage device 5 and assign this instruction to the instruction register 2, which is decoded by the control device 1 and then transferred to the arithmetic device 4. General purpose register 3. It executes instructions by controlling the storage device 6 and the like.

However, in the above configuration, when performing a multi-directional branching operation, for example, when executing a PASCAL case statement or a C language swi tah statement, this can be achieved by repeatedly writing comparison instructions and branch instructions alternately. are doing. This has resulted in problems such as an increase in the amount of programs, a complicated algorithm, and a decrease in program execution speed.

To illustrate a conventional program, an example of an electronic computer device having an instruction set shown in FIG. 2, a general-purpose register L1, and two-operand instructions will be described.

As an example, FIG. 3 shows a multi-directional branch instruction (case statement) written in PASCAL, and FIG. 4 shows a multi-directional branch instruction (5wltch statement) written in Ci language. Figure 3.

The program in Figure 4 represents the same process, with the variable o
The value of p is the value of each constant (congtl to const4)
When equal to one of the constants, the statement indicated by the matching constant is executed, and if there is no match, no processing is performed.

FIG. 6 shows an example in which the programs shown in FIGS. 3 and 4 are written using instructions for a conventional electronic computer device. The program in Figure 6 loads the value of variable Op into register L1, compares the value with each constant (constl to const4), and when they match, uses a conditional branch instruction to load each label (Labe? 1).
Branch from Labet4), and if there is no match, La
Branch to beA5. From these machine words, Figures 3 and 4
Although the multi-directional branch instruction shown in the figure is implemented, as is clear from the program in Figure 6, the repeated use of the same instruction causes problems such as an increase in program size and a corresponding decrease in execution speed. .

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and reduces the program size for processing multi-directional branch instructions in high-level languages compared to the conventional one, and reduces the burden on the compiler that generates machine language. Furthermore, it is an object of the present invention to provide electronic computing equipment that can improve program execution time.

Structure of the Invention The present invention stores the number of branch destinations described in the operand part of an instruction, decreases the stored content by 1 each time the branch condition is compared, and compares the content with O to control the result. A comparison branch control means that communicates to the device, a condition comparison means that compares the branch condition written in the operand section with the contents of the general-purpose register specified in the operand section, and conveys the result to the control device; A branch destination address subtraction means for calculating a branch destination address is provided, and a plurality of branch destination addresses, branch conditions corresponding to each branch destination, and the number of branch destinations are specified, and the branch condition and the contents of the general-purpose register are calculated. It is an electronic computer device that branches to the corresponding branch destination when the two match, and when executing multi-directional branch instructions in high-level languages, it reduces program size, improves program execution speed,
Compiler negative 41! It is possible to reduce the

DESCRIPTION OF EMBODIMENTS FIG. 6 shows the configuration of an electronic computer device in an embodiment of the present invention. In FIG. 6, 6 is a control device that controls the operation of the computer, 7 is an instruction register, 8 is a counter register that stores the number of branch destinations, 9 is a constant arithmetic device that decreases the contents of the counter register 8 by 1, and 10 is a A comparison device that compares the contents of the counter register 8 with 0 and transmits the result to the control device 6, 11 is a signal from the comparison device 61o to the control device 6, 12 is a general-purpose register, and 13 is a link between the value of the branch condition and the general-purpose register. A branch condition comparison device that compares the contents and sends the result to the control device 6; 14 is a signal from the branch comparison device 13 to the control device 6; 16 is an arithmetic device that calculates a branch destination address; 16 is a program counter; 17 is a A storage device 18 is a control signal for the control device 6 to control the electronic computer device.

The comparison branch control function is performed by counter register 8. in FIG. Constant calculation device9. It consists of a comparison device 10, a condition comparison function consists of a branch condition comparison device [13], and a branch destination address calculation function consists of an arithmetic unit 16 and a program counter 16.

The operation of the electronic computer device of this embodiment configured as above will be described below.

FIG. 7 is a flowchart 1 representing the operation of the electronic computer device of this embodiment shown in FIG. 6 at the time of a multi-directional branch instruction, and FIG. 8 is a flowchart 1. FIG.

This is a representation of the program shown in FIG. 4, and FIG. 9 shows the arrangement of the multidirectional branch instruction shown in FIG. 8 in memory, and the explanation will be made using these.

In FIG. 8, 26 CASE to 28 instructions are the multi-directional branch instructions of this embodiment, 1 and 4 following 26 CASE refer to register L1, and the number of branch conditions is 4. 27 instructions have a constant value (
constl) to the branch destination address (Labetl)
) indicates that it corresponds.

In FIG. 9, 29 indicates the instruction code indicating a multi-directional branch instruction and the reference register number, and 30 indicates the number of branch destinations (
7.31 indicates a constant value that is a branch condition (congt1 in the case of the instruction in FIG. 8), and 32 indicates the branch destination address (value 4 in the case of the instruction in FIG. 8).
et1), indicating that the branch condition and the branch destination address form a set, and that several sets of branch destinations are prepared on the memory.

The operation of the multidirectional branch instruction of the electronic computer device of this embodiment will be explained. In flowchart 1 in FIG. 7, 19 is an instruction reading operation, and an instruction 29 is input from the storage device 17 to the instruction register 7. Next, at 20, since the input instruction is a multi-directional branch instruction, the number of branch destinations (value 30 in FIG. 9) is manually entered into the counter register 8. Next, 21 compares the contents of the counter register 8 with O using the comparison device 10 and transmits the result to the control device 6. If the content of the counter register 8 is 0, the control device 6 ends the processing of the multi-directional branch instruction and moves on to the next instruction. If not O,
Proceed to step 22. 22 inputs the branch condition (value 31 in FIG. 9) to the branch condition comparison device 13, and
6) is compared with the contents of the general-purpose register 12 (register L1 in the case of the instruction in FIG. 8), and the result is transmitted to the control device 6.

When the values differ, the control device 6 decrements the contents of the counter register 8 by 1 using the constant arithmetic device 9 and returns the process to step 21. If the values are the same, proceed to step 24.

24 is the value of the branch destination address (for example, 32.3 in Figure 9).
3 etc.) from the storage device 17 to the arithmetic device 16,
It is added together with the value of the program counter 16 to obtain the actual address to branch to. Next, the processing of 26 is performed by the arithmetic unit 16.
A branch is performed by inputting the actual branch address divided by 2 to the program counter 16, thereby performing a multi-way branch. As is clear from comparing the programs shown in FIG. 6 and FIG. 8, the number of program steps in the program used in this embodiment is 7J (7J) in FIG.

Program size has also decreased.

As described above, according to the present embodiment, the constant operation reduces the contents of the counter register 8 by 1 each time the branch condition is compared with the counter register 8 that stores the number of branch destinations written in the operand part of the instruction. Device 9 and counter register 8
A comparison device 10 compares the contents of 0 with 0 and transmits the result to the control device 6, compares the branch condition written in the mapper land section with the contents of the general-purpose register 12 specified in the operand section, and transmits the result to the control device 6. Branch condition comparison device 1
3, and an arithmetic unit 13 that calculates the branch destination address written in the operand section and inputs it to the program counter 16, and specifies a plurality of branch destination addresses, corresponding branch conditions, and the number of branch destinations. By actually executing a multi-directional branch instruction that branches to the corresponding branch destination when the branch condition matches the contents of the general-purpose register 12, the number of program steps and program size can be reduced and the program execution speed can be improved accordingly. can be achieved.

Effects of the Invention The electronic computer device of the present invention memorizes the number of branch destinations described in the maybeland part of an instruction, decreases the stored content by 1 each time the branch conditions are compared, and compares the stored content with 0. A comparison branch control means for transmitting the result to the control device, a condition comparison means for comparing the contents of the branch condition written in the operand section and the general-purpose register specified in the operand section, and transmitting the result to the control device; It is equipped with a branch destination address S1 calculating means for calculating the address of the described branch destination, and specifies a plurality of branch destination addresses, corresponding branch conditions, and the number of branch destinations so that the branch conditions and the contents of the general-purpose register match. By executing an instruction to branch to the corresponding branch destination when executing a program, the program size can be reduced compared to before, the burden on the compiler that generates machine language can be reduced, and machine language for high-level language instructions can be realized in hardware. In particular, the execution time of L reprogramming can be reduced by 1:0, which has a great practical effect.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional electronic computer device, Fig. 2 is a diagram showing an instruction input of a conventional electronic computer device, and Fig. 3 is an example of a multi-directional branch instruction written in PASCAL. Figure 4 is a diagram showing an example of a multi-directional branch instruction written in C language, and Figure 6 is a diagram showing an example of a multi-directional branch instruction written in C language. FIG. 6 is a block diagram of an old electronic t1 machine device according to an embodiment of the present invention, and FIG. 7 is a diagram showing the electronic side computer device of this embodiment, which is a smaller version of FIG. 6. A flowchart showing the operation at the time of a multi-directional branch instruction, Figure 8 is similar to Figure 3. 84 is a diagram showing a program in which the multi-directional branch instruction of FIG. 84 is written using the multi-directional branch instruction of the electric r.
FIG. 9 is a diagram showing the arrangement of the multi-directional branch instruction storage device 6''2 of the electronic i-1 computer device of this embodiment, which is smaller than that shown in FIG. 8. 6... Control device, 7... Instruction register, 8... Counter register, 9... Constant arithmetic unit FI', 10... Comparison device, 12...
... General purpose register, 13 ... Branch condition comparison device, 16 ... Arithmetic device, 16 ... Program counter, 17 ... Storage device. Name of representative: Patent attorney Toshio Nakao and one other person 2 Figure 3 Figure 4 PASCAL C Sill 7 Figure 81! l Figure 9

Claims (1)

[Claims] Comparison branch control means that stores the number of branch destinations described in the operand part of an instruction, decrements the stored content by 1 each time the branch conditions are compared, compares the content with 0, and transmits the result to the control device. A condition comparison means that compares the branch condition written in the operand section with the contents of the general-purpose register specified in the operand section and conveys the result to the control device, and a branch that calculates the address of the branch destination written in the operand section. A destination address dividing means is provided, and a plurality of branch destination addresses, a branch condition corresponding to each branch destination, and the number of branch destinations are specified, and when the branch condition and the contents of the general-purpose register match, the corresponding branch destination is specified. To branch out! Electronic t1 computer device on standby.