JPS6010299Y2 - Signal interference prevention device - Google Patents
Signal interference prevention deviceInfo
- Publication number
- JPS6010299Y2 JPS6010299Y2 JP1982086491U JP8649182U JPS6010299Y2 JP S6010299 Y2 JPS6010299 Y2 JP S6010299Y2 JP 1982086491 U JP1982086491 U JP 1982086491U JP 8649182 U JP8649182 U JP 8649182U JP S6010299 Y2 JPS6010299 Y2 JP S6010299Y2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- prevention device
- signal interference
- contact
- motherboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Combinations Of Printed Boards (AREA)
Description
【考案の詳細な説明】
本考案は、カードエツジ・コネクタを用いてプリント基
板上の導電パターンに信号を伝送する場合に生ずる信号
干渉を防止する装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for preventing signal interference that occurs when a card edge connector is used to transmit signals to conductive patterns on a printed circuit board.
従来、プリント基板上の導電パターンで電子回路を構成
する場合、外部との信号授受には、カードエツジ・コネ
クタが使用されているけれども、微小信号の伝達または
大きなレベルの信号を伝送する場合には、基板またはコ
ネクタの絶縁性やシールド構造的に最適であるとはいえ
なかった。Conventionally, when configuring electronic circuits using conductive patterns on printed circuit boards, card edge connectors have been used to exchange signals with the outside, but when transmitting minute signals or large-level signals, It could not be said that the insulation properties of the board or connector and the shielding structure were optimal.
そのため、プリント基板にスリットを設けたり、または
該基板上に同軸コネクタを装着して導電パターンとは列
配線にしていたが、スリットの縁面でのリークは防止で
きないし、又、組立がめんどうである。For this reason, slits were provided on the printed circuit board, or coaxial connectors were mounted on the board to connect the conductive pattern to the column wiring, but leakage at the edges of the slits could not be prevented, and assembly was troublesome. be.
したがって、本考案は微小電流の導電路に最適なガード
付プリント基板を提供せんとするものである。Therefore, the present invention aims to provide a printed circuit board with a guard that is optimal for a conductive path for minute currents.
以下図面を用いてこれを説明する。第１図は本考案装置
の一実施例による正面図、第２図はその側面図である。This will be explained below using the drawings. FIG. 1 is a front view of one embodiment of the device of the present invention, and FIG. 2 is a side view thereof.
両図において、１０はプリント基板、２０はマザーボー
ド２８上に装着されたカードエツジ・コネクタである。In both figures, 10 is a printed circuit board, and 20 is a card edge connector mounted on a motherboard 28.
１２は前記プリント基板１０上に配設された導電パター
ン、１４はガードパターンで、それビれのパターンはコ
ネクタ２０を経てマザーボード２８の各端子と電気的に
接続される。12 is a conductive pattern disposed on the printed circuit board 10, 14 is a guard pattern, and the pattern on the edge is electrically connected to each terminal of the motherboard 28 via a connector 20.
１６はその一端にスプリング・ピン１８及びこれに電気
的に接続された導線１７を具えた可動接触子で、該接触
子１６は絶縁材のケースを介して前記ガードパターン１
４上に装着されている。A movable contact 16 has a spring pin 18 at one end and a conductor 17 electrically connected to the spring pin 18, and the contact 16 is connected to the guard pattern 1 through an insulating case.
It is mounted on 4.
２２は前記スプリング・ピン１８に対向接触する固定接
点で、該接点２２は絶縁材２４及び導電材の支持部材２
５を経て前記マザーボード２８に固着されている。Reference numeral 22 denotes a fixed contact that contacts the spring pin 18 oppositely, and the contact 22 is connected to an insulating material 24 and a supporting member 2 made of a conductive material.
5 to the motherboard 28.
なお、２６は固定接点２２をとり巻くガード部材で、こ
れは、前記導電部材材２５を介してマザーボード２８の
パターン２７に接続され、更にコネクタ２０を経て前記
基板１０のガードパターン１４に橋絡されている。Note that 26 is a guard member surrounding the fixed contact 22, which is connected to the pattern 27 of the motherboard 28 via the conductive member 25, and further bridged to the guard pattern 14 of the board 10 via the connector 20. ing.
なお、固定接点２２に対する外部導線は省略しである。Note that an external conductor for the fixed contact 22 is omitted.
しかしてプリント基板１０を矢印ｍ方向に移動してコネ
クタ２０に挿着すれば、可動接点１８と固定接点２２と
は圧接される。When the printed circuit board 10 is moved in the direction of arrow m and inserted into the connector 20, the movable contacts 18 and the fixed contacts 22 are brought into pressure contact.
すなわち、微小信号の導電路としてプリント基板１０か
ら絶縁材を介して隔離されている可動接触子１６を利用
すれば、基板上の導電パターン１２との相互干渉は完全
に除去され、しかもその脱着操作は極めて簡単であるか
ら、実用に供して効果大である。In other words, by using the movable contact 16 isolated from the printed circuit board 10 via an insulating material as a conductive path for minute signals, mutual interference with the conductive pattern 12 on the circuit board can be completely eliminated, and moreover, its attachment/detachment operation is easy. Since it is extremely simple, it is very effective in practical use.
第１図は本考案の一実施例による装置の正面図、第２図
はこの側面図である。
１０ニブリント基板、１２：導電パターン、１４ニガー
ドパターン、１６：可動接触子、１８ニスプリング・ピ
ン、２０：コネクタ、２２：固定接点、２４：絶縁材、
２６：ガード部材、２８：マザーボード。FIG. 1 is a front view of an apparatus according to an embodiment of the present invention, and FIG. 2 is a side view thereof. 10 Niblint board, 12: conductive pattern, 14 Nigard pattern, 16: movable contact, 18 Nispring pin, 20: connector, 22: fixed contact, 24: insulating material,
26: Guard member, 28: Motherboard.
Claims (1)
と該基板が装着されるコネクタを具えたマザーボードと
より成る信号伝送装置において、前記基板のガードパタ
ーン上に絶縁材を介して装着された可動接触子と、前記
マザーボード上に前記可動接触子に対接する固定接点を
設けてなる信号の干渉防止装置。A signal transmission device comprising a printed circuit board having a conductive pattern and a guard pattern, and a motherboard having a connector to which the board is mounted, a movable contact mounted on the guard pattern of the board via an insulating material; A signal interference prevention device comprising a fixed contact on the motherboard that is in contact with the movable contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982086491U JPS6010299Y2 (en) | 1982-06-10 | 1982-06-10 | Signal interference prevention device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982086491U JPS6010299Y2 (en) | 1982-06-10 | 1982-06-10 | Signal interference prevention device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58187990U JPS58187990U (en) | 1983-12-14 |
| JPS6010299Y2 true JPS6010299Y2 (en) | 1985-04-09 |
Family
ID=30095287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982086491U Expired JPS6010299Y2 (en) | 1982-06-10 | 1982-06-10 | Signal interference prevention device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010299Y2 (en) |
-
1982
- 1982-06-10 JP JP1982086491U patent/JPS6010299Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58187990U (en) | 1983-12-14 |
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