JPS60102064A - Generating circuit of profile correcting signal - Google Patents

Abstract

PURPOSE:To obtain horizontal and vertical profile correcting signals at the same time by using a semiconductor delay element so as to operate the amount of delay during one horizontal scanning period thereby applying addition and subtraction of delayed output. CONSTITUTION:An input signal (OH signal) is delayed by the semiconductor delay element 10 such as CCD, the input signal and a 2H delay signal are added at an adder 10 and also an output of the adder 10 and a 1H delay signal are subtracted at a subtractor 30 and outputted as a profile correction signal. Since the drive pulse number of the semiconductor delay element 10 outputted from a drive circuit 40 is taken as 454, which is less than the transfer stage number 455 of the semiconductor delay element by one, the phase of the output signal is shifted to the input signal by 1/455 at 1H delay and the 1H delay output and the 2H delay output are added and subtracted in this way, then the profile correction signal output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a contour correction signal circuit for television signals.

Conventionally, this type of contour correction signal generation circuit includes a signal delay circuit 1. as shown in FIG. Horizontal contour signal generation circuit 2, addition circuit 3. It consists of a subtraction (b) circuit 4 and an addition circuit 5. Each of the % delay circuits 1 delays the signal by a time corresponding to one horizontal scanning period of the television signal, and the 1d delay circuit 1111! The signal obtained through i1 (IH(i
i-yi) and the signal delay circuit 2iII! No. 46 (referred to as 2H signal) obtained through J is in the same phase. A vertical contour correction signal can be obtained by adding the input signal (0)1 signal) and the 2H signal in an adder circuit 3, and subtracting it from the IH multiplied signal in a subtracter circuit 4. In addition, 1) ((') A horizontal contour correction signal can be obtained from the horizontal contour tMa positive signal d signal generation circuit 2. The vertical and horizontal contour correction signals are incremented by the adding circuit 5, In this way, in conventional circuits, independent vertical and horizontal contour correction signal generation circuits are used to control the contour correction signal, resulting in a complicated circuit configuration and a large number of component parts. There was a drawback that there were many.

Furthermore, there is a drawback that a portion where the vertical and horizontal contour correction signals are superimposed is generated, and the contour correction signal has a high level only in that portion.

However, an object of the present invention is to provide a contour correction signal generating circuit which has a simple structure and excellent characteristics, eliminating the drawbacks of the conventional circuit.

According to the present invention, when two semiconductor delay elements are used in a signal delay circuit and each element delays one horizontal scanning period, the delay amount of the semiconductor delay elements is manipulated to achieve 0H1IH.
, 2H signal by shifting the phase and outputting it.
Horizontal by adding H and 2H signals and subtracting IH double signal (OH + 2H) signal.

A television signal contour correction signal generation circuit that can simultaneously obtain a vertical contour correction signal is obtained.

In the present invention, the driving pulses of the semiconductor delay elements are not bundled as much as the number of transfer stages of the semiconductor delay elements per horizontal scanning period, and the outputs of the semiconductor delay elements are added and subtracted. Contour correction signals are obtained at the same time.

Next, the present invention will be described in detail with reference to the drawings of an embodiment of the present invention. Referring to FIG. 2, a first embodiment of the present invention includes a semiconductor delay element 10 such as a COD, an adder circuit 20 connected to the semiconductor delay element 10, and a subtraction n circuit 30 connected to the adder circuit 20. and a drive circuit 4o for the semiconductor delay element 1o. In this case, the semiconductor delay element 1o is a CCD.
The number of transfer stages is 455, and the transmission frequency is 7.16 Mz).

The drive circuit 40 creates drive pulses for the semiconductor delay element 10. The adder circuit 20 is a circuit for adding the input signal (0) 1 times the signal) and the signal delayed 92 times by the semiconductor delay element 10 (2H signal). The subtraction circuit 30 doubles the signal (1.H signal) delayed 91 times by the semiconductor delay circuit 10, and subtracts the sum of the previous 01 (and 2H signal).
One wheel with i! Ai...You can obtain the title of Seihaku.

In the present invention, 1 water 1,000) 12 half of the inspection period is 2! The number of drive pulses of the y-body slow IA resistor 10 is set to the number of transfer stages of the semiconductor delay element, 455.
The number is 454, which is one less. Therefore, as shown in FIG. 3, the output signal of the semiconductor delay element will have a phase shift of 1/455 with respect to the input signal A due to the IH delay.
It will look like B. The 2H signal that has passed through one more stage of delay element is again shifted in phase by 1/455 and becomes like C. The signals A and C in FIG. 3 are added in an adder circuit 20 and the 2B signal is subtracted in a subtracter circuit 30 to obtain the signal in FIG. 3E. The signal in Figure 3 E shows the horizontal period, but when looking at the vertical period, the respective delay amounts in Figure 3 B and C are IH and 2H for A, and H/455 is replaced with IH. Become something. Therefore, a contour correction signal can be obtained even in the vertical period. When imaging a wind pattern, conventional contour correction circuits create horizontal and vertical contour correction signals separately, and when mixed, superimposed portions of both appear at the four corners, and only the brightness I of that portion becomes high. Ta. On the other hand, in the method according to the present invention, horizontal and vertical contour correction signals are created simultaneously and all have the same signal level.

As explained above, the present invention uses semiconductor delay elements to operate the contour correction signal circuit by manipulating the delay amount for one horizontal scanning period, thereby simultaneously creating horizontal and vertical contour correction signals. This has the effect of simplifying the circuit configuration, reducing the price of the television camera device, and creating a contour correction signal with good clarity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional contour correction signal generation circuit, FIG. 2 is a non-nap block diagram of the 1'3A tooth row of the present invention, and FIG. 3 is a waveform diagram of the main part of FIG. 2. In the figure, 10... semiconductor delay element, 20...
... Addition circuit, 30 ... Subtraction circuit, 40. River.
・Drive circuit.ゝL-

Claims (1)

[Claims] A contour correction signal generation circuit comprising a semiconductor delay element having a delay amount corresponding to one horizontal period of a television signal, an addition circuit connected to the semiconductor delay element, and a subtraction circuit,
1. A contour correction signal generation circuit for a television signal, comprising a drive circuit that makes the number of drive pulses for a semiconductor delay element in one horizontal scanning period less than the number of transfer stages of the semiconductor delay element by at least one ray.