JPH04159821A - Pwm type d/a converter - Google Patents

Abstract

PURPOSE:To improve the resolution of the this converter without changing the frequency of a clock signal by changing at least one of the outputs of four PWM converters whenever an input signal changes by one unit. CONSTITUTION:Four PWM converters 2-5, analog adders 7 and 8, an analog subtracter 9, and a smoothing circuit 10 are provided. Then, by changing one of the pulse widths of the plural PWM converters whenever input signals change by one unit, the pulses of the PWM converters 2 and 3 belonging to the 1st group are widened in width proportionally to the input signals and the pulses of the converters 4 and 5 belonging to the 2nd group are made to become the inverted signals of the input signals. In other words, the output of this D/A converter is changed against a change in the input signals by adding the outputs of the converters 2 and 3 belonging to the 1st group and subtracting the analog sum of the converters 4 and 5 belonging to the 2nd group. Therefore, the resolution of this D/A converter can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PWM type D/A converter used for demodulating PCM audio signals that require high speed and high accuracy.

[Conventional technology]

A D/D converter that uses multiple PWM circuits to convert digital signals that require relatively high speed and high accuracy into analog signals.
A converter is known. Figure 4 shows such a conventional P
FIG. 2 is a circuit diagram showing an example of a WM type D/A converter. In this figure, digital signals are applied to four PWM converters 21-24 via an input terminal 20 as shown. PWM
The converter 21 outputs a signal with a pulse width corresponding to the level of input data, and the PWM converter 22 outputs a waveform obtained by inverting this output.

Also, the PWM converter 23 is a PWM converter 21 which is the complement of the PWM converter 21.
The waveform and PWM converter 24 outputs the inverted waveform. Further, the same clock signal is applied to these PWM converters 21 to 24 from an input terminal 25.

FIG. 5 shows that when a digital signal that changes from +2 to -2j is input as input data, each PWM converter 21
-24 output waveforms are shown by solid lines. The pulse width of the data before that is shown by the dotted line, and the input data is 1
When the pulse width changes by 1, the pulse width changes as shown by the solid line in the figure. Now, the outputs of the PWM converters 21 and 22 are applied to an analog subtracter 26 for subtraction, and similarly the outputs of the PWM converters 23 and 24 are applied to an analog subtracter 27 for subtraction. The outputs of these subtracters 26 and 27 are further supplied to a subtracter 28 for subtraction. Therefore, PW
If the outputs of the M converters 21 to 24 are respectively E-H, the analog subtracter 28 sends the output to the output terminal 30 via the smoothing circuit 29.
The signal applied to is (E-F)-(GH). FIG. 5(6) shows the output waveform of this analog subtracter 28.

By configuring the analog subtracter in this way, in-phase noise can be removed, and by performing two stages of analog subtraction, the signal level can be increased.

In such a conventional PWM type D/A converter, as shown in FIG. 6 showing changes in the output of the PWM converter 21, if the period of the input signal is T and the period of the clock signal is t, the resolution is as follows. It is shown by the formula.

k= (T/ (2xt)) -1 In the case of FIG. 5, since T/l is 12, the resolution is 5, and five types of values can be output as shown in FIG.

[Problem to be solved by the invention]

However, conventional PWM type D/A converters have the disadvantage that when higher speed conversion or higher resolution is required, a very high frequency clock signal is required, making stable oscillation difficult. Another disadvantage is that the use of a high frequency clock signal increases unnecessary radiation, which may interfere with other equipment.

The present invention was made in view of the problems of the conventional PWM type D/A converter, and it is possible to convert even a low frequency clock signal into an analog signal with high resolution, and also eliminates unnecessary radiation. A technical problem is to provide a PWM type D/A converter with a small number of PWM type D/A converters.

(Means for Solving If! Problem) The present invention provides at least four PWM converters each receiving the same digital input signal and consisting of two or more first groups and two or more second groups, and a first group of PWM converters. A first analog adder that adds the outputs of the PWM converters of the second group, respectively, a second analog adder that adds the outputs of the second group of PWM converters, and a second analog adder that adds the outputs of the second group of PWM converters, respectively. The PWM converter is equipped with an analog subtracter that subtracts the output of the analog subtracter, and a smoothing circuit that smoothes the output of the analog subtracter. The first group of PWM converters outputs a PWM signal with a wide pulse in response to the rise of the input signal, and the second group of PWM converters outputs a PWM signal that is essentially an inverted signal. It is characterized by:

[Effect]

According to the present invention having such characteristics, the input signal is 1
Every time the unit changes, the pulse width of any one of the plurality of PWM converters changes. The first group of PWM converters widens the pulse width in proportion to the input signal, and the second group of PWM converters generates the inverted signal.
By adding the outputs of the WM converters and subtracting them from the analog added value of the second group of PWM converters, the output is changed in response to changes in the input signal, and the resolution is improved.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a PWM type D/A converter according to an embodiment of the present invention. In this figure, input terminal 1 is an input terminal to which a digital signal is applied, and four PWM converters Connected to input terminals 2 to 5. Each PWM
The same clock signal is supplied to the converters 2 to 5 from the input terminal 6. The PWM converters 2 to 5 are converters that sequentially change the pulse width of the output every time the input signal changes by one unit. It is assumed that the PWM converters 2 and 3 change their pulse widths to become wider as the input data changes from negative to positive, and the PWM converters 4 and 5 output inverted outputs. PWM converter 1 converts input data into PW
M number of converters, in this example, the output is changed when the remainder is O when divided by 4, and the PWM converter 3.4.5
It is assumed that the output is changed when the remainders are 1, 2, and 3, respectively. Now, the outputs of PWM converters 2 and 3 are given to an analog adder 7 and added. The outputs of the PWM converters 4 and 5 are also applied to an analog adder 8 and added together.

The outputs of analog adders 7 and 8 are applied to an analog subtracter 9. The analog subtracter 9 subtracts the output of the analog adder 8 from the output of the analog adder 7,
The output is given to a smoothing circuit 10. The smoothing circuit 10 smoothes the input signal, converts it into an analog signal, and outputs it from the output terminal 11.

Next, the operation of this embodiment will be explained with reference to time charts. FIG. 2(a) shows digital signals from "+2" to "-2" of the input data applied to the input terminal 1. Now, it is assumed that when the input data is +2, the PWM converters 2 to 5 output the signals shown in FIG. 2(C) to 5, respectively. Then, when the input data is in a period of "-2", the analog adders 7 and 8 perform PWM control, respectively.
Since the outputs of converters 2, 3 and 4.5 are added and subtracted by the analog subtracter 9, the second
The output shown in the figure (powder) is obtained.And the input data is +1
2, only one of the four PWM converters 2 to 5, for example, the PWM converter 4 as shown in the figure, changes as shown in FIG. 2(e). Here, Figure 2 (C) ~ (
In e), the broken line indicates the previous state of the input level, indicating that only the output of the PWM converter 4 has changed. Similarly, input data is rO'', r-IJ, '-2J
As this changes, the PWM converters 2, 5.3 each change one cycle before that as shown by the broken lines.

Therefore, the subtracter 9 obtains the signal shown in FIG. 2(g),
By smoothing this signal with the smoothing circuit 10, it can be converted into an analog signal. Now, in this embodiment, when the input signal changes by one, only one of the four PWM converters changes. Therefore, as shown in FIG. 3, the resolution of the PWM converter is expressed by the following equation, where T is the period of the input signal, t is the period of the clock signal, and n is the number of PWM converters.

k= (T/ (2Xt)-1) XnFor example, T/l is 12. When n is 4, k is 20, and 20 types of values can be output. The PWM output in FIG. 3 shows the resolution of 20, and by smoothing the outputs of the four PWM converters, analog signals of 20 different levels can be output.

Although this embodiment is configured using four PWM converters, it can also be configured using an even larger number of PWM converters. In this case as well, assuming that the number of PWM converters is n, the output width of each PWM converter changes each time the input signal changes by n.

Then, as shown in FIG. 2, P added to the →- side of the subtractor 9
The output of the WM converter increases the pulse width according to the value of the input data as shown in FIG. By configuring to generate an inverted output, a high-resolution D/A converter can be constructed. Also, since a subtracter is used, common mode noise can be significantly reduced.

〔Effect of the invention〕

As described above in detail, according to the present invention, high resolution can be achieved without changing the frequency of the clock signal. Further, when the resolution is the same as that of the conventional example, the clock frequency can be lowered, and unnecessary radiation can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of a PWM conversion type D/A converter according to an embodiment of the present invention, Fig. 2 is a waveform diagram showing waveforms of each part of this embodiment, and Fig. 3 is a waveform diagram showing the waveform of each part of this embodiment. Fig. 4 is a block diagram showing the configuration of a conventional PWM type D/A converter, Fig. 5 is a waveform diagram showing its operation, and Fig. 6 is a conventional D/A converter. FIG. 2 is a conceptual diagram showing an example of resolution of a device. 2~5・----PWM converter, 7,8・----
1-analog adder, 9--analog subtracter, 10--smoothing circuit. Patent applicant: Matsushita Electric Industrial Co., Ltd. Agent: Yoshiki Okamoto, patent attorney Figure 1 7.8 Analog adder 9 - Analog subtractor Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] (1) At least four PWM converters each receiving the same digital input signal and consisting of two or more first and second groups, and a first analog that adds the outputs of the first group of PWM converters, respectively. an adder, a second analog adder that adds the outputs of the second group of PWM converters, and an analog subtracter that subtracts the output of the second analog adder from the output of the first analog adder. and a smoothing circuit that smoothes the output of the analog subtracter,
The WM converters change the output of any one PWM converter in response to a one-unit change in the input signal, and the first group of PWM converters has a wide pulse in response to a rise in the input signal. A PWM type D/A converter, characterized in that the PWM signal and the second group of PWM converters each output a PWM signal that is substantially an inverted signal.