JPS60101799A - Two-stage sample/hold circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption through simple constitution by driving the current source of a buffer circuit only at the timing of plural sampling pulses. CONSTITUTION:Depletion type FETs 111 and 131 are used and a sampling pulse is supplied to the gate of an enhancement type FET141. Further, a depletion type FET151 is used and a sampling pulse phiSP' is supplied to the gate of an enhancement type FET191 provided in parallel to the FET141. Other stages are constituted similarly. Then, the FETs 141 and 191 are off while no sampling pulse is supplied, and no current flows. When a sampling pulse is supplied, the FETs 111, 131, and 151 transfer a display signal efficiently and the FETs 141 and 191 operate in a saturation area and serves as constant current sources. Consequently, the current value in sampling is equalized to that in reading operation and the pulses phiSP' and phiSP are used as they are.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-stage sample-and-hold circuit used for parallel input, serial to voltage conversion, and the like.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, a two-stage sample bold circuit is used as an input circuit for a line-sequential drive display device. In the figure, the display signal supplied to the input terminal (1) is connected to a first (initial stage) sample and hold circuit (21),
(22)...(2p) K' is supplied, and the first sampling pulse φ51 . φS2...φ8
．． are the respective sample and hold circuits (2,) to (2p
) K is supplied.

The signals sampled and held by these sample and hold circuits (21) to (2p) are respectively supplied to second sample and hold circuits (41) to (42)...(4p) IC, and sampling pulses φ5. A second sampling pulse φ formed at a later timing is supplied to the sample and hold circuits (41) to (4p).

As a result, the display signal supplied to the input terminal (1) K serially is sent to the sample and hold circuits (21) to (2p).
sample and hold circuits (41) to (4).
p) is synchronized and taken out. Note that p corresponds to the number of pixels Fca in one line.

In such a circuit, the specific configuration of the circuit has conventionally been 5 as shown in FIG. That is, the FET (11,
) and a capacitor (121) are provided, and the input terminal (1
) is connected to the source of F ET (111).

The drain of this FBT (11+) is the capacitor (12+)
) is connected to the power supply terminal VSSK. Also, FET (
The drain of the FBT (111) is connected to the gate of the FgT (13t) with a source follower configuration constituting the buffer circuit (51), and the source of this FBT (13x) is connected to the power supply terminal VD.
D K contact M satt, Tovyka FET (14t)
No'/ - Connect power terminal VSSK through strain b
It will be done.

Furthermore, an FF:T (15+) and a capacitor (16t) constituting the second sample and hold circuit (41) are provided, and the drain of the FET (131) is connected to the FET (15+).
, ), and the drain of this FBT (151) is connected to the power supply terminal v8S through a capacitor (161). In addition, the drain of the FET (15*) is connected to the buffer circuit (6).
)FET connected to the gate of (17t), and FET with
The source of (171) is connected to the power supply terminal ■DD", and the drain is connected to the power supply terminal v8s through the source and drain of FET (181). Then, the output terminal (71) is led out from the drain of FET (17t). .

This circuit is provided in p stages. And each F B i' (
11J) +(112)...(lip) Noke-)
K sampling pulses φ811φ32...”
φ, p are supplied, FET (151) I (152)...
・Sampling pulse φ3 common to the gate of (15p)
．． is supplied.

As a result, the signals sequentially sampled and held and converted to rHJ are sent to the output terminals (7t), (72)... (7p
) K is taken out.

However, in this circuit, FET (14+), (1
4z)...(14p) and (181), (182
)...(18p) are each used as a constant current source. Therefore, constant voltages of VDC and vDc' are supplied to each gate, so that a constant current is passed through the circuit. Therefore, a predetermined amount of power is consumed for each stage, and as the number of stages increases, the power consumption becomes extremely large.

OBJECTS OF THE INVENTION In view of the above point K, the present invention aims to reduce power consumption with a simple configuration.

Summary of the Invention The present invention includes a first sample and hold circuit that samples and holds a first sampling pulse signal, and a signal sampled and held by the first sample and hold circuit. A two-stage sample bold circuit is connected to a second sample bold circuit that performs sample bold based on the m,2 sampling pulse generated after a predetermined time has elapsed from the generation of the sampling pulse, via a buffer circuit configured with an emitter follower or a source bore. A two-stage sample and hold circuit characterized in that the current source of the buffer circuit is driven only at the timing of the first and second sampling pulses, and according to this K, the power consumption is reduced with a simple configuration. can be reduced.

In FIG. 4, the FET (lit) and (13+) are configured as a depletion type, and the sampling pulse φ8□ is configured as an enhancement type FET (141).
f) r goo) K supply. Further, the FET (15*) is constructed as a depletion type, and one sampling pulse φsp' is supplied to the gate of an enhancement type FET (19,) provided in parallel with the PET (14,).

Kf and If are similarly formed for each stage thereafter.

In this circuit, FETs (1j+) and (191) are off during the period when there is no sampling pulse, and no current flows. When a sampling pulse is supplied, depletion type FETs (11+) and (13t) are activated.

(15w) efficiently transfers the display signal, and this pulse causes the FETs (144) and (19+) to operate in the saturation region, making them a constant current source. As a result, the circuit configuration is the same as the conventional one at the time of sampling and reading.

Therefore, the power consumption of this first sample and hold is 1 is 1 where the number of stages is p, which is significantly different from the conventional one.

Also, in this case, busy, ■P1T (14t) and (19t)
By making the sizes of the sampling pulses φ5 and . ' φ8. can be used as is.

Sample and hold is performed in this way. According to this circuit, the constant current source of the buffer circuit is turned on with a sampling pulse, and KT is held only during sampling and output.
Since the L current is made to flow, the constant current source used in the buffer circuit of the first sample hole hold circuit is constantly driven in order to obtain a continuous output, compared to the conventional one.

Furthermore, if a depletion type FET is used, signals can be transferred efficiently.

However, if the above-mentioned circuit is used simultaneously with a digital V-transition type enhancement type F'ET, the number of process steps will increase. Therefore, as shown in FIG. 141), (19
1) operates in the saturation region, F B T
(11,), (13s).

(151) can be of the enhancement type, and the sampling pulse φ5. As φ5. can be used.

Furthermore, in FIG. 6, the sampling pulse φ50. φ
8. From the trap of combining with the OR circuit (24,), FE
It is also possible to press one T (14□) or (191).

In this case, the OR circuit (241) is specifically configured as shown in FIG.
If t) is chosen to work in the saturation region, the FET (111
), (131).

(151) does not have to be of the depression type.

Effects of the Invention According to the present invention, power consumption can be reduced with a simple configuration.

[Brief explanation of drawings]

Figures 1 and 2 show 59 of the two-stage sample and hold circuit.
3 is a configuration diagram of a conventional circuit, FIG. 4 is a configuration diagram of an example of the present invention, and FIGS. 5 to 7 are diagrams for explaining other examples. (1) is an input terminal, (2) is a first sample and hold circuit, (3) is a scanning circuit, (4) is a second sample and hold circuit, (5) * (G) is a buffer circuit, (7) is the output terminal. Agent Associate Page ゛-゛Same Hide Matsukuma Moriha 1 ゛Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] a first sample-and-hold circuit that samples and holds a signal using a first sampling pulse; and a first sample-and-hold circuit that samples and holds a signal using a first sampling pulse; In a two-stage sample and hold circuit, the current source of the buffer circuit is connected to the sample and hold circuit of g2, which performs a sample hole route from the sampling pulse of G2, through a buffer circuit configured with an emitter follower or a second follower. A two-stage sample and hold circuit characterized in that it is driven only at the timing of the second sampling pulse.