JPH0414440B2 - - Google Patents

Abstract

PURPOSE:To furnish a shift register in which the number of controlling clocks is small and the arrangement is devised by precharging an output end by a clock- controlled transistor instead of raising the output end steadily by a load transistor. CONSTITUTION:The high potential VGG of clock signals CL1, CL2, CL3 is selected above (VDD + threshold voltage of transistor), and an output of each step becomes a signal that swings fully between VDD and grounding potential. When the CL1 becomes VGG, a Tr11 becomes on, and the output end Q4 is raised to VDD. When the CL1 becomes grounding and CL2 becomes VGG, Tr11 is turned off and a Tr12 becomes on, and the potential of Q4 is determined according to gate potential of 13. At the same time, a Tr14 is turned on by the CL2 and an output end Q5 of the next step is raised to VDD. When the CL2 becomes grounding and the CL3 becomes VGG, the Trs 12, 14 are turned off and 15 is turned on. The Q4 is dynamically held at the previous potential and the Q5 becomes inverted potential. Consequently, data is shifted delayed by time t between rising edges of the CL3 and CL2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift register formed by insulated gate field effect transistors.

Conventionally, several types of shift registers using single-channel field effect transistors are known and in practical use, but if the structure is simple, the E/E type (enhancement If the device is based on an inverter (drive transistor/enhancement load transistor type), the channel width/channel length ratio of the drive transistor must be much larger than that of the load transistor. If the device is based on a load transistor type (load transistor type) inverter, process control is required to prevent the threshold voltage of the load transistor from increasing too much in the negative direction. Also,
Dynamic circuits with low current consumption require multiple control clocks.

SUMMARY OF THE INVENTION In consideration of the above points, it is an object of the present invention to provide a dynamic shift register with a small number of control clocks and a well-arranged arrangement.

To achieve that objective, the shift register of the present invention precharges the output with a clock-controlled transistor, instead of trying to constantly pull up the output with a load transistor, and The transistor is controlled by a clock, and the transistors whose gate input is the output or data signal from the previous stage are switched in series, and the output terminal potential is changed.The number of control clocks is 3 or 2 (inverted (including signals). More specifically, a plurality of stages of the above-mentioned circuits are connected, and a clock signal for controlling a transistor connected in series with a transistor that inputs the previous stage output or data signal of one stage of the circuit is transferred from the output of that stage to the next stage. A clock signal that opens and closes an intervening transistor provided as necessary when inputting to a corresponding transistor in a stage;
and/or a clock signal for controlling a transistor that precharges the output end of the next stage, and is characterized by the arrangement and combination of the clock signals.

A first embodiment of the invention is shown in FIG. The circuit in Figure 1 is constructed by connecting multiple stages (six stages in the figure). A certain one-stage circuit (fourth stage in the figure) has the first clock signal CL1 as the gate input, and the output terminal Q4 is connected to V Transistor 1 precharging to _DD
1, a transistor 12 whose gate input is the second clock signal CL2, and a previous stage output Q3, or a transistor whose gate input is the data signal D in the first stage. 5th stage) is the second clock signal CL2
A transistor 14 which has a gate input and precharges an output terminal Q5 to _VDD , and a third clock signal.
Transistor 15 with CL3 as the gate input and transistor 1 with the previous stage output Q4 as the gate input
This is a shift register composed of 6 and 6 connected in series. In this embodiment, parts represented by transistors 12 and 13, 15 and 16 can be arranged interchangeably in a multi-stage circuit, and
A configuration using an N-channel transistor can be changed to a P-channel transistor configuration by switching the power supply potential V _DD and the ground potential. This also applies to the second and subsequent embodiments. According to the timing chart of the shift register shown in FIG. 1, shown in FIG. 2, the manner in which data is transferred can be clearly seen. The shaded portions are transferred while being reversed for each stage. The high potential V _GG of the clock signal is
(V _DD + threshold voltage of transistor) or more,
The output of each stage is a signal that fully swings between V _DD and ground potential.

When CL1 becomes V _GG , 11 turns on and the output terminal Q
Raise 4 to V _DD . CL1 becomes grounded and CL2
When becomes V _GG , 11 turns off, 12 turns on,
The potential of Q4 is determined according to the gate potential of Q13.
If Q3 is at _VDD , Q4 is grounded, and if Q3 is grounded, Q4 is dynamically held at _VDD . At the same time, CL2 14 turns on and raises the output terminal Q5 of the next stage to V _DD . CL2 is grounded
When CL3 becomes V _GG , 12 and 14 turn off and 15
turns on. Q4 is dynamically held at the previous potential, and Q5 is at the inverted potential of Q4, resulting in the data being shifted with a delay of time t between the rising edges of CL3 and CL2.

The configuration shown in FIG. 3 and the timing chart shown in FIG. 4 are for the second embodiment. The circuit in FIG. The fourth stage) has the first clock signal CL1 as its gate input and a transistor 21 that precharges the output terminal Q4 to _VDD , a transistor 22 that has the second clock signal CL2 as its gate input, and the output from the previous stage ( transistor 27
Q3 output via , or transistor 23 whose gate input is the data signal D in the first stage.
The next stage circuit (fifth stage in the figure) consists of a transistor 24 which receives the third clock signal CL3 as a gate input and precharges the output terminal Q5 to _VDD , and a transistor 24 which receives the third clock signal CL3 as a gate input and precharges the output terminal Q5 to VDD. This shift register is constructed of a series connection of a transistor 25 as an input, and a transistor 26 whose gate input is the output Q4 from the previous stage via a transistor 28 which is opened and closed by a second clock signal.

When CL1 becomes V _GG , 21 turns on and the output terminal Q
Raise 4 to V _DD . CL1 becomes grounded and CL2
When becomes V _GG , 21 is turned off, 22 and 28 are turned on, and the gate potentials of Q4 and 26 are determined according to the gate potential of 23. If the gate potential of 23 is near _VDD , Q4 is grounded, and if the gate potential of 23 is grounded, it is dynamically held near _VDD . When CL2 is grounded and CL3 becomes V _GG , 2
2 and 23 are turned off, 27 and 24 are turned on, and the gate potential of 23 is determined, and the output terminal Q of the next stage is determined.
5 to V _DD . CL3 becomes grounded and CL1
When becomes V _GG , 27 and 24 turn off and 21 and 2
5 turns on. Q4 is pulled up to V _DD and Q5 is at a potential that is the inverse of the gate potential of 26, resulting in data being shifted with a delay of time t between the rising edges of CL1 and CL2. The capacitor added to the output terminal in Figure 3 is to reduce the potential drop due to charge redistribution when inputting the output terminal potential to the next stage gate via the transistor. In cases such as when inputting to the gate of a transistor and buffering it to take it out, the gate capacitance of an added transistor can be used instead.

The configuration of the third embodiment is shown in FIG. 5, and the timing chart is shown in FIG. 6. The circuit in Figure 5 is constructed by connecting multiple stages of circuits, and one stage of the circuit (the third stage in the figure) receives the first clock signal CL.
1 as a gate input and a transistor 31 that precharges the output terminal Q3 to _VDD , and a transistor 32 that has a second clock signal CL2 as a gate input.
and output from the previous stage (third clock signal CL3
Q2 output via a transistor 37 which is opened and closed at A transistor 34 whose gate input is the clock signal CL1 and precharges the output terminal Q4 to V _DD , a transistor 35 whose gate input is the third clock signal CL3, and a transistor 36 whose gate input is the output Q3 from the previous stage are connected in series. It is a shift register made up of connections.

When CL1 becomes V _GG , transistors 31 and 34 turn on, raising output terminals Q3 and Q4 to V _DD . When CL1 is grounded and CL2 becomes V _GG , 31 and 34 turn off,
32 is turned on, and the potential of Q3 is determined according to the gate potential of 33. If the gate potential of 33 is near _VDD , Q3 is grounded, and if the gate potential of 33 is grounded, Q3 is dynamically held at _VDD . 32 when CL2 is grounded and CL3 becomes V _GG
is turned off, 35 and 37 are turned on, and the gate potential of 33 is determined, the potential of Q3 is dynamically held to the previous potential, and the potential of Q4 is almost inverted to that of Q3.As a result, CL3 and C.L.
The data is shifted with a delay of time t1 between the two rising edges. In substantially the same way, data is shifted from the fourth stage to the fifth stage with a delay of time t2 between the rising edges of CL2 and CL3.

The configuration of the fourth embodiment is shown in FIG. 7, and the timing chart is shown in FIG. 8. The circuit in FIG. 7 is constructed by connecting multiple stages of circuits, and one stage of the circuit (the third stage in the figure) receives the first clock signal CL1.
a transistor 41 whose gate input is CL2 and which precharges its output terminal Q3 to V _DD ; a transistor 42 whose gate input is a second clock signal CL2;
and the output from the previous stage (first clock signal CL1
Q2 output via transistor 47 which is opened and closed at The clock signal CL2 is used as the gate input, and the output terminal Q4 is used as the gate input.
The output Q3 from the previous stage is passed through a transistor 44 which is precharged to V _DD , a transistor 45 whose gate input is the first clock signal CL1, and a transistor 48 which is opened and closed by the second clock signal.
This is a shift register configured by connecting in series with a transistor 46 whose gate input is .

When CL1 becomes V _GG , 41 and 47 turn on, raising the output terminal Q3 to V _DD and determining the gate potential of 43. When CL1 becomes grounded and CL2 becomes V _GG , 41, 45, and 47 are turned off, and 42, 44, and 48 are turned on, thereby determining the gate potential of Q3, that is, 46. If the gate potential of 43 is near _VDD , Q3 will be grounded, and if the gate potential of 43 is grounded, Q3 will be grounded.
3 is dynamically held near _VDD . At the same time, the next stage output Q4 is precharged to _VDD .
When CL2 is grounded and CL1 becomes V _GG , 42,
44, 48 are turned off, 41, 45, 47 are turned on, the gate potential of 43 is determined, the gate potential of 46 is dynamically held at the previous potential, and the gate potential of transistor 46 is inverted. It becomes a potential. As a result, CL1 and
Data is shifted with a delay of time t between the rising edges of CL2. In particular, the circuit of FIG. 7 is a two-phase clock type shift register, and the second clock signal CL2 can be an inverted signal of the first clock signal CL1.

The shift register of the present invention described above realizes a dynamic shift register with low current consumption in which transfer is controlled by a small number of clocks. However, as described below, a buffer means is added to the output to improve the waveform. It can be taken out after shaping or impedance conversion.

The fifth embodiment of the present invention shown in FIG.
It is based on the example of , and is configured by connecting multiple stages of circuits, and one stage of the circuit (the first stage in the figure)
However, a signal different from the clock signal CL1 that precharges the output terminal Q1 of the stage (clock signal CL
3) is connected to the drain via a capacitor 52, and has a transistor 51 which receives the output signal Q1 as a gate input, and further includes a transistor 53 which receives the signal Q1 as a gate input, and one side electrode of 52 as a gate input. 5 by connecting the transistors 54 in series.
P1 which converts the impedance of the output of 1 and extracts it.

If Q1 is V _DD , 51 and 53 are turned on, and 51
Since the drain potential of 52 is grounded, even if the waveform of CL3 changes, the differential waveform derived from 52 will be 54
is not turned on, and P1 is grounded. When CL2 becomes V _GG and Q1 becomes grounded, 51 and 53 are turned off. When CL2 is grounded and CL3 becomes V _GG , 5
1 and 53 remain off and the potential of CL3 appears on the drain of 51, so 54 turns on and P1 becomes
It becomes V _DD . When CL3 becomes grounded and CL1 becomes V _GG , the drain potential of 51 becomes grounded, 54 turns off, 51 and 53 turn on, and P1 becomes grounded.

By adopting a similar configuration to the third and fifth stages of the first embodiment as shown in FIG. 9, the shift register outputs P1, P2, whose waveforms are shaped as shown in the timing chart of FIG. P3 can be obtained.

The structure of the sixth embodiment is shown in FIG. 11, and the timing chart is shown in FIG. 12.
This is based on the fourth embodiment, and is configured by connecting multiple stages of circuits, and one stage circuit (the first stage in the figure) includes a transistor 61 whose gate input is the output signal Q1, 63 and a signal CL2' different from the clock signal that precharges the output terminal Q1 of the stage are connected to the drain of 61 and the gate of 64 via a capacitor 62, and a buffer output stage is provided in which 63 and 64 are connected in series. are doing. CL2' can be a different clock signal or a delayed clock signal than the clock signal precharging output Q1, in this embodiment the clock signal
A delayed signal of CL2 is used.

If Q1 is V _DD , 61 and 63 are turned on, and 61
Since the drain potential of is grounded, 64 is turned off,
P1 is grounded. When CL2 becomes V _GG and Q1 becomes grounded according to the data signal, 61 and 63 are turned off. Subsequently, when CL2' becomes V _GG , 64 turns on, and P1 becomes V _DD . When CL2 and CL2' become grounded and CL1 becomes V _GG , 64 turns off and 61,
63 is turned on and P1 is grounded.

The configuration is shown in Figure 13, and the timing chart is shown in Figure 1.
The seventh embodiment is shown in FIG. This is based on the first embodiment, and is configured by connecting multiple stages of circuits, and one stage circuit (the first stage in the figure) includes a transistor 71 whose gate input is the output signal Q1, 73 and a signal (clock signal CL13) different from the clock signal that precharges the output terminal Q1 of the stage is connected to the drain of 71 and the gate of 74 via the capacitor 72,
and said different signal CL3 or clock signal CL
2 (both are used in the figure) are connected in series with transistors 75 and 76, each of which has a gate input.

If Q1 is V _DD , 71 and 73 are turned on, and 71
74 is turned off because its drain potential is grounded. If CL2 and CL3 are grounded, 75 and 76 are also turned off, so P1 dynamically holds the previous potential and becomes the ground potential.

When CL2 becomes V _GG and Q1 is grounded in response to the data signal, 71 and 73 are turned off, 76 is turned on, and P1 continues to hold the ground potential. CL2
becomes grounded and CL3 becomes V _GG , then 71, 73,
76 is off, 74 and 75 are on, P1 is V _DD
becomes. When CL3 becomes grounded and CL1 becomes V _GG , Q1 becomes V _DD , 71 and 73 turn on, and 7
4, 75, and 76 are turned off, and P1 continues to hold V _DD . If CL1 is grounded, CL2 is V _GG , and the data signal is grounded, Q1 remains at V _DD , 71, 73, and 76 are on, and 74 is off, so P1 is grounded. In FIG. 14, a pulse width approximately twice that of the pulse width in FIG. 10 of the fifth embodiment is obtained.

The structure of the eighth embodiment is shown in FIG. 15, and the timing chart is shown in FIG. 16. This is based on the fourth embodiment, and is configured by connecting multiple stages of circuits, and one stage circuit (the first stage in the figure) includes a transistor 81 whose gate input is the output signal Q1, 83 and a signal CL2' different from the clock signal that precharges the output end of the stage are connected to the drain of 81 and the gate of 84 via the capacitor 82,
It has a buffer means connected in series with a transistor 85 whose gate input is . CL2' is the 6th
This is the delayed signal of CL2 as in the embodiment.

If Q1 is V _DD , 81 and 83 are turned on, and 81
Since the drain potential of 84 is grounded, 84 is turned off. If CL2 is grounded, 85 will also be turned off, so P
1 dynamically holds the previous ground potential. CL2 becomes V _GG and Q depending on the data signal
When 1 is grounded, 81 and 83 are turned off and 85 is turned on. Subsequently, when CL2' becomes V _GG , 84 turns on, and P1 becomes V _DD . 85 when CL2 is grounded
turns off, then CL2' is grounded and CL1 becomes V _GG , Q1 becomes V _DD , 84 turns off, 81,
83 turns on. P1 continues to hold V _DD . If CL1 is grounded and CL2 is set to V _GG , and the data signal is grounded, Q1 remains at V _DD , and since 81, 83, and 85 are on and 84 is off, P1 is grounded. In FIG. 15, a pulse width approximately twice that of the pulse width in FIG. 12 of the sixth embodiment is obtained.

Furthermore, the various shift registers described above can use a reset signal to initialize the shift register output.

FIG. 17 shows a ninth embodiment of the present invention, which is configured by connecting multiple stages of circuits, and one stage of the circuit (the first stage in the figure) connects a transistor that is turned on by a reset signal to the output terminal Q1. In addition, precharging to the output terminal is prohibited at the time of reset.

This is an example in which the above function is added to the first embodiment, and if the reset signal R is grounded, 97,9
Since 8 is off, normal operation is performed, and if R is V _GG , by grounding CL1, CL2, and CL3 at the same time, 91, 92, 94, and 95 are turned off, and 97 and 98 are turned on. Q1 goes to V _DD and Q2 goes to ground. By repeating this at the subsequent stage, a constant initial output of the shift register can be obtained.

In addition to being added to the output terminal, the transistor having this reset function can be added to the gate of the next-stage transistor into which the signal from the output terminal is input in the second, third, and fourth embodiments.

FIG. 18 shows a tenth embodiment based on the fourth embodiment, which is constructed by connecting multiple stages of circuits, and one stage of the circuit (the second stage in the figure) is turned on by a reset signal. A transistor is added to the output terminal Q2, and precharging to the output terminal is prohibited at the time of reset.

If the reset signal R is grounded, 108 is turned off and normal operation is performed.If R is V _GG , by simultaneously grounding CL2 and setting CL1 to V _GG ,
102, 104, 107 are off, 101, 10
5,108 is turned on, Q1 is connected to V _DD and Q2 is connected to ground. By repeating this at the subsequent stage, a constant initial output is set in the shift register.

Regarding the above-mentioned reset function, the power-on reset signal is used as the reset signal, and the input clock signal is gated by the same signal to perform initial setting, and automatic initial setting of the shift register can be performed.

As described above, the shift register of the present invention is implemented in a dynamic format by connecting enhancement type transistors in series and controlling the precharging and driving of the output terminal using a clock, resulting in a circuit with low current consumption. In the present invention, the transistor characteristics are such that the threshold voltage of the precharging transistor is higher than that of the load transistor.
It is of course possible to set it low within the enhancement range and increase the drive ability of the output end.
Various well-known schemes can be used. Also,
It can be applied to various transistor circuits using compounds such as amorphous silicon, polycrystalline silicon, laser annealed silicon, single crystal silicon, and CdSe as semiconductors.

According to the present invention, a shift register that controls an image display device that drives a liquid crystal using a plurality of transistors as switching elements can be formed on the same substrate together with the switching elements, which is useful.

[Brief explanation of drawings]

FIG. 1 shows a first embodiment of the shift register of the present invention. FIG. 2 is a timing chart of the embodiment shown in FIG. FIG. 3 shows a second embodiment of the shift register of the present invention. FIG. 4 is a timing chart of the embodiment shown in FIG. FIG. 5 shows a third embodiment of the shift register of the present invention. FIG. 6 is a timing chart of the embodiment shown in FIG. FIG. 7 shows a fourth embodiment of the shift register of the present invention. FIG. 8 is a timing chart of the embodiment shown in FIG. FIG. 9 shows a fifth embodiment of the shift register of the present invention. FIG. 10 is a timing chart of the embodiment shown in FIG. FIG. 11 shows the sixth shift register of the present invention.
Example. FIG. 12 is a timing chart of the embodiment shown in FIG. 11. FIG. 13 shows a seventh embodiment of the shift register of the present invention. FIG. 14 is a timing chart of the embodiment shown in FIG. 13. FIG. 15 shows an eighth embodiment of the shift register of the present invention. FIG. 16 is a timing chart of the embodiment shown in FIG. 15. FIG. 17 shows a ninth embodiment of the shift register of the present invention. FIG. 18 shows a tenth embodiment of the shift register of the present invention. CL1, CL2, CL3...clock signal, Q1,
Q2, Q3, Q4, Q5, Q6...output signal, D
...Data signal, P1, P2, P3...Buffer output, R...Reset signal.

Claims (1)

[Claims] 1. A transistor that precharges an output terminal controlled by a clock signal, a transistor controlled by another clock signal that is different from the timing of the transistor, and a transistor whose input is a previous stage output or data signal, connected in series. Connect multiple stages of connection circuits, and input the clock signal that controls the transistor connected in series to the transistor that receives the previous stage output or data signal of one stage of the circuit, and inputs the output of that stage to the corresponding transistor of the next stage. In this case, a clock signal is used to open and close intervening transistors provided as necessary, and/or a clock signal to control a transistor that precharges the output terminal of the next stage. 2. It is composed of a plurality of stages of circuit connections, and one stage of the circuit includes a transistor that receives the first clock signal as a gate input and precharges the output terminal, and a second
The next stage circuit consists of a transistor whose gate input is the second clock signal and a transistor whose gate input is the previous stage output or data signal, and a transistor whose gate input is the second clock signal and whose output terminal is precharged. , a transistor whose gate input is the third clock signal, and a transistor whose gate input is the output of the preceding stage, connected in series. 3. It is composed of a plurality of stages of circuit connections, and one stage of the circuit includes a transistor whose gate inputs the first clock signal and which precharges the output terminal, and a transistor whose output terminal is precharged.
The next stage circuit consists of a transistor whose gate input is the third clock signal and a transistor whose gate input is the output or data signal from the previous stage, and a transistor whose gate input is the third clock signal and whose output terminal is precharged. and the first
Claim 1, characterized in that the transistor is connected in series with a transistor whose gate input is the clock signal of the second clock signal, and a transistor whose gate input is the output from the previous stage via a transistor that is opened and closed by the second clock signal. Shift register described in section. 4. It is composed of a plurality of stages of circuit connections, and one stage of the circuit includes a transistor that receives the first clock signal as a gate input and precharges the output terminal, and a second
The circuit in the next stage consists of a transistor whose gate input is the clock signal of the first stage, and a transistor whose gate input is the output from the previous stage via a transistor that is opened and closed by the data signal or the third clock signal. A patent characterized in that a transistor is connected in series with a transistor whose gate input is a first clock signal and which precharges its output terminal, a transistor whose gate input is a third clock signal, and a transistor whose gate input is the output from the previous stage. Shift register according to claim 1. 5. It is composed of a plurality of stages of circuit connections, and one stage of the circuit includes a transistor that receives the first clock signal as a gate input and precharges the output terminal, and a second
The circuit in the next stage consists of a transistor whose gate input is the clock signal of the second stage, and a transistor whose gate input is the output from the previous stage via a transistor that is opened and closed by the data signal or the first clock signal. A transistor whose gate input is the clock signal of the transistor whose output terminal is precharged, a transistor whose gate input is the first clock signal, and a transistor whose gate input is the output from the previous stage via a transistor that is opened and closed by the second clock signal. 2. The shift register according to claim 1, wherein the shift register is connected in series with the shift register. 6. The shift register according to claim 5, wherein the second clock signal is an inverted signal of the first clock signal. 7. It is composed of multiple stages of circuit connections, and one stage of the circuit has a transistor whose drain is connected to a signal different from the clock signal that precharges the output terminal of the stage through a capacitor, and whose gate input is the output signal. A shift register according to any one of claims 1 to 6, characterized in that the shift register is provided with: 8. Consisting of multiple stages of circuit connections, one stage of circuit has a transistor whose gate input is a signal different from the clock signal that precharges the output terminal of the stage through a capacitor, and whose gate input is an output signal. 8. The shift register according to claim 7, further comprising a series connection with a transistor. 9. Consisting of multiple stages of circuit connections, one stage of circuit has a transistor whose gate input is a signal different from the clock signal that precharges the output terminal of the stage through a capacitor, and whose gate input is an output signal. 8. The shift register according to claim 7, further comprising a transistor connected in series with a transistor whose gate input is either the different signal or the clock signal. 10. The shift register according to any one of claims 7 to 9, wherein the different signal is a clock signal different from the clock signal for precharging the output end or a delayed clock signal. . 11 Consisting of multiple stages of circuit connections, certain 1
Claims characterized in that the stage circuit is characterized in that a transistor that is turned on by a reset signal is added to the output end or to the gate of the next stage into which the signal from the output end is input, and at the time of reset, precharging to the output end is prohibited. Shift register according to any one of items 1 to 10.