JPS6010498A - Shift register - Google Patents

Abstract

PURPOSE:To furnish a shift register in which the number of controlling clocks is small and the arrangement is devised by precharging an output end by a clock- controlled transistor instead of raising the output end steadily by a load transistor. CONSTITUTION:The high potential VGG of clock signals CL1, CL2, CL3 is selected above (VDD + threshold voltage of transistor), and an output of each step becomes a signal that swings fully between VDD and grounding potential. When the CL1 becomes VGG, a Tr11 becomes on, and the output end Q4 is raised to VDD. When the CL1 becomes grounding and CL2 becomes VGG, Tr11 is turned off and a Tr12 becomes on, and the potential of Q4 is determined according to gate potential of 13. At the same time, a Tr14 is turned on by the CL2 and an output end Q5 of the next step is raised to VDD. When the CL2 becomes grounding and the CL3 becomes VGG, the Trs 12, 14 are turned off and 15 is turned on. The Q4 is dynamically held at the previous potential and the Q5 becomes inverted potential. Consequently, data is shifted delayed by time t between rising edges of the CL3 and CL2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift register formed by insulated gate field effect transistors.

Conventionally, several types of shift registers using single-channel field-effect synchronizers are known and are in practical use, but if the structure is simple, the E/E type has a DC-like current consumption. (enhancement drive transistor/
If the inverter is based on an enhancement load transistor (enhancement load transistor type) inverter, the channel width/channel length ratio of the drive transistor must be much larger than that of the load transistor.
dynamic) transistor/depression load transistor type)
If the device is based on an inverter, it is necessary to control the process so that the threshold voltage of the load transistor does not become too large in the negative direction. Furthermore, dynamic circuits with low current consumption require a large number of control clocks.

Considering the above points, the present invention has a small number of control clocks,
The object of the present invention is to provide a dynamic shift register whose arrangement is well thought out.

In order to achieve this purpose, the shift register of the present invention precharges the output terminal with a clock-controlled transistor, instead of trying to constantly raise the output terminal with a load transistor. Using a transistor controlled by another clock, the transistors whose gate input is the output from the previous stage or data@month are switched in a 1α column, and the output terminal potential is changed, and the number of control clocks is 3 or 2. Species (including inverted signals) are used.

More specifically, a plurality of circuits of the above type are connected to form a certain one.
A clock signal that controls the transistor connected in series with the transistor that receives the previous stage output or data signal in the stage circuit, and a clock signal that opens and closes the transistor that is connected when the output of the stage is input to the corresponding transistor in the next stage. , or as a clock signal to control a transistor that precharges the output end of the next stage, and has a specific arrangement and combination of clock signals.

A first embodiment of the invention is shown in FIG. The circuit in Figure 1 is composed of multiple stages (six stages in the figure) of circuit connections.
The stage circuit (fourth stage in the figure) receives the first clock signal (cL
A transistor (11) which uses l) as a gate input and precharges the output terminal (Q4) to
It consists of a series connection with a transistor whose gate input is the previous stage output ((Q3), or data signal (D) in the first stage), and the next stage circuit (the fifth stage in the figure) receives the second clock signal. (OL2) is the gate input and the output terminal (Q5
) to VDD, a transistor (15) whose gate input is the third clock signal (CL3), and a transistor (16) whose gate input is the previous stage output (Q, 4) are connected in series. This is a shift register made up of connections.In this embodiment, the parts represented by transistors (12) and (13), and (15) and (16) can be arranged interchangeably in a multi-stage circuit. , an N-channel transistor configuration can be changed to a P-channel transistor configuration by swapping the power supply potential vDD and the ground potential.
The same applies to the following examples. According to the timing chart of the shift register of FIG. 1 shown in FIG. 2, the manner in which data is transferred can be clearly seen.

The shaded portions are transferred while being reversed for each stage. ■ High potential of clock signal. , is selected to be greater than (vDD + threshold voltage of transistor), and the output of each stage is VDD
It is a borrowed device that makes a full swing between the ground potential and the ground potential.

OLI is ■. When it becomes 0, (11) turns on and the output terminal Q
4 to VDD. When OLI is grounded and OL2 becomes vGG, (11) is turned off, (12) is turned on, and the potential of Q4 is determined according to the gate potential of (13).

If Q3 is at vDD, Q4 is grounded, and if Q3 is grounded, Q4 is dynamically held at VDD.

At the same time, (]4) is turned on in OL2, and the output terminal Q5 of the next stage is raised to VDD.

OL2 is the ground door', Ct) CTJ3 is VGG, (12) and (14) are closed, and (15) is turned on. Q4 is dynamically held at the previous potential and q5 becomes the inverted potential of Q4, resulting in 1vI between the rising edges of Cu3 and Cu2.
If the data is shifted with a delay of t, then it becomes K.

The configuration is shown in FIG. 3, and the timing chart is shown in FIG. 4 for the second embodiment.

The circuit shown in Fig. 3 is composed of multiple stages of circuit connections.
The stage circuit (fourth stage in the figure) receives the gt clock signal (cr
,,1) as a gate input and a transistor (21) that precharges the output terminal (Q4) to VDD, a transistor (22) that uses the second clock signal (cL+2) as a gate input, and an output from the previous stage ( Transistor (27)
It consists of a series connection with a transistor (23) whose gate input is Q3 output via Q3 or data signal (D) in the first stage, and the next stage circuit (fifth stage in the figure) is the third stage. The clock signal (aLa) is input to the gate and the output terminal (
Transistor (24) precharging Q5) to VDD
), a transistor (25) which receives the first clock signal (OLI) as a gate input, and a transistor (28) which is opened and closed by the second clock signal, and receives the output (Q4) from the previous stage as a gate input. This is a shift register composed of a series connection with a transistor (26).

When OLI becomes VGG, (21) turns on and the output terminal Q
4 to VDD. When OLI is grounded and Cu2 becomes VGG, (21) turns off, and (22), (28)
is turned on, and Q4 and (2) are turned on according to the gate potential of (23).
6) Determine the gate potential. The gate potential of (23) is V
If it is near DD, Q4 is grounded, and if the gate potential of (23) is grounded, it is dynamically held near VDD. Cu2 is grounded and OL3 is VGG!
-(22), (z8N! is turned off, (27) and (24) are turned on, and the gate potential of 23) is determined, and the output terminal Q5 of the primary stage is raised to VDD. Cu3 is grounded and OLI is vGGtonal, (27], (24) Hao7L,, (21), (25) are turned on. Q4 is VDD
At the same time, Q5 becomes the inverted potential of the gate potential of (26), and as a result, CLl and C
The data is shifted with a delay of time t between the rising edges of u2. The capacitance added to the output terminal in Figure 3 is to reduce the potential drop due to charge redistribution when inputting the output terminal box to the next stage gate via the transistor. In cases where the end is input to the gate of a transistor and taken out after being buffered, it can be replaced with the gate capacitance of the added transistor.

The configuration of the third embodiment is shown in FIG. 5, and the timing chart is shown in FIG. 6. The circuit shown in Fig. 5 is constructed by connecting multiple stages of circuits, and one stage of the circuit is connected to the other stage. (3rd row in the diagram)
is a transistor (31) which takes the clock signal (c:t, 1) of ψ, 1 as a gate input, precharges the output terminal (Q3) to VDD, and the second clock signal (C!L2).
A transistor (32) whose gate input is Q2, and an output from the previous stage (Q2 output via a transistor (37) that is opened and closed by the third clock signal (Ol, 3), or 1
The first stage consists of a series connection with a transistor (33) which receives the data signal (D)) as the gate input, and the next stage circuit (fourth stage in the figure) receives the first clock signal (cLB) as the gate input and outputs the data signal (D). A transistor (34) precharging the terminal (Q4) to VDD and a third clock signal (C!
This shift register is constructed by connecting in series a transistor (35) whose gate input is L3) and a transistor (36) whose gate input is the output (Q3) from the previous stage.

OLI is set to vGG, (31) and (34) are turned on, and output terminals Q3 and Q4 are pulled up to VDD. OLI is grounded tx') Cu2 is VGG tx, root (31
), (34) are turned off, (32) is turned on, and the potential of Q3 is determined according to the gate potential of (aa). If the gate potential of (33) is near VDD, Q3 is grounded, and (3
If the gate potential of 3) is grounded, Q3 is dynamically held at VDD. Cu2 is grounded) Cu2
KavaG Tonaruto (32) Hao71. (3s)
, (37) are turned on and the gate potential of 33) is determined,
The potential of Q3 is dynamically held to the previous potential, and the potential of Q4 is almost inverted to that of Q3.
As a result, the data is shifted with a delay of time t1 between the rising edges of OL3 and OL2. Similarly, data is shifted from the fourth stage to the fifth stage with a delay of time t2 between the rising edges of OL2 and OL3.

The configuration of the fourth embodiment is shown in FIG. 7, and the timing chart is shown in FIG. 8. The circuit in FIG. 7 is constructed by connecting multiple stages of circuits, and one stage of the circuit (the third stage in the figure) is 1! −1 clock signal (cbl) as gate input,
A transistor (41) that precharges the output terminal (Q3) to VDD, a transistor (42) that receives the second clock signal (OL2) as a gate input, and an output from the previous stage (first clock signal (OLI)). It consists of a series connection with a transistor (43) whose gate input is the Q2 output via a transistor (47) that is opened and closed at The fourth stage) receives the second clock signal (OL2) as a gate input, and has a transistor (44) that precharges the output terminal (Q4) to VDD, and the first clock signal (OLI).
It consists of a transistor (45) whose gate input is Q3, and a transistor (46) whose gate input is the output (Q3) from the previous stage via a transistor (48) which is opened and closed by the second clock signal. It is a shift register.

OLI is Vaa 7.1), (4]), (4
7) Raise the output terminal Q3 to VDD, (43
) determine the gate potential. (jLl is grounded and OL2
When becomes VGG, (41), (45), and (47) are turned off, and (42), (44), and (48) are turned on, which determines the gate potential of Q3, that is, (46).The gate of (43) If the potential is near vDD, °Q3 is grounded and (43
) is grounded, Q3 is dynamically held near VDD. At the same time, the next stage output Q4 is VDD
will be precharged. OL2 is grounded and OLI is V
GG Tonaruto, (42), (44), (48) Hao7 L, (41), (45), (47) are on, (4
3) is determined, the gate potential of ('il is dynamically bolded to the previous potential, and Q
4 is the inverted potential of Q3. As a result, the data is shifted with a delay of time t between the rising edges of OLI and OL2. In particular, the circuit in FIG. 7 is a two-phase clock type shift register, and the second clock signal (OL2)
can be an inverted signal of the first clock signal (OL).

The shift register of the present invention described above realizes a low-oil/current dynamic shift register in which transfer is controlled by a small number of handles, but as described below, a buffer means is added to the output, It can be extracted by waveform shaping or impedance conversion.

The fifth embodiment of the present invention shown in FIG. 9 is based on the first embodiment, and is configured by multiple stages of circuit connections.
A certain one-stage circuit (the first stage in the figure) connects the output terminal (Q
A transistor (51) is connected to its drain via a capacitor (52) with a signal (clock signal CL3) different from the clock signal (OLI) for precharging the output signal (Q, 1), and whose gate input is the output signal (Q, 1). In addition,
A transistor (53) whose gate input is the same signal (Ql)
) and a transistor (54) whose gate input is one side electrode of (52) are connected in series to convert the output of (5]) into 2. The impedance is converted and extracted (A1).

If Ql is VDD “C”, (51) and (53) are on-state, and the drain potential of (51) is grounded, so oTJ
Even if the waveform of 3 changes, the differential waveform derived from (52) does not turn on (54), and Pl becomes grounded.

When OL2 becomes VGG and Ql becomes grounded, (51),
(53) is turned off. OL2 is grounded and OL3 is Va
a Door', C7) To, (51], (5s) Hao7
Since the potential of Noif, -cOL3 is applied to the drain of (51), (54) is turned on and Pl becomes VDD. When OL3 is grounded and OLI becomes VGG, (5
The drain potential of 1) becomes grounded, and (54) turns off,
(51) and (53) are turned on and Pl is grounded.

A similar configuration is applied to the third stage, fifth stage, and ninth stage of the first embodiment.
By taking the steps as shown in the figure, the shift register output Pl whose waveform is shaped as shown in the timing chart of FIG.
, P2. P3 can be obtained.

The configuration of the sixth embodiment is shown in FIG. 11, and the timing chart is shown in FIG. 12. This is based on the fourth embodiment, and is configured by connecting multiple stages of circuits, and one stage of the circuit (the first stage in the figure) is a transistor whose gate input is the output signal (Ql). (61),
(63), and a signal (cL2) different from the clock signal that precharges the output terminal (Ql) of the stage is connected to the capacitor (62).
It is connected to the drain of (61) and the gate of (64) via a buffer output stage in which (6B) and (64) are connected in series. OL2' can be a different clock signal or a delayed clock signal than the clock signal that precharges the output (ql), and in this embodiment a delayed signal of the clock signal (C!L2) is used. ing.

Ql is VDD Teareba (61), (63) Kaonshi,
Since the drain potential of (61) is grounded, (64) is turned off and Pl is grounded. When OL2 becomes VGG and Ql becomes grounded according to the data signal, (61), (63
) Ha, t 7 f le. Z “v’”C: OL2
When ' becomes VGG, (64) turns on and Pl becomes vDD.

OL2. When OL2' is grounded and OLI is the VGG door, (64) is turned off, (61) and (63) are turned on, and Pl is grounded.

The configuration of the seventh embodiment is shown in FIG. 13, and the timing chart is shown in FIG. 14. This is based on the first embodiment, and is configured by connecting multiple stages of circuits.
) as the gate input (71L (73)
Then, a signal (clock signal OL3) different from the clock signal that precharges the output terminal (Ql) of the stage is connected to the capacitor (
72) to the drain of (71) and (74) σ) to the gate of (73) and (74) and the different signals (OK, 3) or the clock signal (OL2) (Fig. In this case, the transistors (5) and (76), both of which are used as gate inputs, are connected in series.

If Ql is VDD, (71) and (73) are turned on, and (
Since the drain potential of 71) is grounded, (74) is turned on. If OL2 and CL3 are grounded, (75), (76
) is also turned on, so Pl dynamically holds the previous potential and becomes the first ground plane.

When CL2 becomes VGG and Ql becomes grounded in accordance with the data signal, (71) and (73) are turned off, (76) is turned on, and Pl continues to hold the ground potential.

CL2 is grounded (tlt) CL3 is vGG tonal, (7
1), (73), (76) are off, (74], (75)
) is turned on, and Pl becomes VDD. When CL3 becomes grounded and OLI becomes VGG, Ql becomes VDD and (7
1), (73) are turned on, (74], (75), (76
) is turned off and Pl continues to hold VDD. OLI
becomes ground and C! If L2 becomes VGG and the data signal is grounded, Ql remains vDD, (71),
Since (73) and (76) are on and (74) is off, Pl is grounded. FIG. 14 shows the first example of rice 5.
A pulse width approximately twice the pulse width in Figure 0 is obtained.

The configuration of the eighth embodiment is shown in FIG. 15, and the timing chart is shown in FIG. 16. This is based on the fourth embodiment, and is configured by connecting multiple stages of circuits.
) with gate input (81), (83)
and (81) via a signal (82) different from the clock signal that precharges the output end of the stage
) and the gate of (84).
) and (84) and a transistor (85) whose gate input is a clock signal (0112) are connected in series. OL2' is the delayed signal of CL2 as in the 1.6 embodiment.

If Ql is VDD, (81) and (83) are turned on, and (
Since the drain potential of (81) is grounded, (84) is turned off. If CL2 is grounded, (85) will also be off, so P
l dynamically holds the previous ground potential.

When OL2 becomes VC)G and Ql becomes grounded according to the data signal, (81) and (83) are turned off and 85) is turned on. Next, OL2'force''V (when it comes to JG (64)
turns on and PI becomes VDD.

When OL2 is grounded, (85) turns off, and the OL
2 / is grounded, c Ll /l-, VC)G, then
Ql is VDD door x F), (84) Hao7 L,
(81) and (83) are turned on. Pl continues to hold VsiD.

If CLl is grounded and becomes OL2 or VGG, and the data signal is grounded, Ql remains VDD, (81)
, (83), and (85) are on, and (84) is off, so PI is grounded. Fig. 15 shows an example of frame 6 with a pulse width about twice that of Fig. 12. The loop width is obtained.

Further, each of the 4M shift registers can initialize the shift register output using a reset signal.

FIG. 17 shows a ninth embodiment of the present invention, in which a circuit is constructed by connecting two or more stages of circuits.
In the second stage), a transistor that is turned on by a reset signal is added to the output terminal (Ql), and precharging to the output terminal is prohibited at the time of reset.

This is an example in which the above function is added to the first embodiment, and even if the reset signal R is grounded, 1, (97), and (98) are turned off, so the operation is performed in the same manner as in the case of If there is, simultaneous K OLI, OL2. (1! By grounding L3, (91), (92), (94), (95
) turns off, (97) and (98) turn on, and Q l &
'i VDD, Q2 becomes ground. By repeating this in the subsequent stage, the initial output as shown at the beginning of the timing chart σ in Figure 2 can be obtained.

In addition to adding a transistor circuit having this reset function to the output terminal, in the second, third, and ν54 embodiments,
It can be added to the gate of the next stage transistor which inputs the signal from the output terminal.

FIG. 18 shows a tenth embodiment based on the fourth embodiment, which is configured by connecting multiple stages of circuits, and one stage of the circuit (the second stage in the figure) is turned on by a reset signal. It is added to the transistor output terminal (Q2) to inhibit σ knob recharging to the output terminal at the time of reset, and becomes 0.

If the reset signal R is grounded, (108) is turned off and normal operation is performed, and if R is VGG, CL
By setting 2 to ground and CLI to VGG, (102
), (104), (107) are off, (101), (1
05) and (108) turn on, Ql becomes VDD, and Q2
is grounded. By repeating this at the subsequent stage, the initial output is set as shown at the beginning of the timing chart in Figure 4.

Regarding the above reset mode, as a reset signal,
Automatic initialization of the shift register can be performed by using the power-on reset signal 7 and gating the input clock signal with the same signal to perform initialization.

In this way, the shift register of the present invention is realized in a dynamic format by connecting enhancement type transistors in series and controlling the precharging and driving of the output terminal with a clock, and is a circuit with low arithmetic operation consumption. It becomes. In the present invention, the transistor characteristics are such that the threshold voltage of the precharge transistor is lower than that of the load transistor, and it is of course possible to increase the drive capability of the output terminal by adding V to a lower value within the enforcement range. Elaborate schemes can be used. Further, the present invention can be applied to transistor circuits in which semiconductors include amorphous silicon, polycrystalline silicon, laser-annealed silicon, single-crystal silicon, and compounds represented by (JSe).

According to the present invention, a shift register that controls an image display device that drives a liquid crystal using a plurality of transistors as switching elements can be formed together with the switching elements on the same substrate, which is useful.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the shift register of the present invention. Figure 2 shows rabbit, l [i? , I timing chart of the embodiment. FIG. 3 shows a second embodiment of the shift register of the present invention. FIG. 4 is a timing chart of the embodiment shown in FIG. FIG. 5 shows a third embodiment of the shift register of the present invention. Figure 6 is a timing chart of the embodiment shown in Figure 5. FIG. 7 shows a fourth embodiment of the shift register of the present invention. FIG. 8 is a timing chart of the embodiment shown in FIG. FIG. 9 shows a fifth embodiment of the shift register of the present invention. Figure 10 is a timing chart of the embodiment shown in Figure 9. @11 Figure is the sixth embodiment of the shift register of the present invention. 8112 is a timing chart of the embodiment in FIG. 11. Figure 213 shows an example of the shift register of the present invention. 14 is a timing chart of the embodiment of FIG. 13. FIG. 15 shows an eighth embodiment of the shift register of the present invention. FIG. 16 is a timing chart of the embodiment shown in FIG. FIG. 17 shows a ninth embodiment of the shift register of the present invention. FIG. 18 shows an embodiment of the heat 10 of the shift register of the present invention. OLD, OL2. (3L3...clock signal GL1.
Q2. Q3. Q4. Q5. Q6... Output signal D... Day 248 PI, P2. P3...Buffer output R...Reset signal 2) 111 4 trap 1'8 Showa? Jun-O lO Hyunsai//Kaisai/3) fi Off 4 Jun. Off 5 order O 16 area /r /Q IL+ -・- Procedural amendment October 2, 1980 Sunset Patent Office Commissioner Kazuo Wakasugi 1, Display of case 1983 Patent Application No. 117067 2, Title of invention Shift register 3. Relationship with the case of the person making the amendment Patent applicant address 2-1-2 Marunouchi, Chiyoda-ku, Tokyo Name (
004) Asahi Glass Co., Ltd. Voluntary Amendment 8, Number of inventions increased by amendment None 7, Subject of amendment (1) Detailed explanation column of the invention in the specification (2) Drawing 8, Contents of amendment (1) Specification No. Page 17, first line “Q4 is Q3” is rQ
4 is corrected to the gate potential of (46). (2) "In the Examples" on page 23, line 1 O of the specification is amended to "In the Examples". (3) In the 8th and 9th lines of page 24 of the specification, "as at the beginning of the timing chart in FIG. 2" is corrected to "of a shift register set to a constant value." (Correct 0 specifications, page 25, lines 7 to 8, ``As at the beginning of the timing chart in Figure 4'' to ``Constant in the shift register.'' (5) Figures 13 and 15 of the drawings. , Figures 17 and 18
Correct the figure as shown in the attached sheet. More than O/3+1 O/Ai'[

Claims (1)

[Claims] (1) A transistor that precharges an output terminal controlled by a clock signal, a transistor controlled by another clock signal that is different from the timing of the transistor, and a transistor that receives the previous stage output or data signal as input. By connecting multiple stages of series-connected circuits, one can control the transistors connected in series with the transistor that inputs the previous stage output or data signal of one stage of the circuit (the lock signal is used to connect the output of that stage to the next stage's output). A shift register characterized in that the clock signal is used as a clock signal to open and close a transistor that is input to a corresponding transistor, or as a clock signal that controls a transistor that precharges the output terminal of the next stage. (2) By connecting multiple stages of circuits. A one-stage circuit consists of a transistor that uses a first clock signal as a gate input and precharges its output end, a transistor that uses a second clock signal as a gate input, and a previous stage output or data signal as a gate input. The next stage circuit consists of a transistor connected in series with a transistor, and a transistor that takes the second clock signal as a gate input and precharges the output end, a transistor that takes the third clock signal as a gate input, and a transistor that gates the output of the previous stage. The shift register according to claim 1, characterized in that the shift register is connected in series with a transistor as an input.: 8) The shift register is configured by a plurality of stages of circuit connections, and one stage of the circuit is connected to the first clock. It consists of a series connection of a transistor that uses a signal as a gate input and precharges the output terminal, a transistor that uses a second clock signal as a gate input, and a transistor that uses the output or data signal from the previous stage as a gate input, and is connected in series to the next stage circuit. is a transistor whose gate input is a third clock signal and whose output terminal is precharged;
Claims characterized in that the transistor is connected in series with a transistor whose gate input is the first clock signal, and a transistor whose gate input is the output from the previous stage via a transistor that is opened and closed by the second clock signal. 1st
Shift register described in section. (Xu) Consisting of multiple stages of circuit connections, one stage of the circuit includes a transistor whose gate input is the first clock signal and which precharges the output end, a transistor whose gate input is the second clock signal, and a data signal. Alternatively, it consists of a series connection with a transistor that uses the output from the previous stage as the gate input via a transistor that is opened and closed by the third clock signal, and the next stage circuit uses the clock signal of 菟1 as the gate input and precharges the output terminal. The shift register according to claim 1, characterized in that it consists of a transistor connected in series with a transistor whose gate input is a third clock signal, and a transistor whose gate input is an output from a previous stage. (6) Consisting of multiple stages of circuit connections, one stage of circuit includes a transistor whose gate input is the first clock signal and which precharges the output terminal, a transistor whose gate input is the second clock signal, and a data It consists of a multi-column connection with a transistor that uses the output from the previous stage as the gate input through a transistor that is opened and closed by the signal or the first clock signal, and the next stage circuit uses the second clock signal as the gate input and the output terminal is connected to the transistor. It is characterized by a series connection of a precharging transistor, a transistor whose gate input is the first clock signal, and a transistor whose gate input is the output from the previous stage via a transistor that is opened and closed by the second clock signal. A shift register according to claim 1, characterized in that (a) the second clock signal is an inverted signal of the first clock signal. Register. (η Consisting of multiple stages of circuit connections, one stage circuit connects a signal different from the clock signal that precharges the output end of the stage to the drain via a capacitor, and outputs the Gate input foot register. (8) Consisting of multiple stages of circuit connections, one stage of the circuit receives a signal different from the clock signal that precharges the output terminal of that stage as the gate input via the capacitor. A shift register according to claim 7, characterized in that the shift register is provided with a series connection of a transistor and a transistor whose gate input is an output signal. The stage circuit includes a transistor whose gate input is a signal different from the clock signal that precharges the output end of the stage, an L transistor whose gate input is an output signal, and the different signal or clock signal. The shift register according to claim 7, characterized in that it is provided with a series connection 145 with a transistor whose gate input is any one of the transistors. (10141zru・signal, output end)' A clock signal different from the clock signal used for recharging or (↓shift register. Adds the output terminal or the signal from the output terminal to the gate of the next stage transistor that inputs it, and precharges the output terminal at reset.