JPS6010117Y2 - AFT control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AFT control circuit for inhibiting AFT operation of an AFT circuit when switching channels and when power is turned on.

When an AFT circuit is provided in a television receiver tuner device, it is known that unless the AFT operation is prohibited when switching channels and when power is turned on, a malfunction may occur in which an undesired channel is received by the AFT operation.

In this case, the AFT operation inhibition time required when switching channels and the AFT operation inhibition time at power-on required until the power is turned on are different in length, for example, the former is about 100 to 200 [ms]. while the latter is 3
Generally, the prohibition time at power-on is long, such as 00 (ms).

Therefore, it is necessary for the AFT control circuit to generate control signals for inhibiting AFT operation of different lengths by detecting channel switching and power-on, respectively.
A configuration having three time constant circuits is used.

However, if two time constant circuits are directly connected to the control terminal of the switching means for inhibiting AFT operation, there is a risk that the other time constant circuits will act as a load and the desired operation will not be performed. Then, there is a problem that the circuit configuration becomes complicated.

Therefore, it is conceivable to use a single time constant circuit that generates a signal for inhibiting AFT operation of the required length when the power is turned on.
There is a problem that the operation prohibition time becomes longer than necessary.

Taking the above points into consideration, the present invention has developed an AFT control circuit that uses a simple circuit configuration and generates a control signal for inhibiting AFT operation for an optimal length of time both when switching channels and when power is turned on. This is what we aim to achieve.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes an electronic tuning tuner in which a reception channel is determined by the level of a tuning voltage applied to a variable capacitance diode.
A video intermediate frequency amplifier, a video detector, etc. are connected to the video intermediate frequency amplifier, video detector, etc.

Further, 2 indicates a channel selection control circuit, and 3 indicates a channel selection switch circuit.

The tuning switch circuit 3 has a plurality of tuning switches, and by operating any of them, the band switching voltage and tuning voltage of the channel corresponding to the tuning switch operated from the tuning control circuit 2 are changed. A desired channel is received by applying these band switching voltages and tuning voltages to the electronic tuning tuner 1.

Further, 4 is an AFT circuit.

The AFT circuit 4 is configured to supply, for example, a video intermediate frequency signal to a narrow band filter tuned to the video intermediate frequency, and detect the output of this narrow band filter, and one output terminal 5a is connected to a reference DC voltage. An AFT voltage with an S-shaped level change in response to frequency changes is generated at the center.
At the other output terminal 5b, an S-shaped AFT voltage of opposite polarity is generated around the same reference DC voltage.

These AFT voltages of opposite polarity are applied to the AFT voltage input terminal of the electronic tuning tuner 1, and in the AFT operating region, the received frequency is pulled to the tuning point by the voltage difference between the two, and outside the tuning point and the AFT operating region, the receiving frequency is pulled to the tuning point. , output terminal 5
The AFT voltages generated at a and 5b become the above-mentioned reference DC voltage.

Therefore, if a switching element such as FET 6 is provided to short-circuit between the output terminals 5a and 5b of this AFT circuit 4, the AF
When the FET 6 is turned on even within the T operation region, the AFT voltage becomes the reference DC voltage, and the AFT operation is prohibited.

In this example, the control voltage applied to the gate of FET5 is V
t (for example, 12 (V)) or more, this FET
5 is turned on.

The gate of FET 5 for inhibiting the AFT operation is connected to resistor 7.
It is connected to the collector of the PNP transistor 8 via.

A resistor 9 is connected between the collector of this transistor 8 and ground.
A first time constant circuit is provided in which ten series circuits and a capacitor 11 are connected in parallel.

The emitter of this transistor 8 is connected to one end of a power supply terminal to which a power supply voltage of 10 Vcc is applied via a protective resistor 12 of a very small value.

The base of this transistor is resistor 13 and capacitor 1
4 is grounded via a second time constant circuit connected in series.

Further, an NPN transistor 16 is provided, the collector of which is connected to one end of the power supply terminal via a resistor 15 and the emitter of which is grounded.The collector of this transistor 16 is connected to the base of the transistor 8.

The transistor 16 is turned on when a detection signal (positive pulse voltage) generated at the time of channel switching from the channel selection control circuit 2 is supplied to its base.

This detection signal has a pulse width T of a predetermined period of time, starting from the point at which the tuning voltage changes when the tuning switch is operated in the tuning switch circuit 3.

The time constant of the first time constant circuit connected to the collector of the transistor 8 described above is the pulse width T1 of the detection signal.
, power supply voltage (10 Vcc) and FET 6 on level V
Together with t, the value is selected such that a control signal with a pulse width corresponding to the AFT operation inhibition time required when switching channels can be generated.

Note that the connection point between the resistors 9 and 10 is connected to the base of the NPN transistor 17.

This transistor 17 short-circuits a resistor 21 of a series circuit of a capacitor 19 and resistors 20 and 21 inserted between the muting terminal 18 and the ground when it is turned on.
At this time, the audio output is muted by a muting signal generated at the muting terminal 18.

In other words, the audio output is also muted during the AFT operation prohibition period.

An example of the values of each circuit element in the embodiment of the present invention described above is shown below.

Resistor? : 470 (KΩ) Resistor 9, 15: Name [KΩ] Resistor 10: 100 (KΩ) Resistor 12:
22 [Ω] Resistor 13:22 (KΩ) Capacitor 11゜14:1
(μF) Power supply voltage (10 Vcc): 18 (V) In the configuration of the embodiment of the present invention described above, if a detection signal with a pulse width of T1 is generated at the time of channel switching as shown in FIG. 2A, During this time, transistor 16 is turned on as shown in FIG. 2B.

Therefore, the transistor 8 is also turned on during this time as shown in FIG. 2C, and since the value of the resistor 12 is extremely small, the capacitor 11 is immediately charged to the power supply voltage.

Then, since the transistors 8 and 16 are turned off after the period T1 during which the detection signal is generated, the capacitor 11
The charge is discharged through resistors 9 and 10.

Therefore, the control voltage applied to the gate of FET5 changes as shown in the second diagram, and when this control voltage exceeds the on level Vt of FET6, T2 (100~
200 [m5)) Period 1 JET5 is turned on, and AFT operation is prohibited during this period.

Further, when the power is turned on, the power supply voltage gradually rises after the power is turned on and reaches the normal value (Vcc) after a predetermined time, as shown in FIG. 3F.

In this case, since no detection signal is generated as shown in FIG. 3A, the transistor 16 remains off as shown in FIG. 3B.

Further, since the value of the resistor 15 is large as shown in the numerical example given below, a charging current flows from the emitter of the transistor 8 to the capacitor 14 through its base and the resistor 13.

While this charging current is flowing, transistor 8 is turned on.

When the terminal voltage of the capacitor 14, that is, the base voltage of the transistor 8 becomes close to the power supply voltage (zVcc), the charging current to the capacitor 14 stops flowing, and the transistor 8 is therefore turned off.

The operation after this is the same as when the detection signal falls, and the charge stored in the capacitor 11 when the transistor 8 is on is transferred to the resistors 9 and 11 when the transistor 8 is off.
discharge through.

Therefore, the control voltage supplied to the gate of FET6 is as shown in the third diagram, and T3, whose level is higher than Vt.
(If the sequence is 300 (ms)) +7) Period FET 6 is turned on and AFT operation is prohibited.

As is clear from the above, in the AFT control circuit according to the present invention, only the time constant circuit consisting of the resistors 9 and 10 and the capacitor 11 is connected to the gate of the FET 6, and the time constant circuit is connected to the base of the transistor 8. With the simple configuration of adding a time constant circuit consisting of resistor 13 and capacitor 14, the control signal for inhibiting M1 operation, which is required when switching channels and when turning on the power, can be generated without causing malfunction. can occur.

In addition, in the above-mentioned present invention, the present invention was applied to an electronic tuning type tuner, but it can also be applied to a tuner having a mechanical tuning mechanism (rotary switch type, turret type). There are advantages.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an embodiment of the present invention, and FIGS. 2 and 3 are diagrams used to explain its operation. 1 is an electronic tuning tuner, 2 is a tuning control circuit, and 4 is an AFT.
The circuit 6 is an FET for inhibiting AFT operation.

Claims (1)

[Scope of utility model registration request] The collector of the transistor whose emitter is connected to one end of the power supply terminal is connected to the other end of the power supply terminal via a first time constant circuit, and the time constant of this first time constant circuit is set to the time constant necessary for channel switching. A value corresponding to the AFT operation prohibition time is selected, and the connection point between the collector of the transistor and the first time constant circuit is connected to the control terminal of the switching means for inhibiting the AFT operation. A switching means for controlling the conduction state of the transistor and a second time constant circuit are connected in parallel between the terminals, and the switching means is turned on by a detection signal generated when switching channels, and the transistor is turned on. AFT control circuit.