JPS60100471A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the capacity due to a wiring pattern for coupling a plurality of circuit elements formed on a compound semiconductor substrate by coupling the circuit elements with each other, and removing by etching an insulating layer between signal lines wired in parallel on the insulating layer. CONSTITUTION:Air is used for a dielectric material for producing a capacity between wirings, thereby reducing the capacity value. After a resist is, for example, coated on a substrate which includes wiring patterns 3, 3', 3'', a selective exposure and developing are performed to allow the resist to remain only on the patterns 3, 3', 3'', an SiO2 insulating film 2 is chemically etched with an etchant of fluoric acid to a GaAs substrate 1, thereby removing the layer 2 between the wirings except the wiring pattern formed portion. Thus, since the electric line of force passing the layer 2 is replaced by that passing the atmosphere, the capacity between the patterns 3 and 3' can be reduced to substantially a half of the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a structure of a semiconductor device with reduced inter-wiring capacitance.

(b) Background of the Technology Some compound semiconductors have high electron mobility, such as gallium arsenide (GaA) and indium phosphide (Ink), and semiconductor devices that take advantage of this feature have been put into practical use.

For example, the MB8F'BT, which uses a GaAs substrate as a high frequency MH8FET, has already been put into practical use.
Inter-wiring capacitance determines the high frequency limit of GaAs ICs integrated with .

(C) Prior Art and Problems GaAs is currently the most commonly used compound semiconductor material, and one of the reasons for this is that it has high electron mobility.

That is, while 81 has a value of 1350 [cd/V-8], GaAs has a much higher value of 8600 (d/V-S).

FETs are devices that take advantage of this high speed, and logic circuits and memory circuits are made by integrating large numbers of FETs and ETs.

When operating such an integrated circuit at high speed, a problem that arises is not only the structure of the individual unit elements but also the electrostatic capacitance (hereinafter simply referred to as capacitance) of the wiring pattern connecting the unit elements. Embodiment I using Oa AS as a compound semiconductor will be explained below.

Figure 1 shows a cross section of a wiring pattern that connects many circuit elements (TPT) patterned on a chip and is wired in parallel.
There is an insulating layer 2 made of silicon dioxide (8i02) on the s-substrate 1, and on this is gold (Au, ! or aluminum (A)).
The three wiring length turns 3.3' and 3' consisting of 1. - indicates a state of Here, the line width of the wiring patterns 3.3', 3'' decreases as the degree of convergence increases, and in this example, the width is 2 [μm].
The height is 1 [μm], and the wiring patterns 3 and 3'
The distance between them is 4 [μm], and the distance between the wiring patterns 3' and 3N is 10 [μm].

As in this example, '4. lj! i, wiring patterns 3.
3'.

3 are provided close to each other, the signal delay caused by the wiring patency i cannot be ignored.

That is, the GaAs substrate 1 has a high resistance and is thick with a thickness of about 200 [μm], and on top of this is an N! 3 yen)? Wiring patterns 3, 3r, 3t on top of t2
Because of the provision of a capacitance r, not only the capacitance generated between the ground provided under the board 1 and the individual resuscitation patterns 3', 3', 3' but also the capacitance between the wiring patterns becomes a problem. Here, the capacitance C of the parallel plate capacitor is C=j
......Distance between electrodes 1 knee cmJε...
...It is expressed by the dielectric constant of the medium, and is inversely proportional to the distance between the two electrodes, d. Therefore, in the case of the embodiment shown in FIG. To occupy a part\become.

Now, in actual semiconductor HIJL, the packaging density of circuit elements is increasing more and more, and along with this, the number of wiring patterns for each circuit configuration is also increasing proportionally, and it is clear that line capacitance increases the high-speed operation of semiconductor devices. Although this was known, no special measures have been taken to this day.

(d) Object of the Invention An object of the present invention is to provide a structure of a semiconductor device in which the capacitance caused by the wiring pattern l connecting each circuit element of the semiconductor device is reduced.

(e) Structure of the Invention The object of the present invention is to connect signal lines formed on a compound semiconductor substrate by interconnecting one or more circuit elements and partially parallel to each other on an insulating layer. This can be achieved by a semiconductor device characterized in that the insulating layer is removed by etching.

(f) Embodiments of the Invention The present invention reduces the capacitance value by using a dielectric material that causes inter-wiring capacitance.

In other words, in Figure 1, the line 1@2 [μtrt], the interval 4 [μm
] Wiring pattern 3.3' open has 30 Cf F /+
A capacity of a:l is recognized. This 5 constitutes 8iU of the insulating layer 2.

The dielectric constant (ε) of Ga As substrate 1 is 3.9, and the dielectric constant (ε) of Ga As constituting the Ga As substrate 1 is 12.9.

Considering the distribution of electric force when an electric field is applied between wiring patterns 3 + 3'13' in Fig. 1, lines of electric force 4. There are three types: lines of electric force 5 passing through the insulating layer, and lines of electric force 6 passing through the insulating layer 2 and substrate 1.

At this N, the relative dielectric constant of air is 1, so if the area between the marks is the same, there is the least valley when passing through an air layer, and the next is g.
When passing through the A & layer 2, on the other hand, when passing through the insulating layer 2 and the substrate 1, a composite dielectric is formed and the capacitance is the largest in this case.

In the present invention, among the distribution of electric lines of force, 4 lines of electric force passing through the air layer
By increasing the ratio of , the line capacitance is reduced.

In FIG. 2, when the insulating layer between the wirings is removed by etching, this can be done using photolithography.

In other words, resist wiring patterns 3, 3', 3#
After coating the surface of the substrate containing 8I (J
.

By chemically etching the insulating layer 2 down to the Ga substrate 1 or performing dry etching such as reactive ion etching using freon (CF4) and oxygen scum (02) as etchants, as shown in FIG. The insulating layer 2 between the wirings is removed except for the wiring pattern forming area. In this case, the lines of electric force 5 passing through the insulating layer 2 in FIG.
Wiring pattern 3 is replaced by electric line of force 4 passing through the atmosphere.
.

Figure 3 shows an example of reducing the capacitance between lines.The dry etching process shown in Figure 2 was further continued until the thickness was 0.8 μ
When the substrate 1 is dug down by the thickness of the insulating layer 2 of
Since one line can be replaced, the line capacitance can be minimized.

(g) Effects of the invention To describe an example in which the present invention is applicable to a multiplier (multiplier 1) formed on a GaAs substrate, the multiplication speed depends on the signal delay caused by the circuit elements (Fl(T) and the wiring l). Although it depends on the delay of the signal, by implementing the present invention in which the insulating layer 2 is etched up to the surface of the substrate 1, the delay n due to wiring can be reduced to half that of the conventional method.

Specifically, the multiplication speed is 8 in the 8×8 bit multiplier I.
The delay due to the internal wiring (n seconds) occupied 4 (n seconds), but this could be reduced by half, and as a result, the multiplication speed could be increased to 6 (n seconds).

The present invention was made in order to reduce the signal delay caused by wiring capacitance, which has become a problem with the increase in speed of semiconductor devices. can reduce the impact of

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a board on which a wiring pattern is provided;
2 and 3 are cross-sectional views of a wiring board embodying the present invention. In the figure, 1 is a substrate, 2 is an insulating layer, 3.3', 3' are wiring patterns, and 4, 5.6 are lines of electric force.

Claims (1)

[Claims] It has a structure in which a plurality of circuit elements arranged and formed on a compound semiconductor substrate are connected to each other and the insulating layer between the signal lines is partially wired in parallel on the insulating layer, and the insulating layer is removed by etching. A semiconductor device characterized by: