JPH01266786A - Construction of conductor of hybrid integrated circuit and its manufacture - Google Patents
Construction of conductor of hybrid integrated circuit and its manufactureInfo
- Publication number
- JPH01266786A JPH01266786A JP9525288A JP9525288A JPH01266786A JP H01266786 A JPH01266786 A JP H01266786A JP 9525288 A JP9525288 A JP 9525288A JP 9525288 A JP9525288 A JP 9525288A JP H01266786 A JPH01266786 A JP H01266786A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- integrated circuit
- hybrid integrated
- thickness
- copper foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000010276 construction Methods 0.000 title 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000011889 copper foil Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000011888 foil Substances 0.000 claims description 3
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 208000013403 hyperactivity Diseases 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は同一基板上に大電流及び小N6E用の導体が形
成された混成集積回路の導体構造及びその製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a conductor structure of a hybrid integrated circuit in which conductors for large current and small N6E are formed on the same substrate, and a method for manufacturing the same.
(ロ)従来の技術
通常混成集積回路は基板上に所定の導体が形成され、そ
の導体上に複数の半導体素子が固着されてなっている。(B) Prior Art A hybrid integrated circuit typically has a predetermined conductor formed on a substrate, and a plurality of semiconductor elements fixed onto the conductor.
また金属基板からなる混成集積回路において、同一基板
上に01箔を用いて電流容量の大きい導体パターンと電
流容量の小さい導体パターンとを形成する場合は通常第
3図に示す如く、導体(11)の幅の太さで電流容量の
大小が区別されている(このときの銅箔の膜厚は一定で
ある)。In addition, in a hybrid integrated circuit made of a metal substrate, when a conductor pattern with a large current capacity and a conductor pattern with a small current capacity are formed on the same substrate using 01 foil, the conductor (11) is usually used as shown in FIG. The current capacity is determined by the width of the copper foil (the thickness of the copper foil at this time is constant).
(ハ)発明が解決しようとする課題
同一基板とに電流容量の大きい導体と電流容量の小きい
導体ブロックが必要の場合、電流容量大の導体を形成す
る時は、第3図に示す如く、銅箔幅を広くする方法しか
なく、基板の実装面積が小さくなると共に混成集積回路
の小型化という点で問題がある。(c) Problems to be Solved by the Invention When a conductor with a large current capacity and a conductor block with a small current capacity are required on the same substrate, when forming the conductor with a large current capacity, as shown in FIG. The only method available is to increase the width of the copper foil, which poses problems in terms of reducing the mounting area of the board and miniaturizing the hybrid integrated circuit.
また、電流容量の大きい導体を銅箔厚さを大にしてパタ
ーン面積を小坊<シようとすると銅箔厚さが一定である
ので、電流容量の小さい導体ブロックでファインパター
ンを形成することが困難となり、やはり基板の実装面積
が小さくなるという点で問題がある。Also, if you try to reduce the pattern area by increasing the copper foil thickness for a conductor with a large current capacity, the copper foil thickness remains constant, so it is possible to form a fine pattern with a conductor block with a small current capacity. However, there is a problem in that the mounting area of the board becomes smaller.
(ニ)課題を解決するための手段
本発明は上述した問題点に鑑みて為されたものであり、
第1図りに示す如く、混成集積回路基板と、前記基板上
に貼着された銅箔より形成された複数の導体を備え、電
流容量の大きさに対応させ前記導体の膜厚を選択的に異
ならしめて解決する。(d) Means for solving the problems The present invention has been made in view of the above-mentioned problems,
As shown in the first diagram, it is equipped with a hybrid integrated circuit board and a plurality of conductors formed from copper foil stuck on the board, and the film thickness of the conductors is selectively adjusted according to the size of the current capacity. Recognize the difference and resolve it.
(ホ〉作用
この様に本発明に依れば、大電流、小電流用に導体の膜
厚を夫々異ならせ、即ち、大電流用の膜厚を厚く小電流
用の膜厚を薄く形成することにより、大小電流用の導体
幅の差を小さくし高密度導体パターンを形成することが
可能であり、従来と同様に大電流用の導体に大を流を流
すことができる。(E) Effect As described above, according to the present invention, the film thickness of the conductor is made different for large currents and small currents, that is, the film thickness for large currents is thicker and the film for small currents is thinner. By doing so, it is possible to reduce the difference in the width of the conductor for large and small currents and form a high-density conductor pattern, and it is possible to flow a large current through the conductor for large currents as in the conventional case.
(へ)実施例
以下に図面に示した実施例に基づいて本発明の詳細な説
明する。(F) Examples The present invention will be described in detail below based on the examples shown in the drawings.
第1図りは本発明の混成集積回路の導体構造を示す要部
拡大斜視図であり、(1)は放熱性が優れ絶縁処理され
た金属性の基板、(6)(7)は銅箔より形成された大
電流、小電流用の導体、(2)は基板(+)と銅箔とを
接着させる接着性を有する絶縁樹脂層である。The first diagram is an enlarged perspective view of the main part showing the conductor structure of the hybrid integrated circuit of the present invention. The conductor (2) for large current and small current formed is an insulating resin layer having adhesive properties for bonding the substrate (+) and the copper foil.
次に本発明の混成集積回路の製造方法を説明す乙
先ず第1図Aに示す如く、混成集積回路基板り1)を準
備する。混成集積回路基板(1)としては金属、セラミ
ックス、ガラエボ等の基板があるが、銅箔の発熱を容易
に放熱することができる金属のアルミニウム基板を用い
るものとする。そのアルミニウム基板(1)の表面は周
知技術である陽極酸化によって絶縁処理をする。その混
成集積回路基板(1)の−主面に所望厚の銅箔(3)を
貼着する。銅箔(3)は接着性を有するエポキシ樹脂等
の絶縁樹脂層(2)を介して基板(1)に貼着きれる。Next, a method for manufacturing a hybrid integrated circuit according to the present invention will be explained. First, as shown in FIG. 1A, a hybrid integrated circuit board 1) is prepared. The hybrid integrated circuit board (1) may be made of metal, ceramic, glass evo, etc., but a metal aluminum board is used because it can easily dissipate the heat generated by the copper foil. The surface of the aluminum substrate (1) is insulated by anodic oxidation, which is a well-known technique. A copper foil (3) of a desired thickness is adhered to the main surface of the hybrid integrated circuit board (1). The copper foil (3) is adhered to the substrate (1) via an insulating resin layer (2) such as an epoxy resin having adhesive properties.
このとき銅箔(3)の膜厚は大電流用の導体の膜厚と同
一にする。At this time, the thickness of the copper foil (3) is made the same as that of the conductor for large current.
次に第1図Bに示す如く、銅箔(3)の所定領域で銅箔
(3)の膜厚を異ならせる。銅箔(3)の膜厚を異なら
すことで膜厚の厚い領域を大1!流用、薄い領域を小電
流用に用いる。即ち、大電流用の導体が形成される領域
にエツチングレジストを塗布し、小電流用の導体が形成
される領域のみを部分的にハーブエツチングする。小電
流用導体が形成される領域の部分的エツチングの深さは
小電流用の導体となるその表面まで行う。即ち、パター
ン設計で大、小電流用導体の膜厚1,1.が夫々設定き
れるのでその差(t−t+)分だけエツチングすればよ
い。Next, as shown in FIG. 1B, the thickness of the copper foil (3) is varied in predetermined areas of the copper foil (3). By varying the thickness of the copper foil (3), the thick area can be increased by 1! Diversion, use thin area for small current. That is, an etching resist is applied to the area where the conductor for large current is to be formed, and only the area where the conductor for small current is to be formed is partially herbal etched. The depth of the partial etch in the area where the low current conductor is to be formed is up to the surface thereof where the low current conductor is to be formed. That is, in pattern design, the film thickness of conductors for large and small currents is 1, 1, . can be set individually, so it is only necessary to etch by the difference (t-t+).
本実施例では大電流用、小電流用の領域(4)(5)に
区画して説明するが、別に大小電流用の導体領域を区画
する必要性はなくランダムに形成することも可能である
。In this example, the conductor regions for large current and small current will be divided into regions (4) and (5), but there is no need to separate conductor regions for large and small currents, and they can be formed randomly. .
次に第1図Cに示す如く、大小電流領域(4)(5)の
膜厚の異なった銅箔(3)上に感光性レジストをスプレ
一方式、デイプ及びロールコータ方式等を用いて塗布し
、大N、流、小電流用の導体(6)(7)の所望パター
ンに露光・現像する(斜線領域部分)。Next, as shown in Figure 1C, a photosensitive resist is applied onto the copper foil (3) with different film thicknesses in the large and small current regions (4) and (5) using a one-way spray method, a dip coater method, a roll coater method, etc. Then, the desired pattern of the conductors (6) and (7) for large N, current, and small current is exposed and developed (hatched area).
次に第1図りに示す如く、銅箔(3)をエツチングする
と、膜厚tの大電流領域(4)に大電流用の導体(6)
が、膜厚1.の小電流領域(5)に小電流用の導体〈7
)が形成される。Next, as shown in the first diagram, when the copper foil (3) is etched, a large current conductor (6) is formed in the large current area (4) with a film thickness of t.
However, the film thickness is 1. A conductor for small current (7) is placed in the small current region (5) of
) is formed.
図示しないが一方の膜厚の厚い導体上にはパワートラン
ジスタIC及びLSIチップ等の発熱を有する半導体素
子が固着きれ、他方の膜厚の薄い導体上にはチップコン
デンサ、チップ抵抗、及び小信号用トランジスタ等の発
熱性のない半導体素子が固着される。Although not shown, heat-generating semiconductor elements such as power transistor ICs and LSI chips are firmly fixed on one thick conductor, and chip capacitors, chip resistors, and small signal devices are placed on the other thin conductor. A non-heat generating semiconductor element such as a transistor is fixed.
上述した製造方法は夫々の導体(6)(7)の膜厚差が
あまりない場合において有効であ57j(、大小電流用
と夫々の導体(6)(7)の膜厚差が著しく異など)場
合には適応しない。以下に膜厚差が著(7く異なる場合
の製造方法を説明する。The manufacturing method described above is effective when there is not much difference in film thickness between the conductors (6) and (7). ) is not applicable in this case. A manufacturing method in which the film thickness is significantly different will be described below.
基板上に銅箔を貼着するまでは上述と同様であり説明は
省略する。The process until the copper foil is pasted on the board is the same as described above, and the explanation will be omitted.
第2図Aに示す如く、基板(1)上には絶縁樹脂層(2
)を介して所望の膜厚の銅箔(3)が貼着されている。As shown in Figure 2A, there is an insulating resin layer (2) on the substrate (1).
) A copper foil (3) of a desired thickness is attached through the film.
この銅箔(3)の膜厚tは大電流用導体の膜厚に設定し
ておく。基板(1)上に銅箔(3)を貼着した後、銅箔
(3)全面にエツチング用のホトレジストを塗布し、大
電流用導体パターンに露光・現像する。すると大電流用
導体上のみにレジストが残される(斜線領域)。The thickness t of this copper foil (3) is set to the thickness of the large current conductor. After pasting the copper foil (3) on the substrate (1), a photoresist for etching is applied to the entire surface of the copper foil (3), and a conductor pattern for high current is exposed and developed. Resist is then left only on the high current conductor (shaded area).
次に第2図Bに示す如く、銅箔(3)をエッチニゲする
。このときのエツチング深さは小電流用導体の表面、即
ち、膜厚1.になるまで行う。その後、再度銅箔(3)
全面にエツチング用のホトし・・;゛ストを塗布し、小
電流用導体及び大電流用導体(6)のパターンに露光・
現像し、第2図Cに示す如く、小電流用導体(7)とな
る領域と大電流用導体(6)上のみにレジストを残した
後(斜線部分)、露出した銅箔の膜厚1.をエツチング
深去すれば第2図りに示す如く、大/J\電流容量の夫
々の導体(6)(7)差が著しい場合においても同一基
板(1)−Hに電流容量の異なる導体を形成することが
できる。尚、ホトレジストを大電流用導体(6)上に塗
布する場合、最初のレジストは除去しておく方が好まし
い。Next, as shown in FIG. 2B, the copper foil (3) is etched. The etching depth at this time is the surface of the small current conductor, that is, the film thickness is 1. Do it until. After that, copper foil (3) again
Apply a photolith for etching to the entire surface, and expose the pattern of the small current conductor and large current conductor (6).
After developing and leaving the resist only on the area that will become the small current conductor (7) and the large current conductor (6) (hatched area), as shown in Figure 2C, the thickness of the exposed copper foil is 1. .. By etching deeply, as shown in the second diagram, conductors with different current capacities can be formed on the same substrate (1)-H even if there is a significant difference in the current capacities of the respective conductors (6) and (7). can do. Note that when applying photoresist on the large current conductor (6), it is preferable to remove the initial resist.
上述した蝕刻工程をくり返して行えば同一基板上に大、
中及び小電流用の導体、即ち、電流容量の多動化に対応
した導体を形成することも可能である。If the above-mentioned etching process is repeated, large and
It is also possible to form conductors for medium and small currents, that is, conductors corresponding to hyperactivity in current capacity.
斯る本発明に依れば、同一基板上に選択して電流容量の
異なる導体を形成することができるので、基板の大きさ
を変更せずにより大きさの異なった電流容量の導体を形
成することができる。According to the present invention, conductors with different current capacities can be selectively formed on the same substrate, so conductors with different current capacities can be formed without changing the size of the substrate. be able to.
(ト)発明の効果
以上に詳述した如く、本発明に依れば、同一基板上に膜
厚の異なる導体即ち、電流容量の異なる導体を形成する
ことができるため、従来と同一基板で電流容量の大きい
導体形成することができ、混成集積回路の小型化を容易
にすることができる。(G) Effects of the Invention As detailed above, according to the present invention, conductors with different film thicknesses, that is, conductors with different current capacities can be formed on the same substrate. A conductor with a large capacity can be formed, and a hybrid integrated circuit can be easily miniaturized.
また本発明では従来の製造工程をそのまま用いて製造す
ることができる利点を有する。Furthermore, the present invention has the advantage that it can be manufactured using conventional manufacturing processes as they are.
第1図A乃至第1図りは本発明の混成集積回路の導体の
製造方法を示す斜視図、第2図A乃至第2図りは他の製
造方法を示す斜視図、第3図は従来例を示す斜視図であ
る。
(1)・・・混成集積回路基板、 (2)・・・絶縁樹
脂層、(3)・・・銅箔、 (4)(5)・・・大小電
流領域、 (6)(γ)・・・導体。1A to 1D are perspective views showing a method for manufacturing a conductor for a hybrid integrated circuit according to the present invention, FIGS. 2A to 2D are perspective views showing another manufacturing method, and FIG. 3 is a perspective view showing a conventional method. FIG. (1)...hybrid integrated circuit board, (2)...insulating resin layer, (3)...copper foil, (4)(5)...large and small current region, (6)(γ). ··conductor.
Claims (10)
箔より形成された複数の導体を備え、電流容量の大きさ
に対応させ前記導体の膜厚を選択的に異ならしめたこと
を特徴とする混成集積回路の導体構造。(1) It comprises a hybrid integrated circuit board and a plurality of conductors formed from copper foil stuck on the board, and the film thickness of the conductors is selectively varied according to the size of current capacity. A conductor structure of a hybrid integrated circuit characterized by:
よって区画されていることを特徴とする請求項1記載の
混成集積回路の導体構造。(2) The conductor structure of a hybrid integrated circuit according to claim 1, wherein the conductor is divided on the substrate according to the magnitude of the current capacity.
使い分けることを特徴とする請求項1記載の混成集積回
路の導体構造。(3) The conductor structure of a hybrid integrated circuit according to claim 1, wherein the conductors having different film thicknesses are used for large current and small current.
着し、前記基板の所定領域で前記銅箔の膜厚を異ならせ
た後、前記膜厚の異なる夫々の前記銅箔を蝕刻して前記
同一基板上に膜厚の異なる導体を選択的に形成すること
を特徴とする混成集積回路の導体製造方法。(4) After adhering a copper foil of a desired thickness to one main surface of a hybrid integrated circuit board and varying the thickness of the copper foil in a predetermined region of the board, each of the copper foils having a different thickness A method for manufacturing a conductor for a hybrid integrated circuit, comprising selectively forming conductors having different thicknesses on the same substrate by etching a foil.
記銅箔の膜厚を異ならしめることを特徴とする請求項4
記載の混成集積回路の導体製造方法。(5) Predetermined areas of the copper foil are partially etched to make the thickness of the copper foil different.
A method of manufacturing a conductor for a hybrid integrated circuit as described.
徴とする請求項4記載の混成集積回路の導体製造方法。(6) The method of manufacturing a conductor for a hybrid integrated circuit according to claim 4, wherein the etching step is performed at least once.
表面まで行うことを特徴とする請求項6記載の混成集積
回路の導体製造方法。(7) The method of manufacturing a conductor for a hybrid integrated circuit according to claim 6, wherein the etching step is carried out from the maximum thickness of the conductor to the surface of the next thickness.
区画して形成することを特徴とする請求項4記載の混成
集積回路の導体製造方法。(8) The method of manufacturing a conductor for a hybrid integrated circuit according to claim 4, wherein the conductors having different film thicknesses are formed by dividing the conductors into predetermined regions on the substrate.
とを特徴とする請求項1及び4記載の混成集積回路の導
体構造及びその製造方法。(9) The conductor structure of a hybrid integrated circuit and its manufacturing method according to claims 1 and 4, wherein the steel foil is bonded with an insulating resin having adhesive properties.
板であることを特徴とする請求項1及び4記載の混成集
積回路の導体構造及びその製造方法。(10) The conductor structure of a hybrid integrated circuit and its manufacturing method according to claims 1 and 4, wherein the hybrid integrated circuit board is an insulated metal substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63095252A JP2664408B2 (en) | 1988-04-18 | 1988-04-18 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63095252A JP2664408B2 (en) | 1988-04-18 | 1988-04-18 | Manufacturing method of hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01266786A true JPH01266786A (en) | 1989-10-24 |
JP2664408B2 JP2664408B2 (en) | 1997-10-15 |
Family
ID=14132565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63095252A Expired - Lifetime JP2664408B2 (en) | 1988-04-18 | 1988-04-18 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2664408B2 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10205592A1 (en) * | 2002-02-11 | 2003-08-28 | Ksg Leiterplatten Gmbh | Process for the production of a semi-finished product for printed circuit boards |
EP1363483A2 (en) * | 2002-05-14 | 2003-11-19 | rotra Leiterplatten Produktions- und Vetriebs-GmbH | Multilayer printed circuit board laminate and process for manufacturing the same |
DE10221552A1 (en) * | 2002-05-14 | 2003-11-27 | Rotra Leiterplatten Produktion | Multi layered electronic circuit board has circuit areas formed in a series of etching operations and filling of regions with a plastic material |
WO2005081311A1 (en) * | 2004-02-24 | 2005-09-01 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method thereof |
EP1830611A1 (en) * | 2004-11-19 | 2007-09-05 | Multi, Inc. | Printed wiring board and production method of printed wiring borad |
KR100874047B1 (en) * | 2004-02-24 | 2008-12-12 | 산요덴키가부시키가이샤 | Circuit device and manufacturing method thereof |
CN103338595A (en) * | 2013-07-09 | 2013-10-02 | 皆利士多层线路版(中山)有限公司 | Heavy-copper step circuit board and preparation method thereof |
CN103987202A (en) * | 2014-05-20 | 2014-08-13 | 深圳市景旺电子股份有限公司 | PCB manufacturing method for controlling local bronze thickness and PCB |
CN104080275A (en) * | 2014-03-12 | 2014-10-01 | 博敏电子股份有限公司 | Method for manufacturing stepped circuit board |
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JP2016207916A (en) * | 2015-04-27 | 2016-12-08 | 東和プリント工業株式会社 | Printed circuit board and manufacturing method thereof |
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JPS58110090A (en) * | 1981-12-24 | 1983-06-30 | 富士通株式会社 | Conductor pattern for plan circuit |
JPS58138363U (en) * | 1982-03-11 | 1983-09-17 | オリジン電気株式会社 | Printed wiring board for power |
JPS60257191A (en) * | 1984-06-02 | 1985-12-18 | 株式会社日立製作所 | Printed circuit board |
JPS622591A (en) * | 1985-06-28 | 1987-01-08 | 電気化学工業株式会社 | Manufacture of metal base hybrid integrated circuit board |
JPH01253293A (en) * | 1988-03-31 | 1989-10-09 | Yamaha Motor Co Ltd | Printed wiring substrate and manufacture thereof |
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JPS58110090A (en) * | 1981-12-24 | 1983-06-30 | 富士通株式会社 | Conductor pattern for plan circuit |
JPS58138363U (en) * | 1982-03-11 | 1983-09-17 | オリジン電気株式会社 | Printed wiring board for power |
JPS60257191A (en) * | 1984-06-02 | 1985-12-18 | 株式会社日立製作所 | Printed circuit board |
JPS622591A (en) * | 1985-06-28 | 1987-01-08 | 電気化学工業株式会社 | Manufacture of metal base hybrid integrated circuit board |
JPH01253293A (en) * | 1988-03-31 | 1989-10-09 | Yamaha Motor Co Ltd | Printed wiring substrate and manufacture thereof |
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DE10205592B4 (en) * | 2002-02-11 | 2008-01-03 | Ksg Leiterplatten Gmbh | Method for producing a semifinished product for printed circuit boards |
DE10205592A1 (en) * | 2002-02-11 | 2003-08-28 | Ksg Leiterplatten Gmbh | Process for the production of a semi-finished product for printed circuit boards |
EP1363483A2 (en) * | 2002-05-14 | 2003-11-19 | rotra Leiterplatten Produktions- und Vetriebs-GmbH | Multilayer printed circuit board laminate and process for manufacturing the same |
DE10221552A1 (en) * | 2002-05-14 | 2003-11-27 | Rotra Leiterplatten Produktion | Multi layered electronic circuit board has circuit areas formed in a series of etching operations and filling of regions with a plastic material |
EP1363483A3 (en) * | 2002-05-14 | 2005-10-05 | rotra Leiterplatten Produktions- und Vetriebs-GmbH | Multilayer printed circuit board laminate and process for manufacturing the same |
KR100874047B1 (en) * | 2004-02-24 | 2008-12-12 | 산요덴키가부시키가이샤 | Circuit device and manufacturing method thereof |
JPWO2005081311A1 (en) * | 2004-02-24 | 2007-08-02 | 三洋電機株式会社 | Circuit device and manufacturing method thereof |
WO2005081311A1 (en) * | 2004-02-24 | 2005-09-01 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method thereof |
US7714232B2 (en) | 2004-02-24 | 2010-05-11 | Sanyo Electric Co., Ltd. | Circuit device and method of manufacturing the same |
JP4785139B2 (en) * | 2004-02-24 | 2011-10-05 | オンセミコンダクター・トレーディング・リミテッド | Circuit device and manufacturing method thereof |
EP1830611A1 (en) * | 2004-11-19 | 2007-09-05 | Multi, Inc. | Printed wiring board and production method of printed wiring borad |
EP1830611A4 (en) * | 2004-11-19 | 2009-06-24 | Multi Inc | Printed wiring board and production method of printed wiring borad |
CN103338595A (en) * | 2013-07-09 | 2013-10-02 | 皆利士多层线路版(中山)有限公司 | Heavy-copper step circuit board and preparation method thereof |
CN104080275A (en) * | 2014-03-12 | 2014-10-01 | 博敏电子股份有限公司 | Method for manufacturing stepped circuit board |
CN103987202A (en) * | 2014-05-20 | 2014-08-13 | 深圳市景旺电子股份有限公司 | PCB manufacturing method for controlling local bronze thickness and PCB |
JP2016207916A (en) * | 2015-04-27 | 2016-12-08 | 東和プリント工業株式会社 | Printed circuit board and manufacturing method thereof |
CN105744735A (en) * | 2016-04-26 | 2016-07-06 | 广东欧珀移动通信有限公司 | Electronic equipment, printed circuit board and preparation method of printed circuit board |
WO2022162875A1 (en) * | 2021-01-29 | 2022-08-04 | サンケン電気株式会社 | Semiconductor power module |
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