JPS599993B2 - Clock frequency feedback selective shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift register with self-selectable clock frequency.

Conventionally, the clock frequency that determines the shift speed in the shift register has been determined in advance, and the shift speed cannot be changed depending on the progress of the shift in the shift register.

Therefore, for example, when scanning and selecting displays using a shift register, if the shift speed is increased in order to reduce the current consumption of the display, all the displays will go around once and the first display will be driven again. The cycle time will also be shortened. In this case, if the ratio of the energization time to cycle time, that is, the energization rate for one display device, is greater than the predetermined energization rate for that display device, it is necessary to adjust the duration of the output pulse so that the energization rate is within the predetermined energization rate. be. Therefore, it is necessary to include a register for blank feeding in the shift register to adjust the duration of the output pulse, but this requires the provision of a large number of extra registers. The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to provide a shift register that can change the shift speed depending on the progress of shifting in the shift register. It is in.

To achieve this object, the clock frequency feedback selective shift register of the present invention includes a clock source including a plurality of clock oscillators, a shift register formed by cascading a plurality of registers, and an arbitrary stage of the shift register. a clock gate consisting of a plurality of gates that are controlled by the output of a register and selectively open when data is present in the register to supply the output of a particular clock oscillator in the clock source to the shift register as a shift clock; The present invention is characterized in that the shift speed can be changed according to the progress of shifting in the shift register. Examples will be described below.

FIG. 1 is a circuit diagram showing the structure of an embodiment of a clock frequency feedback selective shift register of the present invention.

In the figure, A is a register, 1 is a first stage register, 2 is a second stage register, 3 is a third stage register, and 4 is a register.
is the fourth stage register, 5 is the fifth stage register, a is the first selection feedback line, b is the second selection feedback line, c is the third selection feedback line, d
is the fourth selected feedback line, and e is the fifth selected feedback line. Also B
is a clock gate, where 6 is an input gate, 7 is an inverter, 8 is a clock 1 selection gate, and 9 is a clock 2 gate.
10 is a selection gate, f is a clock 1 selection line, g is a clock 2 selection line, h is a gate 8 output line, 1 is a gate 9 output line, and j is a shift clock line. C is a clock oscillator, 11 is a clock 1 oscillator,
12 is a clock 2 oscillator, k is a clock 1 line, and t is a clock 2 line. FIG. 2 is a time chart showing the signals of each signal line in the circuit of FIG. 1, in which the upper side of each signal represents state 81'' and the lower side represents state 60''. In FIG. 1, the clock 1 oscillator 11 and the clock 2 oscillator 12 of the clock oscillator C are always operating in synchronization with each other and produce pulse trains as shown in the clock 1 line k and the clock 2 line t in FIG. 2, respectively. It is outputting.

In the shift register A, the data in the first stage register 1 is moved to the second stage register 2 by the first pulse of the clock signal on the shift clock line j, and the data moved to the second stage register 2 is transferred to the second stage register 2 by the first pulse of the clock signal on the shift clock line j. The pulse moves to the third stage register 3, and the third stage of the clock signal is
The data is sequentially moved to the fourth stage register 4 and the fifth stage register 5 by the pulse and the fourth pulse. The first selection feedback line a is from the first stage register 1, and the second selection feedback line b is from the second stage register 5.
The third selection feedback line c is output from the third stage register 3, the fourth selection feedback line d is output from the fourth stage register 4, and the fifth selection feedback line e is output from the fifth stage register 5. The signal on each feedback line is 611 when the corresponding register contains data, and becomes 601 when no data is entered.

When the signal on the second selection feedback line b or the third selection feedback line c entering the input gate 6 of clock gate B is 61'', the clock 1 selection line f becomes 601, and therefore the clock 2 selection line g becomes 616. .

This causes the clock 1 selection gate 8 to close and the gate to open.
The output line h of the clock 2 gate 8 becomes 61'', the clock 2 selection gate 9 is opened, and a signal with the opposite polarity to the clock 2 line t is produced on the gate 9 output line 1. Therefore, the output gate 10 that drives the shift register A The shift clock line j, which is the output signal of
When the signals on the selection feedback line b and the third selection feedback line c are both '07', the clock 1 selection line f! ′! 611, and therefore the clock 2 selection line g becomes "0".

As a result, the clock 2 selection gate 9 closes and the gate 9 output line 1 becomes 1', and the clock 1 selection gate 8 opens and a signal with the opposite polarity to the clock 1 line k is generated on the gate 8 output line h. . Therefore, a signal of opposite polarity to the gate output line h is generated on the shift clock line j. This signal has the same polarity as the signal on clock 1 line k. In this way, the data in shift register A is clocked at the frequency of clock 2 when second stage register 2 or third stage register 3 contains data; When there is no data in any of the clocks, the clock moves at the frequency of clock 1.

The circuit shown in Figure 1 operates in this way, so if you use it, you can selectively drive one display at a time when scanning a group of magnetically held displays that consume a large amount of current when driving. In addition to reducing current consumption compared to driving the display group at - degrees, it is also possible to prepare one register for blank feed and select the clock frequency so that the data remains in that register for a longer period of time. For example, the condition regarding the energization rate of the display device can also be satisfied.

Furthermore, in the same way, devices other than the display can be driven. In addition, if used as a time sequencer, when serial tasks are performed sequentially in time, the time allowed for each task can be selected from the registers corresponding to each task. In the above-described embodiment, the case where the shift speed is switched between two types has been described, but it goes without saying that the present invention is not limited to this and can be applied to any number of shift speeds.

As explained above, according to the clock frequency feedback selection type shift register of the present invention, the duration of a selected state when data is entered into the register can be selected using the output of the register containing data. , there is an advantage that the moving time of each register constituting the shift register can be changed depending on the purpose with a simple configuration without requiring any special means for generating a clock switching output.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing the configuration of an embodiment of the clock frequency feedback selective shift register of the present invention, and Fig. 2 is a time diagram showing the signals of each signal line in the circuit of Fig. 1. It's a chat. A...Shift register, 1...1st stage register, 2...2nd stage register, 3...
...3rd stage register, 4...4th stage register,
5...Fifth stage register, B...Clock gate, 6...Input gate, 7...
Inverter, 8...Clock 1 selection gate, 9
...Clock 2 selection gate, 10...
Output gate, C...Clock oscillator, 11
...Clock 1 oscillator, 12...
Clock 2 oscillator.

Claims (1)

[Claims] 1. A clock source including multiple clock oscillators, a shift register consisting of multiple registers connected in cascade,
a plurality of units controlled by the output of a register in any stage of the shift register, selectively opened when data is present in the register, and supplying the output of a specific clock oscillator in the clock source to the shift register as a shift clock; What is claimed is: 1. A clock frequency feedback selection type shift register, comprising: a clock gate consisting of a gate; and a shift speed can be changed according to the progress of shifting in the shift register.