JP2788401B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as an LED road information board.

[0002]

2. Description of the Related Art At present, a display device such as a road information board includes a display element array in which display elements such as LEDs are arranged in a dot matrix, and a drive circuit for controlling the driving of each element. The units are further arranged in a matrix to construct a large-screen display unit, display data is sent from the control unit to the display unit, and elements at predetermined positions of a large number of display element groups of the display unit are turned on or off. A structure in which desired characters, graphics, and the like are displayed by blinking is used.

[0003] As a signal transfer system of this type of display device, conventionally, each display unit of a display unit is connected in series to a control unit, and display data is sequentially transmitted to each display unit by a serial signal. In general, a system in which data is transferred later is generally used. In each display unit, a shift register is generally used for taking in display data from the control unit and sending the data to the next unit.

[0004]

However, according to the display device of the system described above, there is a problem that the number of display units that can be connected to one system of display is limited.

That is, the clock signal sent from the control unit together with the display data has a shorter pulse duration (pulse width) as it goes through each display unit in a number of stages (see FIG. 6). Side becomes extremely short and transmission of display data becomes impossible. For example, experiments have shown that the pulse duration of the clock signal is reduced by about 3 ns each time one display unit is passed. Therefore, if the frequency of the clock signal (duty ratio: 50%) is 1 MHz, for example, , 500 ns / 3 ns ≒ 167, if 167 or more display units are connected to one system, the H side of the clock signal will disappear.

Therefore, as a countermeasure against the above, conventionally, as shown in FIG. 7, for example, display unit groups U1, U2,.
Is divided into a plurality of systems (four systems) and the display data and the clock signal are individually transferred for each system, or the frequency of the clock signal is sufficiently increased while the system of the display remains one system. A method such as lowering the transmission is adopted.

However, according to the former method, a control unit (11... 14) is required for each divided system, and the number of signal cables increases according to the number of divided systems. There is a problem that the cost of the entire apparatus is high.

On the other hand, according to the latter method, it takes a lot of time to finish sending the display data, so that the change when shifting from one display content to another display content is delayed, and the alternate display and the display are not performed. There is a drawback that the display of animation or the like becomes inappropriate.

The cause of the reduction in the pulse duration of the clock signal every time the signal passes through the display unit is due to the Tphl (output H → L propagation time) and Tplh of the inverter (Schmitt circuit) incorporated in each display unit. (Output L
→ H propagation time), Tthl (output H → L transition time)
And Ttlh (output L → H transition time) and Vt +
(Positive threshold voltage) and Vt- (negative threshold voltage), and the capacitance load may be different between the inside of the display unit and the signal transfer line outside the display unit.

The present invention has been made in view of the above circumstances, and provides a display device of a system that can display one system even if the number of connected display units is large and can transmit display data at high speed. Is the intended purpose.

[0011]

A structure for achieving the above object will be described with reference to FIGS. 1 to 3 corresponding to the embodiment. The display device of the present invention comprises a display unit group U1.
.. A correction circuit 3 is connected between the unit Un at a predetermined position of UN and the display unit Un + 1 at the next stage, and the correction circuit 3 is connected to the clock from the display unit Un at the previous stage of this circuit. It is characterized in that the signal is shaped and the pulse duration is lengthened and output to the next display unit Un + 1.

[0012]

The waveform of the clock signal passed through the display units U1, U2,... Un of a plurality of stages is shaped by the correction circuit 3 so that the pulse duration is extended, as shown in FIG. The pulse duty ratio of the signal
State at time point P1 when control section 1 outputs (duty ratio: 5)
0%).

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, the entire display device includes a control unit 1 and a display unit 2 in which a large number of display units U1, U2,... UN are arranged in a matrix.

The control unit 1 is controlled by the CPU 1a.
Display data (serial data) and enable signals (EN signals), latch signals, and clock signals (C
LK signal). The EN signal is a signal for turning on / off a driver 2D, which will be described later, to perform light control and the like.

On the other hand, each display unit U1 (U2,... UN)
As shown in FIG. 2, a display element such as an LED is, for example, 16 ×
A display element array 2A arranged in a matrix of 16 dots (= 256 dots) and a drive circuit C for controlling lighting of each element are provided.

The drive circuit C stores the display data (serial data) sent from the control unit 1 in synchronization with the CLK signal in a shift register 2S, and stores the data taken in the register in accordance with the latch signal. Latch circuit 2L and display element array 2A based on the stored data
This is a circuit in which a driver 2D for driving each element is incorporated. In the drive circuit C, an inverter is provided at each of an input stage and an output stage of each signal.

It should be noted in the embodiment of the present invention that the correction circuit 3 is provided between the unit Un at a predetermined position of the display unit group U1, U2,... UN and the display unit Un + 1 at the next stage. At the point where they are connected.

The correction circuit 3 includes a display unit U in the preceding stage.
3 is a circuit for shaping the waveform of the clock signal from the n by an operation described later, and outputting the shaped signal to the next-stage display unit Un + 1, as shown in FIG. CLK, etc., are provided at the input stage and the output stage, respectively, with inverters Ini... Ini and Ino.
ND gates 3e and 3d are connected.

The output signal of the input-side inverter Ini and the signal output from the inverter Ini and passed through the shift register 3a are led to the AND gate 3d of the CLK line. The shift register 3a and the AND gate 3
An inverter 3c is connected to the shift register 3d, and an oscillation circuit 3b for generating a clock pulse is connected to the shift register 3a.

The frequency of the clock pulse generated by the oscillation circuit 3b is set smaller than the duration (pulse width) of the clock signal output from the control unit 1 (see FIG. 4). Also, the AND gate 3e of the display data line is
The connection is made for the purpose of compensating for a time delay caused by connecting the AND gate 3d to the CLK line and preventing data loss due to a phase shift between the display data and the clock signal.

Next, the operation of the correction circuit 3 will be described with reference to the timing waveform chart shown in FIG. 4 and the previous FIGS. First, as shown in FIG. 1, the position before the clock signal output from the control unit 1 enters the first display unit U1 is set to P1 and the position exiting from the nth display unit Un, that is, to the correction circuit 3. The position before entering is P2, and the position passing through the correction circuit 3 is P3. As shown in FIG. 3, the input and output of the shift register 3a of the correction circuit 3 are Q1 and Q3, respectively, and the output of the oscillation circuit 3b is Q2 and AND.
The output of the gate 3d is Q4.

Assuming that the clock signal after passing through the n-stage display units U1,... Un has the waveform shown by P2 in FIG. 4, the output Q3 of the shift register 3a outputs the clock signal P2 of "L". The state rises and becomes "H" when a period of the state "" has elapsed for a predetermined time. The elapsed (delay) time at this time is given by a clock pulse which is the output Q2 of the oscillation circuit 3b, and the number of clock pulses is a number corresponding to half of the cycle of the initial clock signal P1 (pulse duration). At this point, the signal Q3 rises, at which point the output Q4 of the AND gate 3d switches from H to L, and the output P3 of the output side inverter Ino becomes "H".
State.

Next, when the clock signal P2 rises and the inverted signal Q1 changes from H to L, the output Q3 of the shift register 3a changes from H to L at the same time. At this point, the output Q4 of the AND gate 3d changes. Therefore, the output P3 of the output-side inverter Ino remains at "H", and thereafter, when the clock signal P2 changes from H to L, the output signal P3 switches to "L". And the equivalent operation is sequentially repeated. By such an operation, the clock signal P2 arriving at the correction circuit 3 is shaped into a signal having substantially the same waveform as the initial clock signal P1, and the shaped signal P3 is converted to the next-stage display unit Un. Sent to +1.

Here, the correction circuit is not limited to the circuit configuration shown in FIG. 3. For example, as shown in the waveform diagram of FIG. A circuit configured to detect the falling (or rising) of the clock signal P2 and perform an analog correction operation such as generating a desired pulse width may be employed.

In the above embodiment, the correction circuit 3 is provided at one position in the display system. However, the correction circuit 3 may be provided at a plurality of positions. According to the present invention, in addition to the display device of the above-described example, a plurality of shift registers for drive control of the display element array are connected in series to constitute one display unit. It goes without saying that the present invention is also applicable to display devices connected in series.

[0026]

As described above, according to the display device of the present invention, since the correction circuit is connected in the middle of the display system in which a plurality of display units are connected in series, a plurality of display units are provided. Even if the pulse width of the clock signal becomes extremely short by passing through, the waveform distortion is shaped by the correction circuit,
The same waveform signal as the initial clock signal can be transmitted to the subsequent display units. As a result, even if the number of connected display units is large, a single system can transmit signals such as display data, and it is not necessary to lower the frequency of the clock signal. As a result, it is possible to improve the quality of alternate display and animation display while suppressing costs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a display unit U1 (U2,... UN) of the embodiment.

FIG. 3 is a block diagram showing a configuration of a correction circuit 3 according to the embodiment of the present invention.

FIG. 4 is a timing waveform chart showing the operation of the correction circuit 3;

FIG. 5 is a waveform chart for explaining a modification of the correction circuit.

FIG. 6 is a waveform diagram showing a change in a clock signal via a plurality of display units.

FIG. 7 is a view for explaining a conventional example of a method for avoiding the influence of a change in the clock signal.

[Explanation of symbols]

 1 control unit 1a CPU 2 display unit U1, U2,... Un, Un + 1,... UN display unit 2A display element array 2D driver 2L latch circuit 2S shift register 3 correction circuit 3a shift register 3b oscillation circuit (clock pulse generation Source) 3c inverter 3d, 3e AND gate

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sakae Ito 29-1 Mingoku Shinoda, Miwa-cho, Kaifu-gun, Aichi Prefecture Inside Nagoya Denki Kogyo Co., Ltd. (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 1/00-5/40

Claims (1)

(57) [Claims] 1. A display unit comprising a plurality of display units arranged therein, and a control unit for outputting a signal to the unit group.
A display element array in which a plurality of display elements are arranged in a matrix, and a shift register for drive control of the display elements are provided, and these display units are connected in series to the control unit. In a display device configured so that display data and a clock signal are sequentially sent to a shift register of each display unit, a unit at a predetermined position of the display unit group and a display unit at the next stage are The correction circuit is connected between the two, and the correction circuit is configured to shape the waveform of the clock signal from the display unit at the preceding stage of the circuit, lengthen the pulse duration and output the pulse to the next display unit. A display device, comprising: