JPS5999813A - Pll synthesizer receiver - Google Patents

Abstract

PURPOSE:To attain quick scanning and channel selection by providing a channel selection PLL synthesizer, a channel selection pulse generator, and a counter and the like, and changing the frequency of a channel selection pulse from larger to lower one when the count value of the counter is a prescribed value or over. CONSTITUTION:The channel selection pulse generating circuit 31 generates the channel selection pulse based on the operation of scanning and channel selection switches 29U, 29D, and the pulse is applied to a programmable frequency divider 22. The counter 33 counts the channel selection pulse from the generator 31 and controls the frequency of the channel selection pulse from the count output. When the count value of the counter 33 is a prescribed value or over, the frequency of the channel selection pulse is changed larger from a small value. The channel selecting scanning is attained quickly and automatically by having only to operate the key of a channel selection switch 29 when the band width is broader and the scanning and channel selection require quick operation as the case with a short-wave broadcast.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an improvement of a PLL synthesizer receiver that enables scanning tuning.

BACKGROUND TECHNOLOGY AND PROBLEMS In conventional PLL synthesizer side receivers, when the scanning tuning range is wide, tuning takes time, so a fast forward υ scanning tuning switch is used in addition to the normal scanning tuning switch. Establishment and regular scanning selection as necessary.

However, in this case, each key of the two scanning channel selection switches must be pressed at the same time, which is practically inconvenient.

Purpose of the Invention In view of the above, the present invention has an object to automatically increase the scanning tuning speed when the scanning tuning range during scanning tuning is wide by simply operating the key of one scanning tuning switch. Therefore, we would like to propose a PLL switch/seizer receiver in which scanning and channel selection can be performed quickly.

Summary of the Invention The PLL synthesizer receiver according to the present invention includes a PL for channel selection.
an L synthesizer, a tuning iR pulse generation means for generating a tuning pulse based on the operation of a scanning tuning switch, and supplying the tuning signal to a programmable frequency divider of the tuning PLL synthesizer; The S4 station/P pulse is counted by the channel selection pulse generation means, and the count output is used to control the frequency of the channel selection/P pulse of the channel selection A pulse generation means, and the count value of this counting means is When the frequency is above a predetermined value, the frequency of the channel selection A?rus is changed from low to high.

According to the present invention, by simply operating the key of one scanning channel selection switch, when the scanning channel selection range is wide, the scanning channel selection speed is automatically adjusted to speed, and the scanning channel selection is performed quickly. A PLL synthesizer receiver can be obtained.

Example An embodiment of the present invention will be described below with reference to FIG.

This embodiment includes FM Lazoo broadcasting, AM medium wave radio broadcasting,
This is a case where the present invention is applied to a radio receiver that receives AM shortwave radio broadcasting (2 bands).

(1) is an FM radio receiving section, and (2) is an AM radio receiving section.

First, I will explain the FM radio receiving section.(3)
l″ii antenna 4) is a high frequency amplifier circuit, (5) is a frequency conversion circuit, (6) and (7) are its frequency mixer and local oscillator, respectively, (8) is an intermediate frequency amplifier, and (9) is an FM demodulator. device, 0 (j is a multiplexer, (1, IL),
(IIR) is an output terminal for left and right audio signals.

Next, the AM radio receiving section (2) will be explained. 0□□
□ is an antenna, α) is a high frequency amplifier, negative ◆ is a frequency conversion H(, αυ), (IQ is its frequency mixer and local oscillator, respectively, (1 is an intermediate frequency amplifier, and 0→ is an AM detector. The audio signal (monaural signal) from the AM detector ◇ is supplied to the left and right audio Ka high output terminals 11L and 11R via a multiplexer (1υ).

(4) shows the PLL synthesizer for channel selection as a whole,
This will be explained below. ■υ is the local oscillator (7).

The Norris scaler 'i +221 to which the local oscillation signal from any one of 0Q is supplied is! Programmable frequency divider, 03, supplied with the frequency signal from the restarter Cυ
) is a phase comparator, and 120 is a reference oscillator (crystal oscillator). Then, in the phase comparator (c), the frequency signal from the glogrammer 7 frequency divider C221 and the reference oscillator (2
1) is phase-compared with the reference oscillation signal from (7) is supplied as a tuning signal to each variable capacitance diode of the resonant circuit, and the AM radio receiving section (
For 2), it is supplied as a tuning signal to each variable capacitance diode of the tuning circuit of the high frequency amplifier 0→ and the resonant circuit of the local oscillator 0Q via the other low-pass filter (27). (25) is the last channel memory which stores the last selected frequency division ratio in the programmable frequency divider (2 outputs) and stores the division ratio selected last in the programmable frequency divider (2 outputs).
2.

0 is a band selection switch, and by switching this, the FM'f7-, -'o receiving section (1) and the reaching soo receiving section (2) can be switched by supplying or not supplying power to them. At the same time, in the main receiving section (2), switching between the medium wave and short wave SWI and SW2 bands is performed by switching each coil of the tuning circuit of the high frequency amplifier 0 → and the resonant circuit of the local oscillator αQ. .

(2 barrels are scanning tuning up and down operation switches (2 barrels)
9U).

(29D) is a scanning tuning signal generation circuit which generates up and down scanning tuning signals and a scanning tuning signal indicating that scanning tuning is in progress by suppressing the key.

430) In the H microbunching user, each block surrounded by a broken line represents a functional block constituted by a computer program. (
3+) is a channel selection pulse generating means for generating a channel selection pulse. The channel selection signal from the channel selection signal generating means 0υ is supplied to the programmable frequency divider (221) of the PLL synthesizer for channel selection (A), and its frequency division ratio is controlled. The frequency of the tuning pulse from the pulse generating means <3]) is controlled by the discrimination circuit (three circuits).The scanning tuning signal from the scanning tuning signal generation circuit (c) The signal is supplied to a determining means @ for determining whether the frequency is down, and the frequency division ratio of the programmable frequency divider (counter) is controlled to increase or decrease depending on whether the frequency is up or down.

Distinguishing means (3a is the switching signal from the band changeover switch 0 and the channel selection/zerus generation means 0]) determines the counting output of the counting means for counting the number of channel selection/zeros of the The station pulse generation means controls the frequency of the station selection and main pulse from 0υ. Further, the counting means (g) performs counting when the scanning tuning signal is output from the scanning tuning signal generation circuit (c), and resets the count contents when the scanning tuning signal is no longer output.

When FM radio broadcasting or AM midwave/geo broadcasting is selected by the band selector switch 05), the scanning tuning signal is generated based on the up or down tuning signal from the scanning tuning signal generation circuit. Virus generation means: Select a frequency that is 1 times faster than the standard frequency.Gruss is generated, but shortwave radio broadcasting is received (when it is -, the following is a fake
As will be explained, the frequency of the scanning channel selection and 2-russe generation means (tuning based on success) becomes;

ν1j, +base station from scanning channel selection, f pulse generation means φQ, 9) After counting 10 L pulses by counting means oi, when shortwave SWI /-t wave is being received, , the frequency of the channel selection signal is 10 times faster than the standard frequency, and the SW
The tuning pulse generating means 0◇ is controlled by the discriminating means 6 so that the frequency of the Lj1 tuning pulse becomes 20 times faster than the standard frequency when tuning two bands.

FIG. 2 shows a flowchart of the Zorogram of the microphone 0 computer t30) when receiving and transmitting shortwave broadcasting. That is, by supplying the scanning tuning signal from the scanning tuning signal generation circuit (c) to the discrimination stage 1 (→), it is determined whether it is up scanning tuning or down/scanning tuning. I'J Gramazol frequency divider (b)
The division ratio of is controlled to be switched in the up direction and down direction.

A 1x speed tuning pulse is supplied from the programmable frequency divider Yuni (scanning tuning pulse generation means 01).

Then, scan channel selection operation switch (29U), (29D
) is in operation, the 1x speed tuning pulse, N, continues to supply power to the programmable frequency divider (A). The number of channel selection/J' pulses is 10 or more, that is, the step of the programmable frequency divider (a) (e.g. 5kHz)
When the number reaches 10 steps, the S
Depending on which of the two bands WI and SW is in the receiving state, the frequency of the tuning pulse from the tuning/rust generating means (n') is switched to 10x speed and 20x speed, respectively.
When either the scanning channel selection operation switch (29U) or (29D) is pressed, the speed will be 10 times faster or 2 times faster.
0x speed tuning/2 pulses continue to be supplied to the programmer sol frequency divider.

And the scanning channel selection operation switch (29U).

When the operation (29D) is completed, the frequency division ratio of the programmable frequency divider board is fixed to the state at that time. Also, channel selection 4
Even after removing all 10 Lus, SWI and SW
If it turns out that neither of the two bands is being received,
It becomes a jin where 1x speed selection/yarus occurs.

Although not shown here, when the division ratio of the programmable frequency divider reaches the minimum value or maximum value i, ti±,
Scan tuning can be stopped or can be started from the maximum or minimum value.

Incidentally, the scanning channel selection is performed in the up direction or down direction from a predetermined frequency division ratio inputted to the programmable frequency divider by the last channel 1:0.

According to such a PLL Shinosetsuza receiver, when the band width is wide like shortwave broadcasting and scanning tuning takes time, the scanning tuning range can be changed by simply operating the key of one tuning operation switch. If the band is wide, the tuning scanning speed will automatically increase, and the shortwave S, which has a wider band width than the SWI band, will
In the W2 band, scanning and tuning is performed at a faster speed than in the shortwave SWI band, so scanning and tuning can be performed quickly even in the SW2 band.

Effects of the Invention According to the present invention described above, when the scanning tuning range is wide, the scanning tuning speed is automatically increased by simply operating the key of one scanning tuning operation switch. A PLL synthesizer receiver capable of performing stations quickly can be obtained.

[Brief explanation of drawings]

Fig. 1 is a 7' lock diagram showing one embodiment of the present invention;
The figure is a flowchart for explaining the program of the microcomputer. (20) is a PLL synthesizer for channel selection, (29U),
(29D) is a scanning channel selection operation switch, (1) is a microcomputer, 0]) is a channel selection pulse generation means, and 0 is an argument means.

Claims (1)

[Claims] Tuning based on the PLL synthesizer for tuning and operation of the scanning tuning switch! a tuning pulse generating means for generating a tuning pulse and supplying the tuning pulse to the programmable frequency divider of the PI synthesizer for tuning, and counting the tuning pulse from the tuning pulse generation means; , depending on its counting output υ
and counting means for controlling the frequency of the tuning non-lust of the tuning pulse generation means, and when the count value of the counting means is equal to or higher than a predetermined value, the frequency of the upper C tuning pulse is changed from small to large. A PLL synthesizer side receiver featuring the following features: