JPS5996893A - Control circuit for ac motor - Google Patents

Abstract

PURPOSE:To enable to digitize the current control loop by providing a calculating processor and a timer. CONSTITUTION:A current detector 12a for detecting the actual phase current of an AC motor, an A/D converter 12 for converting the detected actual phase current to a digital value, a processor 3 for calculating the pulse width command of each phase from the calculated current command and the actual phase current of the motor, timers 11a, 11b for outputting the pulse width modulation signal of each phase on the basis of the pulse width command of the processor 3, and an inverter 8 for driving a motor 1 by the pulse width modulation signals of the timers 11a, 11b are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC motor control circuit in which a current control loop for controlling an AC motor is digitized, and in particular, a current detector and a current detector for detecting the actual phase current of the AC motor in the current control loop. The present invention relates to an AC motor control circuit that can simplify the configuration of an analog-to-digital converter.

2. Description of the Related Art In recent years, digital circuits such as microcomputers have made remarkable progress, and various circuits that were made up of analog circuits have been replaced with digital circuits such as microcomputers. This also applies to AC motor control circuits, and the speed control loop is already controlled by a microcomputer.

Fig. 1 is a block diagram of a conventional AC motor control circuit. 3 is an arithmetic circuit that outputs a position pulse TSA in accordance with the rotation, and constitutes a control section of the motor 1, detects the actual speed RA of the AC motor 1 based on the position pulse TSA from the pulse encoder 2, and issues a command. It outputs an amplitude command Id and phase commands Ud and Vd for the U phase and ■ phase according to the difference from the speed CV. The arithmetic circuit 6 connects a processor 60 that performs arithmetic processing, a program memory 61 that stores control programs, a data memory 32 that stores various data, input/output ports 33 and 34, and a counter 65. It consists of an address/data bus 36.

The processor 30 reads the value of the counter 65 that counts the position pulse TEA via the bus 66 according to the control program in the program memory 61, obtains the actual speed RV of the AC motor 1 from the difference with the previously read value, and calculates the actual speed RV of the AC motor 1 according to the command from the outside. An amplitude command Id is calculated based on the difference (speed error ER) from the commanded speed C■ (velocity error ER), and is sent to the input/output port 36 via the bus 36. Further, the processor 50 according to the control program,
Search the angular frequency conversion (RV-ωo) table in the data memory 32 from the above-mentioned actual speed R■ value, and then search the phase and slip conversion (ER-ψ, ER-ωS) table in the data memory using the speed error ER. Search and find the corresponding ω0. ψ.

ωS is read, a U-phase phase command Ud and a V-phase phase command Vd are calculated, and sent to the input/output port 34 via the bus 36.

4a is a digital-to-analog conversion circuit (DA conversion circuit), which converts the digital amplitude command Id into an analog amplitude command Is; 4b and 4c are multiplication type digital-to-analog conversion circuits; V phase phase command [J'
d, Vd to analog, and further analog amplitude command I
s and outputs analog U-phase current command Iu and ■phase current command 1v. 5? "iW phase current generation circuit, analog U phase, ■phase current command ■u, ■v5
6 is the command current Iu for each phase.

An operational amplifier that calculates the difference between Iv, Iw and the actual phase current, and a detector that calculates the difference between each phase command current Iu, Iv, Iw and the actual phase current Iau, Iav, Iaw. 9a, 9b detected and 7'vIav
and an arithmetic circuit that performs addition of Ia and Ia and outputs the W-phase phase current Iaw. 7 is a pulse width modulation circuit, 8
is an inverter controlled by the output signal of a pulse width modulation circuit, and a DC voltage is applied by an external three-phase AC current and a rectifier circuit (diode group and capacitor) K that rectifies this three-phase AC into DC. . As shown in FIG. 2, the pulse width modulation circuit 7 includes a sawtooth wave generation circuit 5TSG that generates a sawtooth signal STS, and comparators COMu and CO.
Mv, C0Mw, Not Kate N0T1~N0T3,
)” Raiha DV, -D'V6, inverter 8
For example, six power transistors Q1 to Q6 and a guiode D
1 to D6. Each comparator COMu, COMv, C0Mw of the pulse width modulation circuit w57 receives a sawtooth wave signal STS and three-phase alternating current signals iu, iv, respectively.

The amplitudes of iw are compared, and when iu, iv, and iw are larger than the STS value, 1'' is output, and when they are smaller, °o'' is output. Therefore, if we focus on iu now, the comparator CO
From Mu, the pulse width modulated current command iu shown in FIG.
c is output. That is, the three-phase current command IUC is pulse width modulated according to the amplitudes of IU, IV, and IW.

ivc and iwc are output. Next, Knot Gate N
OI″I～NO′I″3,)” 5 Iha Ooro DVl
-1) V6 u and t'L Rami flow command iuc, iv
c, iwc into drive signals 5Ql-8Q6, and each power transistor Q1 to Q6 that constitutes the inverter 8
on/off control. 8 is the aforementioned rectifier circuit for DC power supply.

Next, the operation of the configuration shown in FIG. 1 will be described in the case where the AC motor 1 is rotating at the actual speed RV.

The processor 60 of the arithmetic circuit 3 reads the value of the counter 65 that counts the position pulse TSA via the bus 36, and detects the actual speed RV of the AC motor 1. Next, processor 6
0 calculates the amplitude command Id based on the difference between the commanded speed C■ and the detected actual speed C■, searches the angular frequency phase and slip conversion table in the memory 32, and generates the corresponding U-phase phase command Ud.

■Calculate the phase command Vd and send the amplitude command I via the bus 36.
d, to the input/output port circuit 63, U phase, ■ phase phase command U
d and Vd are sent to the input/output port circuit 64. The amplitude command Id of the input/output port 36 is converted into an analog amplitude command Is by the digital/analog conversion circuit 4a, and sent to each multiplication type digital/analog conversion circuit 4b, 4c.

On the other hand, the U-phase and V-phase phase commands Ud and Vd are converted to analog by multiplication type digital-to-analog conversion circuits 4b and 4c, respectively, and multiplied by an analog amplitude command Is, and the analog U-phase and ■phase current commands Iu are multiplied by an analog amplitude command Is. , Iv.

These U-phase and ■-phase current commands Iu and Iv are input to a W-phase current generation circuit 5 to create a W-phase current command Iw, which is input to an operational amplifier 6 together with U-phase and V-phase current commands Iu and Iv.

In the operational amplifier 6, the actual phase current I of the detectors 9a and 9b
au, Iav, and generates the W-phase phase current Iaw, as well as the 6-phase current commands Iu, Iv.

It outputs three-phase AC signals iu, iv, iw, which are the differences between Iw and the actual phase currents Iau, lay, and Iaw of each phase. Then, the difference between the three-phase AC signals iu, iv,
iw is the comparator COMu, CO of the pulse width modulation circuit 7
Applied to Mv, C0Mw. Each comparator COMu,
COMv and C0Mw compare the amplitudes of the sawtooth wave signal STS and three-phase AC signals iu, iv, and iw, respectively, and obtain pulse width modulated three-phase current commands iuc, ivc,
iwc and outputs an inverter drive signal S via NOT gates N0T1 to N0T3 and drivers DV1 to DV6.
Output Q+ to SQ6. These inverter drive signals S
Q1 to SQ6 are respectively inputted to the bases of power transistors Q1 to Q6 constituting the inverter 8', and control on/off of each of the power transistors Q1 to Q6 to supply three-phase current to the AC motor 1. Thereafter, similar control is performed, and the AC motor 1 finally rotates at the commanded speed. In this conventional AC motor control circuit configuration, the current loop requires high-speed response. , 'The DA conversion circuits 48 to 4C1 operational amplifiers 6 and pulse width modulation circuits 7 that make up the current loop had to be constructed with discrete circuits, making it difficult to digitize them.For this reason, the number of parts was large and the circuits were complex. It had the disadvantage of becoming

In particular, detection of real-phase current requires at least two phases Iau and Iav in the case of three-phase AC, and for digitization, an analog-to-digital converter is required for this amount, making it difficult to simplify the configuration of this part. There was also a drawback.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a control circuit for an AC motor in which the current control loop can be digitized and the configuration for detecting the actual phase current can be simplified.

FIG. 4 is a block diagram of an embodiment of the present invention, in which the same components as those shown in FIG. 11a, 11, which are directly connected to the bus control circuit to be described later and perform arithmetic processing according to instructions from the processor 30;
b is a programmable interval timer (hereinafter referred to as a timer) which outputs a pulse width modulation signal in response to a pulse width command signal; 12all''1. is a current detection circuit;
The phase currents Iav and Ia detected by the galvanometers 9a and 9b are shown in detail in Fig. 11.
An isolation amplifier CDC and an isolation amplifier CD that amplify u, respectively.
A pair of analog switches SWU and SWV for guiding the amplified phase currents Iau and Iav, which are the outputs of C, to the analog-to-digital converter 12b in a time-divisional manner; There are 7 lip flops FF, NAND gate NANL)1, NAND2, NAND3 and H/H which make up the switching circuit.
7. It is composed of Kate NOR. To explain the operation with reference to FIG. 12, when the GATE signal applied from the P1 terminal of the arithmetic processor 1o is at a low level (o.)K,
Nantes Gate NAND 1. NAND 2 is opened, and the Q and Q outputs of the flip-flop FF whose initial state is Q output 0'' and Q output 0'' are output as signals VG and UG. That is, since the flip-flop FF inputs the GATE signal as a clock signal, it is inverted at the fall of the GATE signal when it becomes low level (0°'), and the Q output becomes 1" and the Q output becomes °0". From, Nantes Gate NA
"1", "from each of ND1 and NAND2
0” is output.Analog switch SWU, SW
V turns on when the signal is low level (60″), so
The analog switch SW'U is turned on by the low level signal UG, and the phase current Iau is sent to the AD converter 12b. When the GATE signal returns to high level (-1.), the NAND gate NAND1. Since both NAND2 output high level “1”, the analog switch SW
U is off. As a result, the phase current Iau is read into the AD converter 12b only during the low level period of the ()ATE signal, and the AD converter 12b converts the phase current Iau from an analog quantity to a digital value. An analog switch change prohibition period CI is provided so that the phase current is not inputted again during this conversion period. After that, when the control signal applied from the PO terminal of the processor 10 falls (becomes level "'D"), the AD converter 12b sends the control signal to the bus 3.
7, the digitized phase current Iau is transferred to the arithmetic processor 10. Further, the processor 10 stores the phase current Iau in a built-in Langue access memory (RAM). Next, the GATE signal is low level again (・O1')
Then, the flip-flop FF is inverted and its Q, Q
The force where the output is °'o", "i'", Nantes gate NAN
D1. NAND2 output VG, UG are each k”Q”
.

When υ is "1", the analog switch SWv is turned on, and the phase current Iav is sent to the AD converter 12b. When the GAT E signal returns to high level (...1''), both NANDi (Nandi and NANI) 2 become high level and "1" output, so the analog switch S
WV is turned off. As a result, the phase current Iav of the low/' period of the GATE signal is read into the AD converter 12b, and the AD converter 12b converts the phase current Iav from an analog quantity to a digital value.

Thereafter, a change prohibition section CI is provided similarly to the phase current Iau, and the phase current Iav is transferred from the AD converter 12b to the arithmetic processor 10 via the bus 37, and further transferred to the processor 10.
0 stores phase current IaV in built-in R and AM. Next, processor 10 connects terminal P1. Po's GAT E signal 2
, both control signals are set to low level.

A high level output is generated from NAND3 (NAND game), and the output of NOR (NOR game) is changed to low level and inputted to the preset terminal PR of flip-flop FF, and flip-flop FF is put into a preset state.

In this way, the arithmetic processor 10 can obtain the phase currents Iau and Iav when necessary, and also obtain digital values of the two-phase phase currents Iau and Iav using one AD converter.

Returning to FIG. 4, 13 is a bus control circuit, which disconnects or connects the bus 66 on the processor 60 side of the arithmetic circuit 3 and the bus 67 on the arithmetic processor 10 side according to a command. As shown in the figure, gate circuit G1.
It is composed of bidirectional bus transceivers TR1 to TR8 for lines G2 and bus 56.37. The bidirectional path transceivers TR1-TR8 are connected to each line D1-D8 of the bus 36 on the processor 30 side and the arithmetic processor 10.
A pair of transceivers TR, a, TRb are provided to connect the lines DB1 to DBa of the side bus 67, respectively.
have. Each bidirectional path transceiver has a gate circuit G1. Controlled by the output signal of G2, when the gate signal GAT B is at a low level ("0"), either transceiver - TRa or TR is controlled by the level ('l' or "0") of the direction indication signal DIR. It becomes a high-impedance state, and it becomes possible to transfer directions using a transceiver that does not go into a high-impedance state.For example,
If the direction indicating signal I)I is low level ('0''), the output of the gate circuit G1 is high level (1''), '
y'-) Output hello level (0'') of circuit G2,...!
: Since the transceiver-TRbtld enters the high-impedance state, the transceiver-TRa is transmitted from left to right in the figure, i.e. from the processor 30 to the arithmetic processor 1.
On the other hand, if the direction instruction signal DIR is at the no level (.1.), the transfer from the arithmetic processor 1o to the processor 30 becomes possible. or,
When the gate signal GATE is set to high level (i''), the output of any gate circuit ()LG2 is set to low level (-0
), transceiver-TRa, T:ab
The state becomes high impedance, lines D1 to D8 and lines DB1 to DBS of the bus 36 are separated, and the processor 30 uses the bus 36 to transmit signals to and from the program memory 31 etc. connected to the bus 36. The arithmetic processor 10 can be connected to the bus 37 using the bus 37 and exchange signals with the fcAD converter 12b independently.

Returning to FIG. 4, 14a, 14b, 14c are dead zone generation circuits hv, each PWM signal 4uc from timer 11b,
ivc.

This is a circuit that provides a dead zone for the iwc, and the inverter 8
Depending on the accumulation time of the power transistors Qr to Qa (Fig. 2), the power transistors arranged above and below (for example, Ql and Q2) may turn on together and short-circuit during driving, so the base signals of the upper and lower transistors are This is to prevent short circuits by providing an off period. As shown in FIG. 6, this dead band circuit includes an invert circuit lNTl for inverting the PWM signal iuc, and an AND gate AND2 for the PWM signal iuc and the inverted PWM signal iuc.
, ANDl, a first resistor R1 that integrates the inverted PWM signal iuc, and a first capacitor C1, and a second resistor R2 that integrates the PWM signal iuc.
, a second integrator circuit constituted by a second capacitor C2, and a signal inversion type hysteresis circuit HT1 . connected to each integrator circuit. HT2 and invert circuit INT2. IN'
l',! Consists of +. Next, the operation of the configuration in Figure 6 is explained in Figure 7.
To explain based on the waveform diagram of each part in the figure, the PWM signal iuc is sent to the second integrating circuit via the AND gate AN'D2, and the inverted PWM signal iu is inverted by the inverting circuit INT1.
c is input to the first integrating circuit via the AND gate AND1. The values of each capacitor and resistor are determined so that each integrating circuit has a time constant at the rising edge and no time constant at the falling edge. Therefore, at the rise of the PWM signal iuc, the second integration circuit gradually increases the integral amount crab 1.
The first integrating circuit generates an integral output ■1 that falls rapidly, and at the falling edge of the PWM signal iuc, the second integrating circuit generates an integral output ■1 that rapidly falls. An integral output Il which gradually rises is generated. This integral output ■1 + I1 is provided by the hysteresis circuit HT1. Input to HT2. Hysteresis circuit H'l'1. HT2 is the rising slice level SL1 and the falling slice level S.
It is configured differently from L2, and the start-up level SL
I td high<, the falling height level SL2 is set low. Therefore, the hysteresis circuit HT1. HT2 generates outputs I, , I2, respectively, and invert circuits INT2. IN'll is inverted and the inverter drive signals SQl, SQ/! is output as That is, the width of the low level (0'') period of the inverter drive signal SQl is expanded in the shaded area, and the inverter drive signal SQl becomes the inverse two-level inverter drive signal SQl.
This means that the width of the high level (“1”) period of 2 is narrowed by the shaded area. Furthermore, a hysteresis circuit HT1
．． The output of HT2 is the mutual AND gate AND1,
It is input to AND2 as a gate control input, and is in the form of a so-called latch circuit. According to this,
Unnecessary noise components can be removed, and both inverter drive signals SQI and SQ2 are at high level (“1”) due to the noise.
It is possible to prevent this from happening.

Now, in the embodiment configuration of the present invention, the operations of the DA converters 4a, 4b, 4c, W-phase current generation circuit 5, operational amplifier 6, and pulse width modulation circuit 7 of the conventional configuration shown in FIG. 1 are controlled by the operational processor 10. This is done using timers 11a and 11b.

Hereinafter, the operation of the embodiment configuration in FIG. 4 will be explained. As mentioned above, when the processor 3o of the arithmetic circuit 3 calculates the amplitude command Id=i and calculates the U-phase phase command Ud, The amplitude command Id, the U-phase phase command, Ud, and the command speed cV are outputted via the bus control circuit 13 and the bus 37.

The arithmetic processor 10 executes the following arithmetic processing based on an arithmetic program stored in a built-in memory.

■ Calculates V-phase and W-phase phase commands Vd and Wd from the input U-phase phase command U'd (phase command calculation step)
.

This is because the command speed CV is given and the frequency of the sine wave is known, so it is 120° and 240° with respect to the U-phase current command.
° If the delayed values are calculated, ■ phase, W phase current commands Vd, W
d is obtained.

■ Next, the input vibration subcommand Id and the above-mentioned U phase, V[
, W-phase phase commands Ud, Vd, Wd (i-multiply and calculate the current commands Iu, Iv, Iw for each phase (phase current command calculation step). ■ The calculation processor 10 receives the gate signal GATE and the control signal. The bus transceivers of the bus control circuit 13 are output to a high impedance state, the bus 66 and the bus 37 are separated, and the phase currents Iau and I are alternately output from the current detection circuit 12a.
av t-A D is output to the coy-verter 12a, and the real phase current I of the digital value is output from the Vc AD converter 12a.
The data is input to the arithmetic processor 10 via the au, Iav f path 37. The arithmetic processor 10 calculates the real phase current Iau
, Iav, the W-phase real-phase current Iaw is calculated using a well-known calculation equation. (actual phase current step).

■ Current commands Iu, lv, Iw of each phase and actual phase current l
The difference between au, Iav, and Iaw is calculated to obtain three-phase AC signals iu, iv, and iw (three-phase AC calculation step).

■ Proportional integration is performed on the obtained three-phase AC signals iu, iv, and iw (proportional integration step).

(2) Calculate a pulse width command signal from these three-phase AC signals iu, iv, and jw (pulse width command calculation step).

To explain this with reference to FIG. 8, the period of the triangular wave signal TBS shown in FIG. 8(A) is set as <Tt as shown in FIG. 8(B),
The midpoint of the period Tl is the zumbling pulse (Fig. 8 (C)
), a pulse width value T2 corresponding to the value iud K of the AC signal iu at the time of the sampling pulse is calculated. This is obtained by calculating k.(ium-iud).

However, 1utn is the maximum setting value of the AC signal, and k is a constant. Next, the time T3 from the periodic pulse is defined as T3-(Tt
Calculated by Tz )/2. Similarly, V-phase and W-phase AC signals iv.

Also calculate iw. This calculation is performed every cycle of each triangular wave, and a pulse width command signal T2 + T3 is output.

■ Pulse width command signal TU2 for each of these phases. TU3゜TV2. TV3. TW2. TW3 is applied to the processor 60 via the bus 67, the bus control circuit 13, and the bus 36.

This completes the operation of the arithmetic processor 10, and then the processor 40 operates the bus 36. The pulse width command signals TU, ~TW3 are sent to the timer 11a via the bus control circuit 13° bus 67.
, give to b. The timers 'la and 11b include timers for each phase, and after the first timer 11a times the command signal TU3, the second timer iib times the command signal T'U2i.

This will be explained based on the detailed block diagram of the timers 11a and 11b in FIG. 9.Through the bus 37, pulse width command signals TU2, T[Ja, TV2, TVa.

TVV2. Upon receiving Tνv3, the control signal C8K from the processor 30 sends pulse width command signals TUa, TVa, TWs to the timer 11a.
1 l b VC pulse width command signal TU2. TV2.
TWs is set and a strong clock is input, and the timer 11a counts the clocks. In the example of FIG. 10, the timer 11a issues an output oI5 to the gate terminal GT3 of the timer iib when the time TW3 has elapsed, and the timer iib
Start counting TW2 hours. Similarly, each TV3.
TU3 When time is counted, output out2, out
tl f The gate terminal GT2 of the timer 11b generates a signal from GTIK to start the timer 11b (7) TV2, TUz time. Each timer 11b is T.
W2. T.U.

When the TV2W''i count is completed, it is reset and outputs a high level ("1") during the counting period, so that the pulse width modulation signals iuc and ivc are generated for each phase as shown in FIG.

iwc will be output.

These pulse width modulation signals iuc, ivc, and iwc are converted into pulse width modulation signals SQl to SQ6 having dead zones by dead zone generation circuits 14a, 14b, and 14c of each phase, and are applied to each power transistor Ql-Qa of the inverter 8. , a driving current is applied to the AC motor 1. Transfer of the amplitude command Id etc. from the processor 30 to the arithmetic processor 10, calculation of the pulse width command signal of the arithmetic processor 10, transfer of the pulse width command signal from the arithmetic processor 10 to the processor 60, and transfer of the pulse width command signal from the arithmetic processor 10 to the processor 60;
Since the pulse width command signal is transferred to 1a and 11b periodically, the motor 1 is controlled without delay.

Oka, the arithmetic processor mentioned above is a well-known signal processor (for example, Intel's μPD7720), so
Since the pulse width command cannot be transferred to other circuits without going through the processor 60, the pulse width command is given to the timer 11 through the processor 30, but the invention is not limited to this.

As explained above, according to the present invention, there is provided a current detection circuit that detects the actual phase current of an AC motor, an AD converter that converts the detected actual phase current into a digital value, and a calculated current command and the actual phase current of the motor. A processor that calculates pulse width commands for each phase from the current, a timer that outputs H/L/S width modulation signals for each phase based on the pulse width commands of the processor, and a timer that outputs H/L/S width modulation signals of the timers. Since the motor is configured with an inverter that drives the motor, the current loop
This has the effect of making the entire web digital, contributing to simpler configuration and lower prices, and eliminates the need for adjustments. Furthermore, the current detection circuit includes a detector, an analog switch,
Since it is composed of a switching circuit, it is possible to obtain the digital values of the phase currents for two phases with one AD converter, which eliminates the effect of further simplifying the configuration, and also allows the phase current to be obtained when the processor needs it. Therefore, there is also an effect that the execution of the current loop calculation by the processor is not interrupted.

Although the present invention has been described with reference to one embodiment, various modifications can be made within the scope of the spirit of the present invention, and these are not excluded from the scope of the present invention.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional AC motor control circuit, Figure 2 is a block diagram of a conventional AC motor control circuit.
The figure is a main part configuration diagram of the configuration in Figure 1, Figure 6 is an explanatory diagram of the operation of the configuration in Figure 2, Figure 4 is a block diagram of an embodiment of the present invention, and Figure 5
Figure 6 is a block diagram of the bus control circuit in the configuration shown in Figure 4, Figure 6 is a block diagram of the dead band generation circuit in the configuration shown in Figure 4, Figure 7 is a waveform diagram of each part in the configuration shown in Figure 6, and Figure 8 is a diagram of the configuration in Figure 4. An explanatory diagram of pulse width modulation, Fig. 9 is a timer circuit configuration diagram in a four-column configuration, Fig. 10 is a waveform diagram of the configuration in Fig. 9, and Fig. 11 is a diagram of a timer circuit in a four-column configuration.
The current detection circuit configuration diagram in the diagram configuration, Figure 12 is the 11th
The waveform diagram of each part of the diagram configuration is shown. In the figure, 8...Inverter, 1o... Arithmetic processor, 11a, 11b... Timer, 12a... Current detection circuit, 12b... AD converter, SWU, 8WV
...analog switch, 9a, 9b...detector. Patent Applicant Fanuc Co., Ltd. Agent Patent Attorney Sangai Tsuji (2 persons) Figure S Figure 8 q Figure 1 O side

Claims (1)

[Claims] A current detection circuit that detects the actual phase current of an AC motor, an analog/digital exchanger that exchanges the detected actual phase current into a digital value, and a pulse of each phase from the calculated current command and the digitized actual phase current. A processor that calculates a width command, a timer that outputs a pulse width modulation signal of each phase based on the pulse width command of the processor, and an inverter that drives the AC motor using the pulse width modulation signal of the timer, The current detection circuit includes a detector for detecting current of at least two phases, an analog switch provided corresponding to each phase to be detected, and a switching circuit that switches the analog switch according to a control signal of the processor. 1. A control circuit for an AC motor, comprising: sequentially inputting the detected current to an analog-to-digital converter via the analog switch.