JPS5992793A - Pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To eliminate the necessity of an analog circuit and to reduce a ripple of a pulse width modulating circuit by providing a calculator and a timer, and digitally outputting a pulse width modulation signal. CONSTITUTION:When a processor 30 of an arithmetic circuit 3 outputs an amplitude command Id, a V-phase current command Vd and a command speed CV through a bus 36, a bus control circuit 13 and a bus 27 when the processor 30 calculates the amplitude command Id and retrieves the V-phase current command Vd. An arithmetic processor 10 executes the calculation on the basis of a calculating program stored in a memory contained in the processor, and calculates the period (OFF period) from the start of the period as a pulse width command signal and the pulse width time (ON period) of the pulse width signal. This pulse width command is set to a set of timer counters 11a, 11b, thereby generating PWM signals iuc, ivc, iwc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation circuit for pulse width modulating an input signal, and particularly to a pulse width modulation circuit that can output a pulse width modulation signal obtained by triangular wave comparison using a digital circuit. Regarding circuits.

Pulse width modulation circuits are widely used in various fields.

For example, it is also used as part of a control circuit for an AC motor such as an induction motor.

On the other hand, in recent years, with the spread of digital circuits such as microcomputers, various discrete circuits have been replaced by microcomputers. This also applies to AC motor control circuits, and the speed control loop is already controlled by a microcomputer.

Fig. 1 is a block diagram of a conventional AC motor control circuit. 5 is an arithmetic circuit which constitutes the control section of the motor 1, detects the actual speed RV of the AC motor 1 based on the position pulse TSA from the pulse encoder 2, and outputs a position pulse TSA according to the command speed. It outputs the amplitude command 1d1 and phase commands Ud and Vd for the U phase and ■ phase according to the difference from Cv. The arithmetic circuit 6 is
A processor 60 that performs arithmetic processing, a program memory 51 that stores control programs, a data memory 32 that stores various data, and input/output ports 33 and 34.
It consists of a counter 55 and an address/data bus 36 connecting these.

The processor 30 reads the value of the counter 35 that counts the position pulse TSA via the bus 36 in accordance with the control program of the program memory 310, obtains the actual speeds R and V of the AC motor 1 from the difference with the previously read value, and calculates the actual speeds R and V of the AC motor 1 from an external source. Calculate the amplitude command Id based on the difference from the commanded speed Cv,
It is sent to the input/output capotro 3 via the bus 56. Further, according to the control program, the processor 60 searches the data memory 620 phase conversion table from the value of the counter 55 mentioned above, and obtains the corresponding U-phase current command Ud and ■phase current command Vd.
is read out and sent to the input/output capotro 4 via the bus 66. This phase conversion table stores each peak value of a sine wave signal digitally as a numerical value so that U-phase and V-phase sine wave signals are output.

4a is a digital-to-analog conversion circuit (DA conversion circuit), which converts digital amplitude command Id to analog amplitude command I.
s, 'b+4c is a multiplication type digital-to-analog conversion circuit, which converts U-phase, ■-phase current commands Ud,
It converts Vd into analog, further multiplies it by analog amplitude command Is, and outputs analog U-phase current command I u s V-phase current command Iv. 5 is W81'i [current generation circuit, analog U phase, va current command Iu,
6 is an operational amplifier that calculates the difference between the command current Iu, Iv, Iw of each phase and the actual phase current, and 6 is an operational amplifier that calculates the difference between the command current Iu, Iv, Iw of each phase and the actual phase current.
.

An operational amplifier that calculates the difference between Iw and the actual phase current Iau+Iav, Iaw, and an operational circuit that adds Iav and Iau detected by the current transformers 9a and 9b and outputs the W-phase phase current Iaw. configured. 7 is a pulse width modulation circuit; 8 is an inverter controlled by the output signal of the pulse width modulation circuit;
A DC voltage is applied by a rectifier circuit (a group of diodes and a capacitor) that rectifies phase alternating current to direct current. As shown in FIG. 2, the pulse width modulation circuit 7 includes a sawtooth wave generation circuit 5TSG that generates a sawtooth signal STS, a comparator COMU,
COMv, C0Mw, Not Gate No T+ ~
The inverter 8 has six power transistors Q, -Qa and diodes D, . Each comparator COMU, COMv, C0Mw of the pulse width modulation circuit 7 receives a sawtooth wave signal STS and three-phase alternating current signals iu, iv, respectively.

, iw are compared, and when iu, iv, and iw are larger than the value of Sπ, 1'' is output, and when they are smaller, a'' is output. Therefore, if we focus on in now, the comparator CO
The pulse width modulated current command i shown in Fig. 3 is sent from the MU.
uc is output. That is, the three-phase current commands iuc, i which are pulse width modulated according to the amplitude of 1u+IV+IW
vc and iwc are output. Next, NOT gate NOT+ ~NOTs, driver circuit Dv1~Dv6
These current commands iuc+ivc, iwc are used as the drive signal SQ.

~SQa, and controls on/off of each power transistor Q, -Qa constituting the inverter 8. In addition, 8
' is the aforementioned rectifier circuit for DC power supply.

Next, we will briefly explain the operation of the structure shown in FIG. 1 when the AC motor 1 is rotating at the actual speed RV.

The processor 30 of the arithmetic circuit 5 reads the value of the counter 35 that totals the position pulse TSA via the bus 56, and detects the actual speed RV of the AC motor 1. Next, the processor 30 calculates the amplitude command Id based on the difference between the commanded speed CV and the detected actual speed RV, searches the phase conversion table in the memory 32, and searches the phase conversion table in the memory 32 for the corresponding U-phase current commands Ud, V
The phase current command Vd is read out and the amplitude command Id is read out via the bus 36.
is the U-phase and V-phase current command Ud to the input/output boat circuit 66.

Vd is sent to the input/output port circuit 64. Kapo in and out)
The amplitude command Id of 33 is the digital-to-analog conversion circuit 4a.
is converted into an analog amplitude command Is by each multiplication type digital-to-analog conversion circuit 4b.

Sent to 4c. On the other hand, current command Ud for U phase and ■ phase
, Vd are multiplication type digital-to-analog conversion circuits 4b, respectively.
It is converted into an analog signal by r'c, multiplied by an analog amplitude command Is, and converted into analog U-phase and V-phase current commands IU and IV. This U phase, V phase current command I
U and IV are input to a W-phase current generation circuit 5 to generate a W-phase current command IW, which is input to an operational amplifier 6 together with U-phase and V-phase current commands IU and IV. In the operational amplifier 6,
Receives the actual phase currents IaU and IaV of the converters 9aT and 9b, creates the W-phase phase current IaW, and also generates the 6-phase current commands IU, IV, IW and the actual phase currents IaU and IaV of each phase.
Three-phase AC signals iu and iv that are the difference between IaV and IaW
Output +iw. Then, the three-phase AC signals iu, iv, iw, which are the differences, are sent to the comparator C of the pulse width modulation circuit 7.
Applied to OMU, COMv, C0Mw. Each comparator COMU, COMv, C0Mw receives a sawtooth wave signal STS and a three-phase AC signal 111+I, respectively.
Compare the amplitudes of V + iw and output the pulse width modulated three-phase current command 1 uc T IN'e + 1w (!, not game) N0T1"7NOTs and)' 5
IHA DV, ~DV, 'f: Outputs intermediate inverter drive signals SQ+~SQ6. These inverter drive signals SQ+ to SQ are respectively input to the bases of power transistors Q and Q6 constituting the inverter 8,
These power transistors Q, . . . are controlled on/off to supply three-phase current to the AC motor 1. Thereafter, similar control is performed and the AC motor 1 finally rotates at the commanded speed.

In such a conventional AC motor control circuit configuration, the current loop is required to have high-speed response, so the DA conversion circuits 4a to 'Cs operational amplifier 6 and pulse width modulation circuit 7 that constitute the current loop are discrete circuits. It was difficult to digitize it. Therefore, there are disadvantages in that the number of parts is large and the circuit is complicated.

In particular, in pulse width modulation circuits, the current ripple is smaller when using triangular wave comparison than when using sawtooth wave comparison, so triangular wave comparison must be realized digitally, which is considered to be a factor that complicates digitalization. Ta.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a pulse width modulation circuit that can digitally generate a pulse width modulation signal using triangular wave comparison.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a diagram showing the principle of pulse width modulation, comparing triangular wave comparison and sawtooth wave comparison.
S is a sawtooth wave, TBS is a triangular wave, and the periods are the same. iu, iv, iw are AC signals of each phase, iuc, i'u
c is a U-phase pulse width modulation signal (referred to as U-phase part signal), iv
c, i'vc is ■ phase pwM<a, iwc, i'w
c is the W-phase PWM signal, and IaU and I'aU are the actual currents of the U-phase. The one based on triangular wave comparison compares the levels of AC signals iu, iv, iw of each phase and triangular wave TR8, and calculates T
When R3≧jullV11w, high level U phase, ■ phase,
W-phase PVI/M signal iuc, is<c, iwc
is generated. On the other hand, in the method based on sawtooth wave comparison, AC signals iu, iv, iw of each phase and sawtooth wave S
Compare the level with TS, STS≧iu+iv, iw
When , high level U phase, ■ phase, W phase PWM signal 1'u
C,1'V C+i'w c. That is, in the case of sawtooth wave comparison, each PWM signal i'u
Since c + i'v c + i'wc rise at the same timing, the fluctuation range of the current ripple (amplitude fluctuation of the U-phase current IaU) becomes a dog, and becomes a cause of motor vibration. On the other hand, when triangular wave comparison is used, the rise/fall timing of each PWM signal iuc + ivc + iwc is shifted, so the ripple frequency of the current becomes high and the motor does not respond.

In this way, in order to digitally perform pulse width modulation using triangular wave comparison, it is insufficient to simply calculate the pulse width of each phase.

Therefore, in the present invention, the time from the start of the cycle to the pulse width signal (off time) and the pulse width time (on time) of the pulse width signal are calculated as pulse width commands, and these pulses are stored in a set of timer counters. Set the width command and
PWM signal iuc+ivc in the figure.

IWC is generated.

Hereinafter, the present invention will be described in detail regarding an example in which the PM circuit of the present invention is used in a control circuit for an AC motor.

FIG. 5 is a block diagram of an embodiment of the present invention. In the figure, the same components as those shown in FIG. 11a, 11 which are directly connected to the bus 56 of
b is a programmable interval timer (hereinafter referred to as a timer), which outputs a pulse@modulation signal in response to a pulse width command signal, and 12a is a current detection circuit, which detects the phase current detected by the galvanometers 9a + 9b. Isolation amplifier that amplifies Iay and IaU and phase current I a V + I
a Mixing circuit that outputs U in a time-divisional manner, 1
2b is an analog-to-digital conversion circuit (hereinafter referred to as AD converter), which converts the analog phase I av + I au of the mixed circuit of the current detection circuit 12a into a digital value, and sends it to the arithmetic processor 1o. It is something that forces you to do something.

Reference numeral 13 denotes a bus control circuit, which disconnects or connects the bus 36 on the processor 30 side of the arithmetic circuit 3 and the p-bus 37 on the arithmetic processor 10 side according to a command, and its configuration is shown in FIG. Gate circuit G1. G2 and bus 56
．． Bidirectional bus transceiver for 57 lines - TR1
~TR8. Bidirectional path transceivers TR1 to TR8H are provided to connect each line D1 to D8 of the bus 66 on the processor 50 side and each line DB1 to DB8 of the bus 67 on the arithmetic processor 10 side, each pair of transceivers TRa, It has TRb and has 7. Each bidirectional path transceiver has a gate circuit Q1.
Controlled by the output signal of Q2, when the gate signal GATE is low level 10''), either transceiver is
When TRa and TRb are in a high impedance state, directional transfer is possible using a transceiver that does not go into a high impedance state. For example, if the direction indication signal DIR is at a low level ("0"), the output of the gate circuit G1 is at a high level (11"), the output of the gate circuit G2 is at a low level (0"), and the transceiver TR
b is in a high impedance state, from left to right in the figure by transceiver TRa, i.e. processor 30.
The data can be transferred from the data to the arithmetic processor 10. on the other hand,
If the direction instruction signal DIR is at a high level (1''), transfer from the arithmetic processor 10 to the processor 30 is possible in the same way.
1''), the output of either gate circuit G?
a and TRb are both in a high impedance state, lines D1 to D8 and lines DBI to DB8 of the bus 36 are separated, and the processor 30 uses the bus 66 to transfer signals to and from the program memory 31 etc. connected to the bus 36. By using the bus 37, the arithmetic processor 10 can independently exchange signals with the AD converter 12b connected to the bus 37.

Returning to FIG. 5, 14a, 14b, and 14c are dead zone generating circuits and each PM'M signal iuc from the timer 11b.

This is a circuit that provides a dead zone for ivc and iwc, and depending on the accumulation time of power transistors Q, ~, etc. of inverter 8 (Fig. 2), power transistors placed above and below (for example, Q and q) are both turned on during driving. Therefore, a period is set in which the base signals of the upper and lower transistors are turned on to prevent short circuits.

As shown in FIG. 7, this dead band circuit is connected to the PWM signal iuc.
and an invert circuit lNTl that inverts the PWM signal tu.
AND gate of c and anti-EPWM signal iuc
2, AND 1, a first integrating circuit consisting of a first resistor R8 that integrates the inverted PWM signal iuc, and a first capacitor C1, and a second integrating circuit that integrates the PWM signal iuc.
a second integrator circuit composed of a resistor island, a second capacitor C2, and a signal inversion type hysteresis circuit HT1 connected to each integrator circuit. HT2 and invert circuit INT2
, consists of INT3. Next, the operation of the configuration in FIG. 7 will be explained based on the waveform diagram of each part in FIG. 8. PWM signal iu
c is an inverted ptvM signal 1 which has been inverted by an invert circuit lNTl and is sent to the second integrating circuit via AND2.
uc is input to the first integrating circuit via the analogue-1-AND1. The values of each capacitor and resistor are determined so that each integrating circuit has a time constant at the rising edge and no time constant at the falling edge. Therefore, at the rising edge of the PWM signal iuc, the second integrating circuit gradually rises and integrates the output ■,
However, an integral ratio crab that rapidly falls is generated from the first integrating circuit, and when the PWM signal IUC falls, an integral ratio crab that rapidly falls from the second integrating circuit is generated, but the first integral ratio The circuit generates an integral ratio crab that gradually rises. These integral outputs I, , I, are connected to hysteresis circuits HTI and HT2.
is input. Hysteresis circuit HT1. HT2 is the rising slice level SL1 and the falling slice level S.
The rising level SL is configured to be different from L2.
1 is set high, and falling level SL2 is set low.

Therefore, the hysteresis circuits H'I''1 and HT2 generate outputs I, , I, respectively, and the invert circuit INT
2, it is inverted at INTO, and the inverter drive signal S
It is output as Q, , SQ. That is, the width of the period in which the inverter drive signal SQI is at a low level (0") is widened in the shaded area, and conversely, the width of the period in which the inverter drive signal SQz is at a high level (1") is narrowed only in the shaded area. It turns out.

Furthermore, a hysteresis circuit HT1. The four outputs of HT2 are input to each other's gates AND1 and AND2 as gate control inputs, and are in the form of a so-called latch circuit. According to this, unnecessary noise components can be removed, and it is possible to prevent both the inverter drive signals SQ+ and SQt from becoming the same level (1'') due to noise.

Now, in the embodiment configuration of the present invention, the operations of the conventional configuration ODA converter 4B, 41), 4C% W-phase current generation circuit 5, operational amplifier 6, and pulse width modulation circuit 7 shown in FIG. 11a and 11b.

The operation of the embodiment configuration in FIG. 5 will be described below. As mentioned above, when the processor 60 of the arithmetic circuit 3 calculates the amplitude command Id and searches for the U-phase current command Ud, the processor 60 of the arithmetic circuit 3
0, this amplitude command Id is transmitted via the bus 36, the bus control circuit 13, and the bus 37.

Outputs U-phase current command Ud and command speed CV. The arithmetic processor 10 executes the following arithmetic processing based on an arithmetic program stored in a built-in memory.

■ Calculate ■ phase and W phase current commands Vd and Wd from the input U-phase current command Ud (current command calculation step).

This is because the command speed Cv is given and the frequency of the sine wave is known, so it is 120° and 240° with respect to the U-phase current command.
° If the delayed values are calculated, ■ phase, W phase current commands Vd, W
d is obtained.

■ Next, the input amplitude command Id and the above-mentioned U-phase, ■-phase, and W-phase current commands ua, va, and wa are combined.
L, calculate current commands IU, Iv, and Iw for each phase (phase current command calculation step).

■ The arithmetic processor 10 outputs the gate signal GATE, sets each bus transceiver of the bus control circuit 16 to high impedance, separates the bus 66 and the bus 37, and alternately outputs the actual phase current I from the current detection circuit 12a. a U +
Output I a V to AD controller (-12a,
Furthermore, the digital values of actual phase currents 1aU and IaV are sent from the AD converter 12a to the arithmetic processor 1 via the bus 57.
Enter 0. The calculation processor 10 calculates the actual phase current IaW of the W phase from the actual phase currents IBu and IaV using a well-known calculation equation.

(Actual phase current calculation step).

■ Current commands IU, IV, IW for each phase and actual phase current I
The difference between aU, Iav, and IaW is calculated to obtain three-phase AC signals iu, iv, and iw (three-phase AC calculation step).

■ Proportionally integrate the obtained three-phase AC signal iu + iv + iw (proportional integral step knob).

(2) Calculate a Nockles width command signal from this three-phase AC signal in+IV+IW (Nockles width command calculation step).

To explain this with reference to FIG. 9, the period of the triangular wave signal TR8 shown in FIG. 9(A) is expressed as shown in FIG.
7. Bus sampling the midpoint of period T1 (Figure 9 (
C)), the current transformation signal i at the time of the sampling pulse
(bus width value T, (on time) corresponding to the value iud of u
Calculate. This is obtained by calculating k·(ium=iud).

However, ium is the maximum setting value of the AC signal, and k is a constant. Next, the time from the periodic pulse (off time) Ts is calculated by Ts" (T+ T2)/2. Similarly, the V-phase and W-phase AC signals iv, iw
Also calculate. This calculation is performed every cycle of each triangular wave, and a pulse width command signal T2+Ts is output.

■ Pulse width command signals for each of these phases TU2, TU,
.

TVt + T V3 , TW2 , TWlf is provided to the processor 30 via the Hass 5'7, Hass control 1 channel 16, and bus 36.

This completes the operation of the arithmetic processor 10. Next, the processor 30 operates the bus 66, the bus control port k<13, and the bus 67.
Through the pulse width command signal TU, the ~IT demon is sent to the timer 11.
a, l). The timers 11a and 11b include timers for each phase, and after the first timer 11a measures the command signal T Us, the second timer 11b clocks the command signal '1'' Ut.
time. This will be explained based on the detailed block diagram of the timers 11a and 11b in FIG. 10.Through the bus 37, the pulse width command signals TU2, TU! , TV.

TVs, TW2. T%, pulse width command signals TU3, TVs, TWs are sent to the timer 11a by the control signal C8 from the processor 30.
1), pulse width command signals TUt, TV2, and T% are set, a clock (not shown) is input, and timer 1 is set.
1a counts the clock. In the example of FIG. 11, the timer 11a is TW, and when the time elapses, the output out3 is sent to the timer 1.
1b, and starts counting the T% time of the timer 11b. Similarly, when each TVs and TU3 time is counted, the output out2+out1 is sent to the gate terminal GT2. of the timer 11b. Issued to GT1, timer 11
b TV2. Start counting TU2 hours. The timers 11b are TW2, TU2, and TV?, respectively. It is reset when counting is completed and remains at high level ('1") during the counting period.
Since it emits an output of , each phase as shown in Fig. 11.

For, the pulse width modulated signal 1 u C* I V C+
1 we will be output.

This pulse width modulation signal iuc+ivc+iwc is converted into pulse width modulation signals SQ+ to SQa having dead zones by dead zone generation circuits 14a, 14b, and 14c of each phase, and is applied to each power transistor Q, -Qa of the inverter 8,
A drive current is applied to the AC motor 1. Transfer of the amplitude command Id etc. from the processor 30 to the arithmetic processor 10, calculation of the pulse width command signal of the arithmetic processor 10, transfer of the pulse width command signal from the arithmetic processor 10 to the processor 60, from the processor 30 to the timer 11fi, 1
Since the pulse width command signal is transferred to 1b periodically, the motor 1 is controlled without delay.

In addition, since the above-mentioned arithmetic processor is a well-known signal processor (for example, μPD7720 manufactured by Intel Corporation),
Since the pulse width command cannot be directly transferred to other circuits via the processor 60, the pulse width command is given to the timer 11 via the processor 30, but the invention is not limited thereto.

As explained above, according to the present invention, in a pulse width modulation circuit that compares a modulated signal with a reference triangular wave signal and outputs a pulse width modulated signal, the reference triangular wave signal corresponding to the level of the modulated signal is an arithmetic circuit that calculates an on time and an off time from the start of the reference triangular wave signal from the cycle of the reference triangular wave signal and the on time; A first timer circuit for counting, the on-time is set, and the first
and a second timer circuit for counting the set on time of the hind leg of the timer circuit,
Since pulse width modulation signals can be output digitally, in addition to the effect of not requiring separate analog circuits, pulse width modulation by triangular wave comparison can be performed digitally, which is always effective in ripple reduction. play.

Furthermore, since it is composed of one arithmetic circuit and a timer,
The configuration is simple, no adjustment is required, and it also has the effect of greatly contributing to cost reduction.

Although the present invention has been described with reference to one embodiment, various modifications can be made within the scope of the present invention, and these are not excluded from the scope of the present invention.

[Brief explanation of the drawing]

Figure 1 is a Glock diagram of a conventional AC motor control circuit;
The figure is a block diagram of the main parts of the configuration shown in Figure 1, Figure 3 is an explanatory diagram of the operation of the configuration shown in Figure 2, Figure 4 is an explanatory diagram of the pulse width modulation method, and Figure 5 is a plot diagram of an embodiment of the present invention. , FIG. 6 is a block diagram of the bus control circuit in the configuration shown in FIG. 5, FIG. 7 is a block diagram of the dead zone generation circuit in the configuration shown in FIG. 5, FIG. 8 is a waveform diagram of each part in the configuration shown in FIG. Figure configuration pulse width modulation explanatory diagram, 1st
0 shows a timer circuit diagram in the configuration shown in FIG. 5, and FIG. 11 shows a waveform diagram in the configuration shown in FIG. 10. In the figure, 6... Arithmetic circuit, 30... Main processor, 5
6.57... Bus, 10... Arithmetic processor, 1i
a. 11b...Timer, 8...Inverter, 1...AC motor. Patent applicant Fanuc Co., Ltd. agent Patent attorney Tsuji Sanagai, 2 persons ---J 2nd 3rd page / Figure 3 JCJPi plate book■'' 且■且脹■ Bu 4, $6, page 8, Figure 8 90 (β) 70th 1st/@

Claims (2)

[Claims] (1) In a pulse width modulation circuit that compares a modulated signal with a reference triangular wave signal and outputs a pulse width modulated signal, calculates the on time of the reference triangular wave signal corresponding to the level of the modulated signal, and an arithmetic circuit that calculates an off time from the start of the reference triangular wave signal from the period of the triangular wave signal and the on time; a first counter circuit in which the off time is set and counts the set off time; The on-time is set, and the first counter circuit counts the off-time; the second counter circuit counts the set on-time;
A pulse width modulation circuit comprising a second counter circuit, and outputting a pulse width modulation signal from the second counter circuit. (2) The calculation circuit includes a main processor that calculates an amplitude command based on the difference between the command speed and the actual speed of the motor, and outputs the amplitude command and a current command for at least one phase; Claim (1) is characterized in that it is comprised of an arithmetic processor that calculates a pulse width control command for each phase from an amplitude command, a current command, and an actual phase current of the motor. pulse width modulation circuit.