JPH01321866A - Control of pwm waveform of inverter - Google Patents

Control of pwm waveform of inverter

Info

Publication number
JPH01321866A
JPH01321866A JP63154215A JP15421588A JPH01321866A JP H01321866 A JPH01321866 A JP H01321866A JP 63154215 A JP63154215 A JP 63154215A JP 15421588 A JP15421588 A JP 15421588A JP H01321866 A JPH01321866 A JP H01321866A
Authority
JP
Japan
Prior art keywords
timer
pwm
output
data
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63154215A
Other languages
Japanese (ja)
Other versions
JP2719927B2 (en
Inventor
Yukio Kawa
川 由紀夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kasuga Denki Inc
Original Assignee
Kasuga Denki Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kasuga Denki Inc filed Critical Kasuga Denki Inc
Priority to JP63154215A priority Critical patent/JP2719927B2/en
Priority to KR1019890000059A priority patent/KR930003234B1/en
Publication of JPH01321866A publication Critical patent/JPH01321866A/en
Application granted granted Critical
Publication of JP2719927B2 publication Critical patent/JP2719927B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/06Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
    • H02P7/18Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
    • H02P7/24Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
    • H02P7/28Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
    • H02P7/285Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only
    • H02P7/29Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only using pulse modulation
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To shorten a processing time by employing a resistor, used for timer interruption, as an auxiliary resistor. CONSTITUTION:An inverter 17 is constituted of a DC power source 10 and semiconductor elements 11-16 to drive an induction motor 18. The inverter 17 is provided with an one-tip CPU 19 consisting of an A/D converter 22, a plurality of timers 23, a ROM 24, a RAM 25, a microprocessor 26 and the like. A PWM control waveform is outputted by timer interruption utilizing the one-tip CPU 19 and when a resistor, used for the timer interruption of PWM waveform output control, is used as an auxiliary resistor and a main resistor is switched to the auxiliary resistor upon interruption to effect the transfer of data for a timer processing the pulse width of the PWM output and the setting of starting, the auxiliary resistor is employed without passing the data through the RAM 25 thereby transferring the data and setting the starting. As a result, a processing time may be shortened and PWM control reduced in errors may be effected.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は3相誘導電動機の可変速に使用するインバータ
のPWM波形制御方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a PWM waveform control method for an inverter used for variable speed of a three-phase induction motor.

従来技術 従来実施されているインバータのP’WM波形制御方法
として第1図に示す構成のものがあるが。
PRIOR ART As a conventional method for controlling the P'WM waveform of an inverter, there is a structure shown in FIG.

この構成は出力周波数設定人力lをA/D変換器2に入
力し、A/D変換器2の出力をマイクロプロセッサ3に
印加し、ROM4に記憶されたpwV波形パターンのデ
ータを引出し、マイクロプロセッサ3で演算処理して得
たpwu波形のデータをプログラムタイマ6に印加し、
プログラムタイマ6より3相’)”H+ v+ * ”
r * Ut g ”t l ”! ’) PW”出力
を作成しインバータのトランジスタTr、〜Tr6のペ
ースに印加するものであるが、この場合のPWM波形は
#c2図に示すように一定間隔ごとに同時にHレベルか
らLレベルに下がる為、インバータの+アームのトラン
ジスタTr、 、 TI”s 、 Trs又は−アーム
のトランジスタTrt、 TI4. Trgが同時にO
N又はOFFすることになり、出力電流の振動や高調波
成分の問題があった。これを解決する為になり、このP
WM波形を作成する方法として第4図の■のようにT7
2周期ごとにパルス1輻a、  bをマイクロプロセッ
サ3で演算しプログラムタイマ6で出力して■の波形を
得て、フリップフロップ8で第4図■のようにPWM波
形を合成するものがある。この方法は、一定周期Tの1
/2間隔ごとに異なる幅のパルスを出力し7.フリップ
フロップ8で合成するために、フリップフロップ回路が
外部に必要とし制御回路のプリント基板が太き(なりコ
スト高になる欠点があった。
This configuration inputs the output frequency setting manually to the A/D converter 2, applies the output of the A/D converter 2 to the microprocessor 3, draws out the data of the pwV waveform pattern stored in the ROM 4, and then Apply the pwu waveform data obtained through the arithmetic processing in step 3 to the program timer 6,
3 phase from program timer 6')"H+ v+ *"
r * Ut g “t l ”! ') PW'' output is created and applied to the pace of transistors Tr and Tr6 of the inverter, but the PWM waveform in this case drops from H level to L level at regular intervals as shown in figure #c2. Therefore, the transistors Tr, , TI"s, Trs in the + arm of the inverter or the transistors Trt, TI4. in the - arm of the inverter. Trg is O at the same time
This resulted in problems with output current vibration and harmonic components. In order to solve this, this P
To create a WM waveform, use T7 as shown in ■ in Figure 4.
There is one that calculates pulses a and b every two cycles using a microprocessor 3, outputs them using a program timer 6 to obtain the waveform shown in ■, and synthesizes the PWM waveform using a flip-flop 8 as shown in Figure 4 ■. . This method uses 1 of a constant period T.
7. Output pulses with different widths every /2 intervals. Since the synthesis is performed by the flip-flop 8, the flip-flop circuit is required externally, and the printed circuit board for the control circuit is thick (which has the disadvantage of increasing costs).

発明が解決しようとする問題点 従来実施されている第1図に示す構成のPWM出力を改
善するものとして、メモリー回路、タイマtea、 入
出力インタフェース、マイクロプロセッサ等よりなる1
チツプcpσを使用し、てPWM出力制御するものがあ
り、この方法は3相の為の2wM出力を合成する外部回
路を必要とすることなく回路構成が簡略化される利点を
有している。
Problems to be Solved by the Invention In order to improve the PWM output of the conventionally implemented configuration shown in FIG.
There is a method that uses a chip cpσ to control the PWM output, and this method has the advantage that the circuit configuration is simplified without requiring an external circuit for synthesizing the 2wM output for three phases.

1チツプcpσによるPWM出力制御の一例として株式
会社東芝製のタイプTMP900840を使用した場合
のプログラムを説明すると、TMP900840は8ビ
ツトの割込タイマと8ビツトのPWM出力を備えている
ので割込タイマ(タイマ0)により一定間隔の割込処理
を行ないpvrM出力モード(タイマ1)を制御するこ
とで第5図に示す周期Tごと)c T / zを中心と
するPWM波形を出力できる。第5図の■パターンはA
、 m B。
As an example of PWM output control using 1-chip cpσ, we will explain a program using the type TMP900840 manufactured by Toshiba Corporation.Since the TMP900840 is equipped with an 8-bit interrupt timer and an 8-bit PWM output, the interrupt timer ( By performing interrupt processing at regular intervals using timer 0) and controlling the pvrM output mode (timer 1), it is possible to output a PWM waveform centered at c T / z every cycle T shown in FIG. 5. ■Pattern in Figure 5 is A
, mB.

の場合、■パターンは^〈馬の場合の波形でありこの時
の浄振周波数るIQ M H!?とし、′@込同周期ル 大−204PsとすればPWM出力の1周期に4回の割
込をかければ、PWM出力の周期T−204X4:81
6戸Sとなりキャリア周波数が約1225HMのPWM
出力が得られる。
In the case of , the ■ pattern is the waveform for a horse, and the pure vibration frequency at this time is IQ M H! ? If '@include same period le large - 204Ps, then if 4 interrupts are applied to one period of PWM output, the period of PWM output is T - 204X4:81
PWM with 6 units S and carrier frequency of approximately 1225HM
I get the output.

PWM出力を得るタイマ割込処理プログラムを第6図の
70チヤートに基づいて説明すると、ステップ@でレジ
スタ退避を行ない、ステップ[相]でタイマ1を停止し
、ステップOでP?rM周期のデータをタイマ1のレジ
スタにセットし、ステップ[相]でタイマ1をスタート
するか又は停止の状態のままとする。割込処理カウンタ
が第5図に示すTllTl + Tt * T3のカウ
ントの繰返しとすると、ステップ■で現在の割込カウン
タがT、かど5か判定し。
The timer interrupt processing program for obtaining a PWM output will be explained based on chart 70 in FIG. 6. In step @, the register is saved, in step [phase], timer 1 is stopped, and in step O, P? Data of rM period is set in the register of timer 1, and timer 1 is started at step [phase] or left in the stopped state. Assuming that the interrupt processing counter repeatedly counts TllTl+Tt*T3 as shown in FIG. 5, it is determined in step (2) whether the current interrupt counter is T, or 5.

T6の場合にステップOでT、 %/ ’r3のPWM
出カバターンを一括計算してRAM上に格納し、ステッ
プ[相]でPWM出カバターンに基づきPWM出力デー
タをRAM上にセットする。この時PfM出力は8ビツ
トで256種類のパターンとすると、256X4=10
24バイトのテーブルを用意しテーブルの番地とパター
ンを対比させる事で簡単に処理可能となる。第7図のテ
ーブル例に示す如く。
PWM of T, %/'r3 in step O for T6
The output cover turns are collectively calculated and stored on the RAM, and in step [phase] PWM output data is set on the RAM based on the PWM output cover turns. At this time, assuming that the PfM output is 8 bits and has 256 types of patterns, 256 x 4 = 10
This can be easily processed by preparing a 24-byte table and comparing the table address with the pattern. As shown in the example table of FIG.

第5図の@パターンの場合A番地からA+3番地K O
+ AI −BI + Bl t ’のデータを設定し
たテーブルを用意し、■パターンの場合はB番地から〜
In the case of the @ pattern in Figure 5, from address A to address A+3 K O
+ AI - BI + Blt Prepare a table in which data is set, and if it is a pattern, start from address B ~
.

八L o、o、131−−4投屋したテーブルを用意し、ステ
ップ[相]でステップ[相]で退避したレジスタを復帰
し割込処理を終了する。
8L o, o, 131--4 A table is prepared, and in step [phase], the register saved in step [phase] is restored, and the interrupt processing is ended.

次に割込タイマ(タイマO)により割込処理が受けつけ
られてからTMP90(!840の処理プログラムを第
8図の70−チャートで説明するとステップ■でプログ
ラムカウンタPOとレジスタム?の内容をスタックヘセ
ープし9割込許可フラグIFFを「0」にリセットする
事で割込禁止モードとする。ステップ[相]で受けつけ
られた割込の処理スタート番地Vをプログラムカウンタ
へ移しステップOで割込逃理プログラムヘジャングし。
Next, after the interrupt processing is accepted by the interrupt timer (timer O), the processing program of TMP90 (!840 is explained using the 70-chart in FIG. The interrupt processing start address V of the interrupt accepted in step [phase] is moved to the program counter, and the interrupt is escaped in step O. Jump to the physical program.

ステップOでステップ[相]の処理後復帰する。In step O, the process returns after processing step [phase].

割込が受は付けられてから1割込処理プログラムカウン
タするまでの処理時間は4pS必要となる。第9図は第
5図■のPWM波形を出力する場合のタイマによる割込
処理と第6図の処理プログラムとの関係を示し、タイマ
割込後から4pB後のaで割込処理プログラムにジャン
プし、第6図のレジスタ退避■及びタイマ停止■、タイ
マ1データ転送■の処理を行ない、b点でタイマl起動
設定Oを行なうと、この時のデータAによる時間後0点
で出力はLレベルからHレベルへ移ル。
The processing time from when an interrupt is accepted until one interrupt processing program counter is counted is 4 pS. Figure 9 shows the relationship between the interrupt processing by the timer and the processing program in Figure 6 when outputting the PWM waveform in Figure 5 ■, and jumps to the interrupt processing program at a, 4 pB after the timer interrupt. Then, when register saving ■, timer stop ■, and timer 1 data transfer ■ in Fig. 6 are performed, and timer l start setting O is performed at point b, the output becomes L at point 0 after a time period based on data A at this time. Move from level to H level.

第1O図はデータムが大きい場合で、この時間がal−
すより長い場合、タイマ出力がLレベルからHレベルに
移る前にa嘗においてタイマは停止させる為Lレベルの
ままでEレベルに移らない事になり波形が乱れることに
なる。従ってデータAはa、 −bの時間が最大となり
、a、−aすなわちT11−T、が第5図におけるt時
間より短かくなり、PIFM波形に誤差を生じる事とな
り、これは割込処理ヘジャンプしてタイマを停止してか
ら次にタイマを起動させるまでの処理時間の存在のため
に発生する問題点であった。
Figure 1O shows the case where the datum is large, and this time is al-
If the timer output is longer than the timer output, the timer is stopped at step A before the timer output moves from the L level to the H level, so it remains at the L level and does not shift to the E level, resulting in a waveform disturbance. Therefore, for data A, the time of a, -b becomes maximum, and a, -a, that is, T11-T, becomes shorter than the time t in Fig. 5, causing an error in the PIFM waveform, which causes a jump to the interrupt processing. This problem arises because of the processing time from when the timer is stopped to when the timer is started again.

問題点を解決するための手段 本発明は上記の内容Kfiみて、PWM出力のタイマ割
込処理において、タイマ割込に使用するレジスタを補助
レジスタとすることで、タイマ割込処理持主レジスタを
退避させることなく、主レジスタと補助レジスタを切替
えることで割込処理をさせて処理時間の短縮をすること
ができる。
Means for Solving the Problems In view of the above content Kfi, the present invention saves the timer interrupt processing owner register by making the register used for the timer interrupt an auxiliary register in the timer interrupt processing of PWM output. By switching between the main register and the auxiliary register, interrupt processing can be performed and the processing time can be shortened.

実施例 以下第11図〜第13 iQ Ic基づいて説明すると
、 10は直流電源、 11〜16は6個の半導体素子
でインバータ■を構成し、 1Bは交流誘導電動機、■
はインバータFをPWM制御する見チップOPσ、20
は出力周波数設定入力で入力インターフェース21′に
印加し、22はA/D変換器、23は複数のタイマで割
込、PWMパルス幅の設定を行ない、24はプロダラム
やパルス幅データを格納するROM、25はデータを記
憶するRAM、26はデータの′OJ1.算処理を子処
理イクロプロセッサ、27は出カイ/ターフエースでイ
ンバータ■へP W M IIJ御出力出力加する。
10 is a DC power supply, 11 to 16 are six semiconductor elements that constitute an inverter ■, 1B is an AC induction motor, ■
is the chip OPσ, 20, which controls the inverter F by PWM.
is an output frequency setting input and is applied to the input interface 21', 22 is an A/D converter, 23 is a plurality of timers for interrupts and PWM pulse width settings, and 24 is a ROM that stores program data and pulse width data. , 25 is a RAM for storing data, and 26 is a data 'OJ1. The arithmetic processing is performed by the child processing microprocessor, and 27 outputs the PWM IIJ output to the inverter (2) through the output/Turf Ace.

次に本発明によるPWM出力を得る処理方法について@
12図のフローチャートに基づいて説明すると、ステッ
プ■で主レジスタと補助レジスタを切替、以後のレジス
タは補助レジスタを使用する。ステップOでタイマlを
停止し、ステップ・でBルジスタに設定しであるタイマ
1のデータをタイマ1のレジスタに転送し、ステップ・
でCルジスタに設定しであるタイマ1の起動又は停止の
設定にもとづきタイマ1の状態を設定する。ステ7プ[
相]、Oは第6図のステップ■、■と同様の処理であり
、ステップ@で計算したデータを補助レジスタB′に転
送し、タイマの起動又は停止の条件をCルジスタに転送
し、ステップOで主レジスタと補助レジスタを切替1割
込処理を終える。この慄屯 にした場合、tR13番に示すよ5に割込処理ヘジャン
プしてからタイマ1のデータを設定するまでの時間は、
第6図の従来の処理では11.2pElかかり本発明の
第12図の処理では3.6 p 8となり7.6PS短
縮される事になる。タイマ1のデータの理論的最大値は
204pF3とした場合、7.6/204X 100 
== 3.7%分のデータを理論値に近づける事ができ
、それだけ誤差の少ないPWM波形を出力させる事が可
能となる。
Next, regarding the processing method for obtaining PWM output according to the present invention @
Explaining based on the flowchart in FIG. 12, in step (2), the main register and the auxiliary register are switched, and the auxiliary register is used for the subsequent registers. At step O, timer l is stopped, and at step O, the data of timer 1 is set in the B register and transferred to the timer 1 register.
The state of timer 1 is set based on the start or stop setting of timer 1 set in the C register. Step 7 [
phase], O is the same process as steps ■ and ■ in Fig. 6, in which the data calculated in step @ is transferred to the auxiliary register B', the condition for starting or stopping the timer is transferred to the C register, and step At O, the main register and auxiliary register are switched and the 1st interrupt processing is finished. In this case, the time from jumping to interrupt processing at 5 to setting timer 1 data is as shown in tR13.
The conventional process shown in FIG. 6 requires 11.2 pEl, and the process shown in FIG. 12 according to the present invention requires 3.6 pEl, which is a reduction of 7.6 PS. The theoretical maximum value of timer 1 data is 204pF3, then 7.6/204X 100
== 3.7% of the data can be brought closer to the theoretical value, and a PWM waveform with fewer errors can be output.

発明の効果 本発明は、lチップCPUを利用してタイマ割込により
PWM制御波形を出力するものにおいてPWMデータ処
理に使用するレジスタを有効利用してデータの処理時間
の短縮を計ったもので次のような効果がある。
Effects of the Invention The present invention aims to shorten the data processing time by effectively utilizing the registers used for PWM data processing in a device that uses a 1-chip CPU to output a PWM control waveform by a timer interrupt. There is an effect like.

(1)  PWM波形出力制御の割込タイマに使用する
レジスタを補助レジスタとし1割込時主レジスタを補助
レジスタに切替え、PWM出力のパルス幅を処理するタ
イマへのデータ転送、起動設定を行なう場合、データを
一時記憶するRAMを通さないで補助レジスタを使用し
てデータ転送、起動設定するようにしたので、処理時間
が短縮され誤差の少ないPWM制御ができる。
(1) When setting the register used for the interrupt timer for PWM waveform output control as an auxiliary register, switching the main register to the auxiliary register at the time of one interrupt, and performing data transfer and activation settings for the timer that processes the pulse width of the PWM output. Since data transfer and startup settings are performed using an auxiliary register without passing the data through the RAM that temporarily stores it, processing time is shortened and PWM control with fewer errors is possible.

(2) 一定間隔の割込処理を行ない9割込処理時間の
偶数倍の周期で、その周期の中心がパルスの中心となる
PWM波形を外部に回路を必要とすることなく、1チツ
プOP[Tの機能のみで作成する事ができ9回路構成が
簡単で安価なインバータを構成できる。
(2) Performs interrupt processing at regular intervals, and generates a PWM waveform in which the center of the cycle is the center of the pulse with a cycle that is an even multiple of the 9-interrupt processing time without the need for an external circuit. It is possible to construct an inverter with a simple and inexpensive 9-circuit configuration since it can be created using only the functions of T.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明に係るインバータのPWM波形制御方法の一
実施例を示すもので、第1図〜第10図は従来例を示し
第1図はPWM制御部のブロック構成v、iz図はプロ
グラムタイマ6より出力されるP W M 阪形図、第
3図は7リツプフロクブ8より出力されるPWM波形図
、第4図は第1図の制゛御回路で出力されるPWM波形
の説明図、第5図は1チツプCPUによるPWM出力波
形図、第6図は1チツプcpaによるPWM出力制御の
フロ−チャート図、第7図はpw−t−出力パターンの
テーブル例、第8図は割込処理のフローチャート図第9
図、第10図は問題点を説明するためのPfM波形図、
第11図〜第13図は本発明のPWM波形制御方法を示
す図で第11図はインバータのPWM出力波形制御を示
すブロック構成図、第12図はpwM出力のフローチャ
ート図、第13図は割込処理ヘジャンプしてからタイマ
1のデータを設定するまでの処理時間を比較する図であ
る。 ■はインバータ、19は1チップCPU、21は入力イ
ンターフェース、23はタイマ、26はマイクロプロセ
ッサ、27は出力インターフェースである。
The figure shows an embodiment of the PWM waveform control method for an inverter according to the present invention, and FIGS. 1 to 10 show a conventional example. 6 is a PWM waveform diagram output from the control circuit 8, FIG. Figure 5 is a PWM output waveform diagram by a 1-chip CPU, Figure 6 is a flow chart of PWM output control by a 1-chip CPU, Figure 7 is a table example of a pw-t-output pattern, and Figure 8 is an interrupt processing diagram. Flow chart diagram No. 9
Figure 10 is a PfM waveform diagram for explaining the problem,
11 to 13 are diagrams showing the PWM waveform control method of the present invention. FIG. 11 is a block diagram showing the PWM output waveform control of the inverter, FIG. 12 is a flowchart of the PWM output, and FIG. 12 is a diagram comparing the processing time from jumping to the input processing until setting the data of timer 1. FIG. 2 is an inverter, 19 is a 1-chip CPU, 21 is an input interface, 23 is a timer, 26 is a microprocessor, and 27 is an output interface.

Claims (1)

【特許請求の範囲】[Claims] 1、メモリー回路とタイマ機能と入出力インターフェー
スとマイクロプロセッサよりなる1チップCPUと、該
1チップCPUのタイマ機能の1つで一定間隔にPWM
出力波形の出力モードを設定する割込処理手段と、該割
込処理に使用するレジスタを全て補助レジスタとし主レ
ジスタから割込時に切替える手段と、前記割込タイマの
周期の4倍の周期でこの周期の中心がPWM波形パルス
幅の中心となるようにしたインバータのPWM波形制御
方法。
1. A 1-chip CPU consisting of a memory circuit, a timer function, an input/output interface, and a microprocessor, and one of the timer functions of the 1-chip CPU performs PWM at regular intervals.
an interrupt processing means for setting the output mode of the output waveform; a means for making all the registers used for the interrupt processing auxiliary registers and switching from the main register at the time of an interrupt; A PWM waveform control method for an inverter in which the center of the cycle is the center of the PWM waveform pulse width.
JP63154215A 1988-06-22 1988-06-22 Inverter PWM waveform control method Expired - Lifetime JP2719927B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63154215A JP2719927B2 (en) 1988-06-22 1988-06-22 Inverter PWM waveform control method
KR1019890000059A KR930003234B1 (en) 1988-06-22 1989-01-06 Inverter pwm control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63154215A JP2719927B2 (en) 1988-06-22 1988-06-22 Inverter PWM waveform control method

Publications (2)

Publication Number Publication Date
JPH01321866A true JPH01321866A (en) 1989-12-27
JP2719927B2 JP2719927B2 (en) 1998-02-25

Family

ID=15579358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63154215A Expired - Lifetime JP2719927B2 (en) 1988-06-22 1988-06-22 Inverter PWM waveform control method

Country Status (2)

Country Link
JP (1) JP2719927B2 (en)
KR (1) KR930003234B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100645555B1 (en) * 2004-12-03 2006-11-15 현대자동차주식회사 Motor controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217863A (en) * 1986-03-18 1987-09-25 Mitsubishi Electric Corp Waveform generation circuit for inverter
JPS62290357A (en) * 1986-06-10 1987-12-17 Hitachi Ltd Control device of power converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217863A (en) * 1986-03-18 1987-09-25 Mitsubishi Electric Corp Waveform generation circuit for inverter
JPS62290357A (en) * 1986-06-10 1987-12-17 Hitachi Ltd Control device of power converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100645555B1 (en) * 2004-12-03 2006-11-15 현대자동차주식회사 Motor controller

Also Published As

Publication number Publication date
KR930003234B1 (en) 1993-04-23
KR900001107A (en) 1990-01-31
JP2719927B2 (en) 1998-02-25

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