JPS6281492U

JPS6281492U -

Info

Publication number: JPS6281492U
Application number: JP1985172359U
Authority: JP
Priority date: 1985-11-11
Filing date: 1985-11-11
Publication date: 1987-05-25

Description

[Brief explanation of the drawing]

第１図乃至第３図は本考案の第１の実施例を示
すもので、第１図は断線検出手段の回路図、第２
図は第１図中の各部波形図、第３図は全体の電気
的構成を概略的に示すブロツク図である。また、
第４図及び第５図は本考案の第２の実施例を示す
もので、第４図は断線検出手段を示すブロツク図
、第５図は第４図中のマイクロコンピユータのプ
ログラムを示すフローチヤートである。さらに第
６図は従来例を示す第３図相当図である。図中、２は加工テーブル、３は速度設定回路、
４は速度指令値演算回路、５はモータ（負荷）、
６は速度検出手段、７はインバータ装置、８，２
０は断線検出手段、１１，２３は第１のコンパレ
ータ回路（第１の検出手段）、１５，２４は第２
のコンパレータ回路（第２の検出手段）、１６は
論理回路（信号発生手段）、１７はＡＮＤ回路、
１８はインバータ、２１はマイクロコンピユータ
（信号発生手段）を示す。 1 to 3 show a first embodiment of the present invention, and FIG. 1 is a circuit diagram of a disconnection detection means, and FIG.
The figure is a waveform diagram of each part in FIG. 1, and FIG. 3 is a block diagram schematically showing the entire electrical configuration. Also,
4 and 5 show a second embodiment of the present invention, FIG. 4 is a block diagram showing the disconnection detection means, and FIG. 5 is a flowchart showing the program of the microcomputer in FIG. 4. It is. Further, FIG. 6 is a diagram corresponding to FIG. 3 showing a conventional example. In the figure, 2 is a processing table, 3 is a speed setting circuit,
4 is a speed command value calculation circuit, 5 is a motor (load),
6 is a speed detection means, 7 is an inverter device, 8, 2
0 is a disconnection detection means, 11 and 23 are first comparator circuits (first detection means), and 15 and 24 are second
a comparator circuit (second detection means), 16 a logic circuit (signal generation means), 17 an AND circuit,
18 is an inverter, and 21 is a microcomputer (signal generating means).

Claims

[Scope of utility model registration request]

A speed detecting means that generates a feedback signal according to the speed of the load, and the speed of the load is feedback-controlled to a value corresponding to the speed setting signal based on the speed setting signal and the deviation of the feedback signal. a first detection means for outputting a first logic value signal when the level of the speed setting signal exceeds a predetermined value; and a second logic value signal for outputting the second logic value signal when the level of the feedback signal becomes zero. and a signal generating means that generates an abnormal signal when the first logical value signal and the second logical value signal are output simultaneously. Control device.