JPH0139119Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a phase control device for a PWM inverter, and more particularly to a phase control device for a PWM inverter that calculates and controls pulse width using a microcomputer or the like to obtain, for example, a sine wave output.

Conventionally, as shown in FIG. 1, there is a control system that uses a microcomputer (hereinafter abbreviated as microcomputer) to control the pulse width of an inverter.
In the figure, 20 is an AC power supply, 22 is a forward conversion section consisting of a rectifying element that converts AC from this AC power supply 20 into DC, 24 is a capacitor connected in parallel to the output side of this forward conversion section 22, and 26 is a The inverse conversion section (inverter section) consists of switching elements according to the number of phases, and in the embodiment, three-phase transistor bridges 26 _U , 26 _X , 26 _V , 26 _Y , 26 _W , 2
It is composed of 6 _Z. In addition, a microcomputer is used as the phase control circuit of this inverter section 26, and as is well known, a central processing unit (MPU) 1
ROM7, RAM8,
An I/O interface 9 is connected. Further, a timer 2 is provided to apply an interrupt _IP to the MPU 1, and a counter 5 whose counter sets pulse width calculation data in synchronization with the signal 4 to generate a required gate pulse; A gate pulse output control circuit 6 connected to the output stage is connected via a bus line 10. This gate pulse output control circuit 6 performs polarity control and amplification of gate pulses in synchronization with the control signal 3 for polarity control and transmission control.

In the above configuration, since it is necessary to generate gate pulses in real-time processing, an interrupt I _P is sent from the external timer 2 to the MPU 1 every cycle T, and the arithmetic processing for generating gate pulses is performed by interrupt processing. In the conventional system, a program as shown in the flowchart of FIG. 2 is activated by this interrupt _IP . As can be understood from this flow, the counter trigger signal is processed in the first step 11, then the pulse width is calculated in step 12, the calculated data is set in the counter 5 in step 13, and the gate pulse is output. The transistors 26 _U to 26 _Z of the inverter section 26 are driven through the control circuit 6 to perform phase control.

In the case of such a conventional method, timer 2 issues an interrupt request to MPU 1 exactly every cycle T, but
It takes 0 to 1 instruction execution time to accept this request and start the process shown in FIG. 2. That is, interrupt processing can be performed after the instruction is executed. Therefore, as shown in FIG. 3, once the trigger signal is issued at point a, it takes an additional time o or t from point b until the next interrupt request is issued and the trigger signal is issued. t is 1
Since it is the instruction execution time, in the example
The variation ranges from about 1.35 to 5.42 μS. When controlling something with a fast response like the gate current of an inverter, this variation becomes a relatively large disturbance that enters the control system, and the control accuracy is affected. This may cause a drop in performance or malfunction.

This invention was developed in view of the above points.When controlling the inverter by calculating the pulse width using a microcomputer, etc., it is affected by variations in instruction execution time based on interrupt requests from an external timer. The purpose of the present invention is to provide a phase control device for a PWM inverter that reduces disturbances in the control system by eliminating the noise and optimizes the division of control between hardware and software.

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts, and the explanation thereof will be omitted.

In one embodiment of the present invention, the trigger signal 16 of the counter 5 is synchronized with the interrupt I _P of the timer 2 so that the trigger signal 16 of the counter 5 is
The control signal 15 of the gate pulse output control circuit 6 is also provided in synchronization with this trigger signal 16. Because of this configuration, as shown in the flowchart of FIG. 5, the step of processing the trigger signal of the counter 5 is omitted, and the pulse width calculation and pulse width calculation of step 12 are directly performed.
This calculation data is set in the counter in step 13. Therefore, Fig. 6 a, b,
As shown in c, the interrupt signal from timer 2 and the trigger signal of the counter completely match, and the interrupt processing shown in FIG. 5 described above is performed after one instruction execution time t.

One embodiment of the present invention is as described above, and by directly obtaining the trigger signal of the counter 5 from the timer 2 by hardware, it is possible to maintain an accurate and stable switching cycle, so that disturbances in the control system are reduced. reduce Furthermore, when using a microcomputer to control the phase of a PWM inverter, it is possible to optimize the division of control between hardware and software, compared to conventional methods where control is heavily distributed to software.

As described above, the present invention is capable of eliminating the influence of variations in instruction execution time based on interrupt requests from an external timer when controlling the phase of an inverter by calculating the pulse width using a microcomputer or the like. This has the effect of reducing disturbances in the control system and optimizing the division of control between hardware and software.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the general circuit configuration of a conventional PWM inverter phase control device, Figure 2 is the flow of a program started by an interrupt from the timer in Figure 1, and Figure 3 is a block diagram showing the schematic circuit configuration of a conventional PWM inverter phase control device. A waveform diagram illustrating the relationship between the trigger signal and instruction execution time in the figure, Figure 4 is related to the present invention.
A block diagram showing the circuit configuration of the main part of the phase control device of the PWM inverter. Figure 5 is the flow of the program started by an interrupt from the timer in Figure 4. FIG. 3 is a waveform diagram showing each signal of a timer interrupt and a counter trigger in the figure, and interrupt processing. 1...MPU, 2...Timer, 5...Counter,
6... Gate pulse output control circuit, 7...
ROM, 8... RAM, 9... I/O interface, 10... Bus, 15... Control signal of gate pulse output control circuit, 16... Counter trigger signal, 26... Inverter section, 26 _U , 26 _V ,2
6 _W , 26 _X , 26 _Y , 26 _Z ...Switching elements.

Claims (1)

[Claims for Utility Model Registration] (1) In response to an interrupt from an external timer, the memory calculation processing section calculates the required pulse width, sets this calculation data in a counter, and sends a gate pulse to the switching element that constitutes the inverter. A phase control device for a PWM inverter that performs phase control by supplying a PWM inverter, characterized in that the trigger signal of the counter is directly provided from the timer in synchronization with an interrupt of the timer.
Inverter phase control device. (2) The utility model according to claim 1, characterized in that the counter trigger signal directly applied from the timer also serves as a control signal for a gate pulse output control circuit connected to the output stage of the counter. PWM inverter phase control device.