JPS5995708A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JPS5995708A
JPS5995708A JP20572682A JP20572682A JPS5995708A JP S5995708 A JPS5995708 A JP S5995708A JP 20572682 A JP20572682 A JP 20572682A JP 20572682 A JP20572682 A JP 20572682A JP S5995708 A JPS5995708 A JP S5995708A
Authority
JP
Japan
Prior art keywords
terminal
voltage
output
differential amplifier
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20572682A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Sugawara
光俊 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP20572682A priority Critical patent/JPS5995708A/en
Publication of JPS5995708A publication Critical patent/JPS5995708A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain selectively a positive and a negative output with a few lead terminals by switching one of different polarities of the 1st and the 2nd differential amplifiers selectively by means of an output of a voltage comparator and leading the result to an output terminal. CONSTITUTION:When a voltage of a reference voltage source 9 is 5V and a voltage at a terminal 3 is 0-5V, a switch 10 connects a positive output of a differential amplifier 2 to a terminal 4 by an output of a voltage comparator 8. When a voltage at the terminal 3 is 5-10V, the output of the comparator 8 is inverted and a negative output of the differential amplifier 6 is outputted to the terminal 4 via the switch 10. Since a voltage of 5-10V is applied to the terminal 3, the voltage is corrected into the original range (0-5V) by a level shift circuit 7 and the result is impressed to the amplifier 6. Thus, the polarity is switched selectively by a voltage at the terminal 3, and the ratio of performance to cost of an IC is improved.

Description

【発明の詳細な説明】 本発明は出力極性を切換可能な増幅回路に関する。[Detailed description of the invention] The present invention relates to an amplifier circuit capable of switching output polarity.

従来、差動増幅器は集積回路装置(以下ICという)に
おいて広く用いられているが、差動増幅器の正負の両極
性入力端子及び正負の両極性出力端子をすべて端子とし
てIC外へ引き出すことはICの端子数をいたずらにふ
やし、価格/性能比を悪くするため通常必要な端子のみ
IC外へ引き出すようにしている。
Conventionally, differential amplifiers have been widely used in integrated circuit devices (hereinafter referred to as ICs). In order to unnecessarily increase the number of terminals and worsen the price/performance ratio, only the normally necessary terminals are brought out of the IC.

本発明はより少ない引き出し端子数で、差動増幅器の正
負極性の出力を選択的に引き出し可能たらしめる増幅回
路を提供することを目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide an amplifier circuit that can selectively draw out positive and negative polarity outputs of a differential amplifier with a smaller number of lead-out terminals.

本発明の増幅回路は、第1及び第2の差動増幅器と、少
くとも1ケのレベルシフト回路と、電圧比較回路と入力
及び出力端子を有し、前記ン、l及び第2の差動増幅器
の各々の第1極性入力端子と各々の第2極性入力端をそ
れぞれ一対となし、少くともその一方は前記レベルシフ
ト回路を介して接続するとともに他方の対を前記入力端
子に接続すると共に、該入力端子の入力端子を前記電圧
比較回路に印加せしめ、該電圧比較器の出力にて前記第
1及び第20差動増幅器の相異なる極性の−方を選択的
に切換えて前記出力端子に導出したことを特徴とする。
The amplifier circuit of the present invention has first and second differential amplifiers, at least one level shift circuit, a voltage comparator circuit, and input and output terminals, A first polarity input terminal of each amplifier and a second polarity input terminal of each amplifier are formed as a pair, at least one of which is connected via the level shift circuit, and the other pair is connected to the input terminal, An input terminal of the input terminal is applied to the voltage comparator circuit, and an output of the voltage comparator selectively switches the negative polarity of the first and twentieth differential amplifiers and outputs the negative polarity to the output terminal. It is characterized by what it did.

次に図面を参照して詳細に説明する。第1図は従来の差
動増幅器を含むICの一例であり、1は集積回路装置、
2け差動増幅器、3は負入力端子で基準電圧入力として
用いられており、41は正出力端子、42け負出力端子
である。また差動増幅器2の正極性入力はICI内の他
の回路(図示せず)へ接続されている。このような例は
負帰還増幅器や電圧比較器を含むIC等に広く用いられ
ている。
Next, a detailed explanation will be given with reference to the drawings. FIG. 1 shows an example of an IC including a conventional differential amplifier, in which 1 is an integrated circuit device;
In the 2-digit differential amplifier, 3 is a negative input terminal used as a reference voltage input, 41 is a positive output terminal, and 42 is a negative output terminal. Further, the positive polarity input of the differential amplifier 2 is connected to other circuits (not shown) within the ICI. Such examples are widely used in ICs including negative feedback amplifiers and voltage comparators.

第2図は本発明の実施例を示すブロック図である。第1
図と同じものには同一の符号を付しである。この増幅回
路は、従来の差動増幅器2のほかに差動増幅器6を有し
、前者を正極性出力用、後者を負極性出力用として用い
、電子スイッチ10を介して出力端子4よシ所望の極性
の出力を得るものである。ここで、極性切換信号として
入力端子3の電圧を用いる。より具体的にのべると、た
とえば基準電圧源9の電圧を5vとすれば、端子3の電
圧が0〜5Vのとき、′電圧比較器8の出力により、電
子スイッチ10は差動増幅器2の正極性出力を端子4へ
接続している。また端子3の電圧が5〜IOVのときは
電圧比較器8の出力が反転し、差動増幅器6の負極性出
力が電子スイッチ10を介して端子4へ出力される。こ
のとき端子3は前述のとお95〜10Vの電圧がかかっ
ているため、それをレベルシフト回路7でもとの範囲(
0〜sV)に補正し差動増幅器6に印加している。この
ようにすれば端子3の電圧で選択的に極性を切換えるこ
とができ、かつ第1図の端子5に相当する端子を必要と
しないため、1.Cにおいて性能M曲格比を向上するこ
とができる。
FIG. 2 is a block diagram showing an embodiment of the present invention. 1st
Components that are the same as those in the figure are given the same reference numerals. This amplifier circuit has a differential amplifier 6 in addition to the conventional differential amplifier 2, and uses the former for positive polarity output and the latter for negative polarity output, and connects the output terminal 4 to the desired output via an electronic switch 10. The polarity of the output is obtained. Here, the voltage at the input terminal 3 is used as the polarity switching signal. To be more specific, for example, if the voltage of the reference voltage source 9 is 5V, when the voltage of the terminal 3 is 0 to 5V, the output of the voltage comparator 8 causes the electronic switch 10 to connect to the positive terminal of the differential amplifier 2. The output is connected to terminal 4. Further, when the voltage at the terminal 3 is 5 to IOV, the output of the voltage comparator 8 is inverted, and the negative polarity output of the differential amplifier 6 is outputted to the terminal 4 via the electronic switch 10. At this time, since the voltage of 95 to 10V is applied to the terminal 3 as mentioned above, the level shift circuit 7 transfers it to the original range (
0 to sV) and applied to the differential amplifier 6. In this way, the polarity can be selectively switched by the voltage of the terminal 3, and there is no need for a terminal corresponding to the terminal 5 in FIG. 1, so 1. The performance M curvature ratio can be improved in C.

またレベルシフト回路7は必ずしも第2図の位置に入っ
ていなくてもよく、たとえば差動増幅器6の正極性入力
側に入れることもでき、この場合は差動増幅器6の正負
両極性入力とも差動増幅器2のそれよp5V高くなって
いる。これまでIC内の他の回路より差動増幅器2,6
の正極性入力に印加される電圧をほぼO〜5vの範囲内
にあるものとして考えていたが、もし、そうでないなら
必要に応じてレベルシフトを行うとよい。
Furthermore, the level shift circuit 7 does not necessarily have to be placed in the position shown in FIG. p5V is higher than that of dynamic amplifier 2. Until now, differential amplifiers 2 and 6 were used more than other circuits in the IC.
It was assumed that the voltage applied to the positive input of the circuit was approximately within the range of 0 to 5V, but if this is not the case, level shifting may be performed as necessary.

第3図は第2図の実施例を具体的に示す回路図である。FIG. 3 is a circuit diagram specifically showing the embodiment of FIG. 2.

Q1〜Q9けトランジスタを、R1−R6は抵抗を示す
。Q6のペースにはIC内の他の回路(図示せず)より
の信号(その変化範囲は2〜6v以内とする。)が印加
され、Q6と几5からなるエミッタホロアを介して、第
2図の差動増幅器2の正極性入力に相当するQ5のペー
スと、第2図の差動増幅器6の正極性入力に相当するQ
3のペースに印加されている。一方、端子3はエミッタ
ホロアを構成するQlを介して、第2図の差動増幅器2
の負極性入力に相当するQ4のペースに接続されるとと
もに、ツェナーダイオードZD(この場合5.3vであ
る)とR3からなるレベルシフト回路(第2図の7に相
当)を介して、第2図の差動増幅器6の負極性入力に相
当するQ2のペースへ接続されており、さらに几1.R
2によって分圧され第2図の比較器8に相当するQl(
これとQ8で比較器を構成)のペースに接続されておシ
、その基準電圧(第2図の9に相当)はVref(この
場合1.5 V )としてQ8のペースに与えられる。
Q1 to Q9 represent transistors, and R1 to R6 represent resistors. A signal from another circuit (not shown) in the IC (its variation range is within 2 to 6 V) is applied to the pace of Q6, and the signal as shown in FIG. The pace of Q5 corresponds to the positive polarity input of the differential amplifier 2 in FIG.
It is applied to the pace of 3. On the other hand, the terminal 3 is connected to the differential amplifier 2 of FIG.
is connected to the pace of Q4, which corresponds to the negative polarity input of It is connected to the pace of Q2, which corresponds to the negative input of the differential amplifier 6 in the figure, and is further connected to the base of Q2. R
2 and corresponds to the comparator 8 in FIG.
This and Q8 constitute a comparator), and its reference voltage (corresponding to 9 in FIG. 2) is applied to the pace of Q8 as Vref (1.5 V in this case).

なおIは定電流源である。また端子3の電圧が6vのと
きにQlのペース電圧が1.5vになるように几1.R
2の比は決定されている。上記接続により端子3が6v
以下のときはQ8がONし、Q4.Q5  からなる差
動増幅器が動作し、逆に6v以上(7)ときHQ7がO
NL、Q2.Q3 からなる差動増幅器が動作するとい
う電子スイッチの機能をあわせて有している。第2図の
差動増幅器2の負極性出力に相当するQ5のコレクタと
第2図の差動増幅器6の正極性出力に相当するQ2のコ
レクタは負荷R4に接続され、さらにQ9と几6からな
る反転増幅器で増幅され、端子4よ多出力が得られる。
Note that I is a constant current source. Also, when the voltage of terminal 3 is 6V, the pace voltage of Ql is set to 1.5V. R
The ratio of 2 has been determined. With the above connection, terminal 3 is 6V
In the following cases, Q8 is ON and Q4. The differential amplifier consisting of Q5 operates, and conversely, when 6V or more (7), HQ7 becomes O.
NL, Q2. It also has the function of an electronic switch that operates a differential amplifier consisting of Q3. The collector of Q5, which corresponds to the negative polarity output of the differential amplifier 2 in FIG. 2, and the collector of Q2, which corresponds to the positive polarity output of the differential amplifier 6 in FIG. The signal is amplified by an inverting amplifier, and multiple outputs can be obtained from terminal 4.

したがって端子3の電圧が2〜6vのとぎは正極性増幅
器として動作し、6v以上のときは負極性増幅器として
動作する。
Therefore, when the voltage at the terminal 3 is 2 to 6 V, it operates as a positive polarity amplifier, and when it is 6 V or more, it operates as a negative polarity amplifier.

本発明は実施例に限ることなく、たとえばレベルシフト
を抵抗分割で行ってもよく、また他の形式のレベルシフ
ト回路を用いることもできる。電子スイッチとしては差
動増幅器のエミッタをプルアップしてOF Fにする方
式や他の方式を用いることもできる。
The present invention is not limited to the embodiments; for example, level shifting may be performed by resistor division, or other types of level shifting circuits may be used. As the electronic switch, a method of pulling up the emitter of a differential amplifier to turn it off, or another method may be used.

本発明によれば性能/価格比を向上できる。According to the present invention, the performance/price ratio can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の差動増幅器を示すブロック図、第2図、
第3図は本発明の実施例を示すブロック図9回路図であ
る。 1・・・・・・IC12・・・・・・差動増幅器、3・
・・・・・入力端子、4,5・・・・・・出力端子、6
・・・・・・差動増幅器、7・・・・・・レベルシフト
回路、8・・・・・・電圧比較器、9・・・・・・基準
電圧源、10・・・・・・電子スイッチ、Q1〜Q9・
・・・・・トランジスタ、■1〜R6・・・・・・抵抗
、■・・・・・・定電流源、vref・・・・・・基準
電圧、zD・・・・・・ツェナーダイオード。
Figure 1 is a block diagram showing a conventional differential amplifier; Figure 2 is a block diagram showing a conventional differential amplifier;
FIG. 3 is a block diagram 9 circuit diagram showing an embodiment of the present invention. 1...IC12...Differential amplifier, 3.
...Input terminal, 4, 5...Output terminal, 6
... Differential amplifier, 7 ... Level shift circuit, 8 ... Voltage comparator, 9 ... Reference voltage source, 10 ... Electronic switch, Q1~Q9・
...Transistor, ■1 to R6...Resistor, ■...Constant current source, vref...Reference voltage, zD...Zener diode.

Claims (1)

【特許請求の範囲】[Claims] 第1及び第2の差動増幅器の各々の第1極性入力端子と
各々の第2極性入力端をそれぞれ一対となし、少くとも
その一方はレベルシフト回路を介して接続するとともに
他、方の対をti入力端子に記第1及び第2の差動増幅
器の相異なる極性の出力の一方を選択的に切換えて出力
端子に導出したことを特徴とする増幅回路。
The first polarity input terminal of each of the first and second differential amplifiers and the second polarity input terminal of each of the first and second differential amplifiers are formed as a pair, and at least one of them is connected via a level shift circuit, and the other An amplifier circuit characterized in that one of outputs of different polarities of the first and second differential amplifiers is selectively switched and outputted to the output terminal.
JP20572682A 1982-11-24 1982-11-24 Amplifier circuit Pending JPS5995708A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20572682A JPS5995708A (en) 1982-11-24 1982-11-24 Amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20572682A JPS5995708A (en) 1982-11-24 1982-11-24 Amplifier circuit

Publications (1)

Publication Number Publication Date
JPS5995708A true JPS5995708A (en) 1984-06-01

Family

ID=16511656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20572682A Pending JPS5995708A (en) 1982-11-24 1982-11-24 Amplifier circuit

Country Status (1)

Country Link
JP (1) JPS5995708A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215104A (en) * 1983-05-20 1984-12-05 Matsushita Electric Ind Co Ltd Low frequency amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215104A (en) * 1983-05-20 1984-12-05 Matsushita Electric Ind Co Ltd Low frequency amplifier
JPH0475682B2 (en) * 1983-05-20 1992-12-01 Matsushita Electric Ind Co Ltd

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