JPS5994417U - buffer circuit - Google Patents

buffer circuit

Info

Publication number
JPS5994417U
JPS5994417U JP19022682U JP19022682U JPS5994417U JP S5994417 U JPS5994417 U JP S5994417U JP 19022682 U JP19022682 U JP 19022682U JP 19022682 U JP19022682 U JP 19022682U JP S5994417 U JPS5994417 U JP S5994417U
Authority
JP
Japan
Prior art keywords
pair
emitter
complementary
input
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19022682U
Other languages
Japanese (ja)
Inventor
文男 石川
田中　國信
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP19022682U priority Critical patent/JPS5994417U/en
Publication of JPS5994417U publication Critical patent/JPS5994417U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のバッファ回路を示す接続図、第２図は本
考案によるバッファ回路の一実施例を示゛す接続図、第
３図はそのカーレントミラー回路の変形例を示す接続図
である。 １１・・・入力端子、１４・・・出力端子、１５．１６
・・・カーレントミラー回路、１７・・・サンプルホー
ルド用−コンデンサ、ＴＩＡ、Ｔ２Ａ・・・入力側トラ
ンジスタ、Ｔ２Ａ、Ｔ２Ｂ・・・バイアス用トランジス
タ、Ｔ３Ａ、Ｔ３Ｂ・・・出力側トランジスタ、Ｔ４Ａ
。 Ｔ４Ｂ・・・駆動用トランジスタ。Fig. 1 is a connection diagram showing a conventional buffer circuit, Fig. 2 is a connection diagram showing an embodiment of the buffer circuit according to the present invention, and Fig. 3 is a connection diagram showing a modification of the current mirror circuit. be. 11...Input terminal, 14...Output terminal, 15.16
...Current mirror circuit, 17...Sample and hold capacitor, TIA, T2A...Input side transistor, T2A, T2B...Bias transistor, T3A, T3B...Output side transistor, T4A
. T4B...Drive transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベースを入力端子に共通に接続したエミッタホロワ構成
のコンプリメンタリな一対の入力側トランジスタと、入
力側トランジスタのエミッタをベースに接続しかつエミ
ッタを出力端子に共通に接続シたエミッタホロワ構成の
コンプリメンタリな一対の出力側トランジスタと、ベー
スを直結したコンプリメンタリな一対のダミー用トラン
ジスタと、上記ダミー用トランジスタを流れる電流と同
一の電流をそれぞれ上記入力側トランジスタのエミッタ
に直流バイアスとして流す一対のカーレントミラー回路
とを具えることを特徴とするバッファ回路。A pair of complementary input transistors with an emitter-follower configuration in which the bases are commonly connected to the input terminal, and a complementary pair of outputs in the emitter-follower configuration in which the emitters of the input transistors are connected to the base and the emitters are commonly connected to the output terminal. A pair of complementary dummy transistors whose bases are directly connected to the side transistor, and a pair of current mirror circuits that respectively flow the same current as the current flowing through the dummy transistor to the emitter of the input side transistor as a DC bias. A buffer circuit characterized by the ability to
JP19022682U 1982-12-16 1982-12-16 buffer circuit Pending JPS5994417U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19022682U JPS5994417U (en) 1982-12-16 1982-12-16 buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19022682U JPS5994417U (en) 1982-12-16 1982-12-16 buffer circuit

Publications (1)

Publication Number Publication Date
JPS5994417U true JPS5994417U (en) 1984-06-27

Family

ID=30409928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19022682U Pending JPS5994417U (en) 1982-12-16 1982-12-16 buffer circuit

Country Status (1)

Country Link
JP (1) JPS5994417U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02186706A (en) * 1988-11-10 1990-07-23 Burr Brown Corp Bias voltage generating circuit and method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02186706A (en) * 1988-11-10 1990-07-23 Burr Brown Corp Bias voltage generating circuit and method thereof

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