JPS5992536A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS5992536A
JPS5992536A JP57203011A JP20301182A JPS5992536A JP S5992536 A JPS5992536 A JP S5992536A JP 57203011 A JP57203011 A JP 57203011A JP 20301182 A JP20301182 A JP 20301182A JP S5992536 A JPS5992536 A JP S5992536A
Authority
JP
Japan
Prior art keywords
semiconductor
resin
semiconductor substrate
substrate
polishing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57203011A
Other languages
English (en)
Inventor
Nobuhaya Takebashi
信逸 竹橋
Fujiko Kinoshita
木下　富士子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57203011A priority Critical patent/JPS5992536A/ja
Publication of JPS5992536A publication Critical patent/JPS5992536A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/151—Die mounting substrate
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法、特に半導体ペレットの
ダイポンド方法に関するものである。
従来例の構成とその問題点 パワー用半導体デバイスは、素子動作時の発熱カ一般の
デバイスより太きいため、この熱ひずみにより半導体ペ
レット、収納容器のクラックが発生して信頼性、特性に
大きな影響を及ぼしていた。
その対策として、ウェル裏面研磨により半導体３１−ジ ペレッ）ｋ薄くした状態で収納容器に実装する方法が用
いられていた。第１図（Ａ）、　（Ｂ）にその従来方法
を示す。同図において１はコレット、２は半導体ペレッ
ト、３は半導体ペレットのクラック（割れ）である。す
なわち、第１図（Ａ）に示すごとく、従来の半導体ペレ
ット２の厚さは通常６０〜１００μｍであるため、コレ
ット１での保持が困難であった。したがって、前記半導
体ペレット２を収納容器に実装（以下ダイボンドと称す
）する際コレット１による十分な保持が出来ず、第１図
中）に示すごとく、半導体ペレット２にクラック３を発
生させることがあった。又、半導体ペレット２の裏面と
収納容器４とが完全に密着しないため、半導体ペレット
２から発生した熱は収納容器４から外部に発散出来ず、
十分な放熱効果が得られない。
発明の目的 本発明はこのような従来の問題に鑑み、ウェル裏面研磨
により薄くした半導体ペレット全損傷することなくダイ
ボンドし、又半導体ペレット裏面と収納容器とを十分に
密着固定し、良好な放熱効果を得ること全目的とする。
発明の構成 本発明は、半導体基板表面に樹脂塗布する工程、前記半
導体基板裏面研磨する工程、前記半導体基板を半導体ペ
レットに分割する工程、前記半導体ペレットヲ収納容器
に載置時又は載置後、樹脂除去する工程を有することに
より、裏面研磨によって薄くなった半導体ペレットヲ収
納容器に確実な接着固定を行い、さらに素子動作時発生
する熱を効率よく外部に発散させ、高性能、高出力な半
導体装置を製造可能とするものである。
実施例の説明 本発明の実施例を図面を用いて詳しく説明する。
第２図において、１０は半導体基板、１１は補強用樹脂
、１２は溝、１３は半導体ペレット、１４はコレット、
１５は収納容器、１６は外部リードである。半導体素子
製造工程が終了した半導体基板１０の表面に補強用樹脂
１１を第２図（Ａ）のように塗布する。この場合の補強
用樹脂１１の厚みは次の工程を示す第２図中）で研磨す
べき厚みと同じ５１・−ノ 厚み、もしくはそれ以上の厚みになるようにする。
すなわち、同図（Ｂ）において、補強用樹脂１１を塗布
した半導体基板１ｏの裏面を補強用樹脂１１の厚みと同
等分またはそれ以下の厚み分だけ研磨する。この時、半
導体基板１０の表面に形成された半導体素子上に前記補
強用樹脂１１を塗布しているため、研磨時、前記半導体
素子の損傷が無い。
なお、ここで補強用樹脂１１として重合体が加熱により
単量体に分解する樹脂、すなわち熱解重合形樹脂を用い
るとよい。さらに、加熱により分解される樹脂であれば
、上記樹脂に限られるものではないことは明らかである
。
しかるのち、同図（Ｃ）に示すごとく、研磨を行った半
導体基板１ｏをダイシング・ソーを用いて表面に溝１２
を形成し、個々の半導体ペレット１３に分割する。この
時、同図中）と同様に半導体基板１ｏ表面に形成された
半導体素子上に補強用樹脂１１が形成されているため、
ダイシング時の水。
ゴミ等による半導体素子の汚染が無い。
同図中）において、分割された半導体ペレット１３６ペ
ージ をコレット１４にて保持し、人ｕ　／　Ｓｉ共晶法、半
田付法、導電性樹脂接着法等を用いて収納容器１５にダ
イボンドを行なう。この時、半導体ペレット１３は研磨
のため非常に薄い状態であるが、半導体ペレット１３表
面には研磨すべき厚みもしくはそれ以上の厚みの補強用
樹脂１１が形成している。
そのため、半導体ペレット１３の全体の厚さは研磨無し
の半導体ペレットと変わらない。つｔｖ。
補強用樹脂１１の厚さが研磨量を補なっている。
従って半導体ペレットが薄くても、一般の比較的厚さの
厚い半導体ペレットのダイボンドと同様な、クラックの
無い、良好なダイボンドが容易に行なうことが出来る。
同図停）において、補強用樹脂１１熱解重合形樹脂を用
いることによ５．Ａｕ／Ｓｉ共晶法、半田付法を用いて
ペレット１３を接着すると、補強用樹脂１１は熱解重合
形樹脂であるので、樹脂１１はダイボンド時の熱により
完全に分解除去される。
又、導電性樹脂を用いたペレット１３の接着法では、導
電性樹脂の熱硬化時、同じく熱により完全７１・−ジ゛ に除去される。
なお、本発明においては、半導体基板の裏面研磨後、前
記半導体基板表面に同じく補強用樹脂を塗布し、以下工
程を実施例と同様に行ってもよい。
発明の効果 以上の説明により明らかなとおり、半導体基板表面に補
強用樹脂全塗布することにより、研磨。
ダイシング時に、前記半導体基板表面に形成された半導
体素子の損傷、汚染を防ぐことが出来る。
さらに、半導体ペレットダイボンド時、半導体ペレット
表面に研磨される量もしくはそれ以上の補強用樹脂が形
成されているため、半導体ペレット全体の厚さは一般の
半導体ペレットの厚さと変わらず、むしろ厚くなってい
る。従って、コレットによる半導体ペレットの保持が確
実となり、保持された半導体ペレットに無理な力が加わ
らず、クラックの無いダイボンドが可能となる。又、コ
レットの確実な保持により、従来では不可能であった半
導体ペレットと収納容器の圧着接合が出来、良好なダイ
ボンドが可能となる。これによジ半導体素子動作時発す
る熱を効率よく収納容器に伝え、外部に放出することが
出来、発熱に伴なう素子の特性変動が無くなジ、高性能
な半導体装置を得ることが出来る。
【図面の簡単な説明】
第１図（Ａ）、　（Ｂ）は従来のダイボンドの状態を示
す図、第２図（Ａ）〜（ト））は本発明の一実施例のダ
イボンド方法を示す工程断面図である。 １ｏ・・・・・・半導体基板、１１・旧・・補強用樹脂
、１２・・・・・・溝、１３・・・・・・半導体ペレッ
ト、１４・・・・・・コレット、１６・・・・・・収納
容器。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名城 １７３

Claims (6)

    【特許請求の範囲】
  1. （１）多数個の半導体素子が形成された半導体基板表面
    に樹脂を塗布する工程、前記半導体基板の裏面を研磨す
    る工程、前記半導体基板を個々の半導体ペレットに分割
    する工程、前記半導体ペレッ）ｋ収納容器に載置時又は
    載置後、前記樹脂を除去する工程を有することを特徴と
    する半導体装置の製造方法。
  2. （２）樹脂として熱解重合形樹脂を用いることを特徴と
    する特許請求の範囲第１項記載の半導体装置の製造方法
    。
  3. （３）樹脂を半導体基板の裏面の研磨量と同等もしくは
    それ以上塗布することを特徴とする特許請求の範囲第１
    項記載の半導体装置の製造方法。
  4. （４）多数個の半導体素子が形成された半導体基板裏面
    を研磨する工程、前記半導体基板表面に樹脂全塗布する
    工程、前記半導体基板表面々の半２ページ 導体ペレットに分割する工程、前記半導体ベレットヲ収
    納容器に載置時又は載置後、前記樹脂を除去する工程を
    有することを特徴とする半導体装置の製造方法。
  5. （５）樹脂として熱解重合形樹脂を用いることを特徴と
    する特許請求の範囲第４項記載の半導体装置の製造方法
    。
  6. （６）樹脂を半導体基板の裏面の研磨量と同等もしくは
    それ以上塗布することを特徴とする特許請求の範囲第４
    項記載の半導体装置の製造方法。
JP57203011A 1982-11-18 1982-11-18 半導体装置の製造方法 Pending JPS5992536A (ja)

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JP57203011A JPS5992536A (ja) 1982-11-18 1982-11-18 半導体装置の製造方法

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Publications (1)

Publication Number Publication Date
JPS5992536A true JPS5992536A (ja) 1984-05-28

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Country Link
JP (1) JPS5992536A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0675536A1 (en) * 1994-03-31 1995-10-04 AT&T Corp. Process for fabricating an integrated circuit
US7129110B1 (en) * 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US7790578B2 (en) 2006-11-30 2010-09-07 Fujitsu Limited Dicing method using volatile protective agent

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0675536A1 (en) * 1994-03-31 1995-10-04 AT&T Corp. Process for fabricating an integrated circuit
US7129110B1 (en) * 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US7790578B2 (en) 2006-11-30 2010-09-07 Fujitsu Limited Dicing method using volatile protective agent

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