JPS5991721A - Comparison circuit - Google Patents
Comparison circuitInfo
- Publication number
- JPS5991721A JPS5991721A JP20172682A JP20172682A JPS5991721A JP S5991721 A JPS5991721 A JP S5991721A JP 20172682 A JP20172682 A JP 20172682A JP 20172682 A JP20172682 A JP 20172682A JP S5991721 A JPS5991721 A JP S5991721A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resistor
- transistors
- transistor
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
(発明の属する技術分野〕
本発明は、差動トランジスタを用いた比較回路に関し、
特に差動トランジスタのスレッシュボルドレベルを変更
できる比較回路に関するものである。[Detailed description of the invention] (Technical field to which the invention pertains) The present invention relates to a comparison circuit using differential transistors,
In particular, the present invention relates to a comparison circuit that can change the threshold level of differential transistors.
第り図は従来例の比較回路の回路図である。同図におい
て、2個のトランジスタl、2は差動トランジスタを構
成しており、そのエミッタは共通接続し定電流源3に接
続される。トランジスタlのベースにはバイアス抵抗4
.5を、またトランジスタ2のベースにはバイアス抵抗
6.7が接続され、トランジスタlのコレクタにはトラ
ンジス夕18.8、抵抗9からなる出カ回1t’&が接
続されている。ダイオード10.ツェナーダイオード1
1、抵抗12は電圧安定化電源回路であり、安定化電源
電圧Vsを前記の差動トランジスタ1.2等に供給する
。なお、同図中の各端子は、入力端子13、出力端子1
4、非安定化電源端子15、接地端子16、安定化電源
端子17である。FIG. 2 is a circuit diagram of a conventional comparison circuit. In the figure, two transistors 1 and 2 constitute a differential transistor, and their emitters are commonly connected and connected to a constant current source 3. A bias resistor 4 is installed at the base of the transistor l.
.. 5, a bias resistor 6.7 is connected to the base of the transistor 2, and an output circuit 1t'& consisting of a transistor 18.8 and a resistor 9 is connected to the collector of the transistor 1. Diode 10. zener diode 1
1. A resistor 12 is a voltage stabilized power supply circuit, which supplies a stabilized power supply voltage Vs to the differential transistors 1.2 and the like. In addition, each terminal in the same figure is input terminal 13, output terminal 1
4, an unregulated power supply terminal 15, a ground terminal 16, and a stabilized power supply terminal 17.
この回路において、トランジスタ12のそれぞれのベー
ス電位をVa、Vbとすると、ベース電位vbはベース
電位Vaよりも高く設定されており、このベース電位V
a、Vbは次式ただし、R4、Rs 、R6、Rvはそ
れぞれ抵抗4.5.6.7の抵抗値。In this circuit, when the base potentials of the transistors 12 are Va and Vb, the base potential vb is set higher than the base potential Va, and this base potential V
a and Vb are the following formulas. However, R4, Rs, R6, and Rv are the resistance values of resistor 4, 5, 6, and 7, respectively.
で求められる。is required.
この比較回路では、入力端子13がら入力する信号がな
いときに、トランジスタ1が普通状態になるために必要
なスレッシュボルド電圧vthはV th= V b
−V a −(31で示される。In this comparator circuit, the threshold voltage vth required for the transistor 1 to enter the normal state when there is no signal input from the input terminal 13 is V th = V b
-V a -(denoted by 31).
この従来例回路の入力端子Vinと出力電圧V。Input terminal Vin and output voltage V of this conventional circuit.
の関係は第2図に示すようなものとなり、入力電圧Vi
nがスレッシュボルド電圧Vtl+を越えると出力端子
14に出力電圧VOが出力される。The relationship between is as shown in Figure 2, and the input voltage Vi
When n exceeds the threshold voltage Vtl+, the output voltage VO is output to the output terminal 14.
上式(1)〜(3)から明らかなように、この従来例比
較回路ではスレッシュホルド電圧vthが固定されてい
て、半導体集積回路に構成した場合には、スレッシュホ
ルド電圧vthを用途に応じて変化させることができな
い欠点がある。As is clear from the above equations (1) to (3), the threshold voltage vth is fixed in this conventional comparison circuit, and when configured in a semiconductor integrated circuit, the threshold voltage vth can be changed depending on the application. There are drawbacks that cannot be changed.
本発明は、上記の欠点をなくすためになされたものであ
り、外部からの操作で制御電流を変化させて、用途に応
じて容易にスレッシュボルド電圧vthを変化できる比
較回路を提供することを目的とする。The present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a comparison circuit that can easily change the threshold voltage vth according to the application by changing the control current by external operation. shall be.
本発明は、差動回路の二つのトランジスタのベース間に
入力信号のない状態でも電位差を与える回路を設り、こ
の回路の印加電圧を外部から接続するIl(抗の値によ
り変化できるように構成したことを特徴とする。The present invention provides a circuit that provides a potential difference between the bases of two transistors of a differential circuit even when there is no input signal, and the voltage applied to this circuit is configured so that it can be changed depending on the value of Il (resistor) connected from the outside. It is characterized by what it did.
以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.
第3図は本発明に係る比較回路の一実施例を示す回路図
である。FIG. 3 is a circuit diagram showing an embodiment of the comparison circuit according to the present invention.
第3図において入力端子13から入力した信号は、コン
デン920を介してトランジスタ21のベースに導き、
トランジスタ21のエミッタは抵抗22.23をそれぞ
れ介してl・ランジスタ24.25のベースに接続する
。また、トランジスタ24.25のコレクタは共通接続
して安定化電源端子17に導く。In FIG. 3, the signal input from the input terminal 13 is led to the base of the transistor 21 via the capacitor 920,
The emitters of the transistors 21 are connected via resistors 22, 23 respectively to the bases of l transistors 24, 25. Further, the collectors of the transistors 24 and 25 are commonly connected and lead to the stabilized power supply terminal 17.
トランジスタ26.27は差動回路を構成するトランジ
スタであり、トランジスタ26.27のエミッタは共通
接続して定電流源間に、導く。トランジスタ26のベー
スはトランジスタ24のエミッタを接続するとともに1
1(抗29を介して接地する。またl・ランジスタ27
のベースは抵抗園の一端に接続し、この抵抗30の他端
はトランジスタ25のエミッタに接続するとともに抵抗
31を介して接地する。そしてトランジスタ26のコレ
クタには、トランジスタ32.33、抵抗34、出力端
子14からなる出力回路を接続する。Transistors 26 and 27 constitute a differential circuit, and the emitters of the transistors 26 and 27 are commonly connected and led between constant current sources. The base of transistor 26 connects the emitter of transistor 24 and
1 (grounded via the resistor 29. Also, the l transistor 27
The base of the resistor 30 is connected to one end of a resistor garden, and the other end of this resistor 30 is connected to the emitter of the transistor 25 and grounded via a resistor 31. An output circuit consisting of transistors 32 and 33, a resistor 34, and an output terminal 14 is connected to the collector of the transistor 26.
トランジスタ35.36.37、冷、抵抗30.39お
よび可変抵抗40は電流分配回路を構成する。トランジ
スタ35は2個の特性の等しいコレクタを有し、その2
個のコレクタに流れる電流が等しくなるように構成され
ている。トランジスタ36はベースとコレクタを結合し
てダイオード接続される。可変抵抗40は端子41と端
子16との間に外付けされるように構成され、その抵抗
値は任意に選択することができる。この電流分配回路は
、トランジスタ36から可変抵抗40に流れる制御電流
を11、トランジスタ35の各コレクタに流れる電流を
■2とすると、電流11と12との比をに1mにする。Transistors 35, 36, 37, cold resistors 30, 39 and variable resistor 40 constitute a current distribution circuit. Transistor 35 has two collectors of equal characteristics, the two
The structure is such that the current flowing through each collector is equal. Transistor 36 is diode-connected with its base and collector coupled. The variable resistor 40 is configured to be externally connected between the terminal 41 and the terminal 16, and its resistance value can be arbitrarily selected. In this current distribution circuit, when the control current flowing from the transistor 36 to the variable resistor 40 is 11, and the current flowing to each collector of the transistor 35 is 2, the ratio between the currents 11 and 12 is 1 m.
次に、この実施例回路の動作を説明する。Next, the operation of this embodiment circuit will be explained.
′制御端子41に流れる制御電流11はR40
ただし、Vsは安定化電源電圧、
V [+e36はトランジスタ36のエミッタ・ベース
間順方向電圧、
1ン4oは可変抵抗40の抵抗値、
で示される。この電流11とトランジスタ35の一方の
コレクタに流れる電流I2との比は前記のようにl:m
であり、トランジスタ27に流れるベース電流は無視で
きるので、抵抗30の両端に生ずる電位差V30は、
V2O−12°R3o=m °’l 1 °R30と
なる。抵抗22と23、トランジスタ24と25、抵抗
29と31の整合がとれていれば、トランジスタ24と
25のエミッタ・コレクタ間電圧は互いに打ち消しあい
、1−ランジスク26と27で構成される差動トランジ
スタのスレッシュホルド電圧vth’はV2Oと等しく
なり、
V tl+e ’ = V2O−−−(61と
なる。'The control current 11 flowing to the control terminal 41 is expressed as R40, where Vs is the stabilized power supply voltage, V[+e36 is the forward voltage between the emitter and base of the transistor 36, and 1-4o is the resistance value of the variable resistor 40. The ratio of this current 11 to the current I2 flowing through one collector of the transistor 35 is l:m as described above.
Since the base current flowing through the transistor 27 can be ignored, the potential difference V30 generated across the resistor 30 is V2O-12°R3o=m°'l 1°R30. If the resistors 22 and 23, the transistors 24 and 25, and the resistors 29 and 31 are matched, the emitter-collector voltages of the transistors 24 and 25 cancel each other out, and the differential transistor composed of the transistors 26 and 27 The threshold voltage vth' of becomes equal to V2O, and V tl+e '=V2O---(61).
このように、上式(5)および(6)から明らかなよう
に、本発明では抵抗40の抵抗値を可変させることによ
り、スレッシュホルド電圧を任意に変更することができ
る。In this way, as is clear from the above equations (5) and (6), the threshold voltage can be arbitrarily changed by varying the resistance value of the resistor 40 in the present invention.
第4図は本発明に係る比較回路のスレッシュボルド電圧
vth’と抵抗40との関係を示した図であり、抵抗4
0の抵抗値V40が増大すると、スレッシュボルド電圧
Vth’が低下する様子を示す。FIG. 4 is a diagram showing the relationship between the threshold voltage vth' and the resistor 40 of the comparator circuit according to the present invention.
The figure shows how the threshold voltage Vth' decreases as the zero resistance value V40 increases.
以上に述べたように、本発明に係る比較回路はスレッシ
ュホルドレベルが任意に変更できるので、各種の検出用
途に適し、また半導体築積回路化に極めて適している。As described above, since the threshold level of the comparator circuit according to the present invention can be changed arbitrarily, it is suitable for various detection applications and is extremely suitable for use in semiconductor integrated circuits.
第1図は従来例比較回路の回路図。
第2図は従来例比較回路の入出力特性を示す図。
第3図は本発明に係る比較回路の一実施例の回路図。
第4図は本発明に係る比較回路のスレッシュボルド電圧
Vtb“と可変抵抗4oの関係を示す図。
2G、27・・・差動トランジスタ、3o・・・抵抗、
4o・・・可変抵抗。FIG. 1 is a circuit diagram of a conventional comparison circuit. FIG. 2 is a diagram showing input/output characteristics of a conventional comparison circuit. FIG. 3 is a circuit diagram of an embodiment of a comparison circuit according to the present invention. FIG. 4 is a diagram showing the relationship between the threshold voltage Vtb'' of the comparator circuit according to the present invention and the variable resistor 4o. 2G, 27... differential transistor, 3o... resistor,
4o...variable resistance.
Claims (1)
ミッタが共通に接続された差動回路を含み、 この二つのトランジスタのベースのバイアス電圧に差を
設けるように構成され、 この二つのトランジスタのいずれか一方のベースに入力
信号が与えられ、 この二つのトランジスタの少なくとも一方のコレクタか
ら出力信号が取り出されるように構成された比較回路に
おいて、 上記二つのトランジスタの少なくとも一方のベースハイ
アス回路に別のトランジスタ(35)の」レクタ回路が
接続され、 この別のトランジスタのベース回路には、この別のトラ
ンジスタのベースに与えるバイアス電流を定める抵抗器
(40)を含み、 この抵抗器(40)の抵抗値が2個の端子(41,16
)の間に外部接続される抵抗器の値により変更すること
ができるように構成されたことを特徴とする比較回路。[Claims] +1.1 It includes a differential circuit in which the emitters of two I transistors (26, 27) are connected in common, and is configured to provide a difference in bias voltage between the bases of these two transistors. , In a comparator circuit configured such that an input signal is applied to the base of one of these two transistors and an output signal is taken out from the collector of at least one of these two transistors, A receiver circuit of another transistor (35) is connected to the base bias circuit, and the base circuit of this other transistor includes a resistor (40) that determines a bias current to be applied to the base of this other transistor. The resistance value of the device (40) is the same as that of the two terminals (41, 16
) A comparison circuit characterized in that the comparison circuit is configured such that the value can be changed by the value of a resistor externally connected between ).
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20172682A JPS5991721A (en) | 1982-11-17 | 1982-11-17 | Comparison circuit |
US06/552,518 US4634902A (en) | 1982-11-17 | 1983-11-16 | Circuit arrangement capable of adjusting a threshold level of a differential transistor circuit |
DE3341593A DE3341593C2 (en) | 1982-11-17 | 1983-11-17 | Comparator circuit for comparing an input signal with an adjustable comparison voltage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20172682A JPS5991721A (en) | 1982-11-17 | 1982-11-17 | Comparison circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5991721A true JPS5991721A (en) | 1984-05-26 |
JPH0347608B2 JPH0347608B2 (en) | 1991-07-19 |
Family
ID=16445912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20172682A Granted JPS5991721A (en) | 1982-11-17 | 1982-11-17 | Comparison circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5991721A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52105756A (en) * | 1976-03-01 | 1977-09-05 | Sony Corp | Level adjustment circuit |
JPS54159152A (en) * | 1978-06-07 | 1979-12-15 | Hitachi Ltd | Voltage comparison circuit |
-
1982
- 1982-11-17 JP JP20172682A patent/JPS5991721A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52105756A (en) * | 1976-03-01 | 1977-09-05 | Sony Corp | Level adjustment circuit |
JPS54159152A (en) * | 1978-06-07 | 1979-12-15 | Hitachi Ltd | Voltage comparison circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0347608B2 (en) | 1991-07-19 |
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