JPS598890B2 - data detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data detection device for reading data from a magnetic storage medium such as a magnetic tape or a magnetic disk.

Specifically, the present invention relates to a data detection device that reproduces magnetization reversal recorded by a single modulation NRZI recording method and demodulates a pattern of processed recorded data. There is a modulation NRZI recording method as a format for recording high-density binary data in saturation on a magnetic storage medium.

From then on, modulated NRZI recording will be referred to as MNRZI (Modified
d-NRZI) recording. In saturated MNRZI recording, redundant 1 is added to 4-pit data according to certain rules.
Bits are added and converted to 5-pit data for recording, and during conversion, it is prohibited to continue ``o'' for 3 or more bits.The converted data is recorded in the same way as the normal NRZI method. According to the MNRZI recording, as shown in FIG.
001...1'' each frequency (period) 3f
o(To/3) and 1.5fo(To/1.5) and fo(
To), the recording signal w is inverted only when it is binary ``1'', and magnetization reversal is recorded on the storage medium.MNRZI recording is a recording method that allows self-clock discrimination. it is obvious.

However, the reproduction process of data recorded by MNRZI recording has problems such as pit shift, that is, data shifting irregularly from its assigned position, which occurs when data is recorded and reproduced on an unstable magnetic surface. This includes the problem that the reliability of data reproduction detection decreases due to
Especially between frequencies fo and 3fo, 3fo is 1.5f
o is often mistaken. The devices other than the broken line A in FIG. 6 are examples of conventional data detection devices. Figure 3 shows the bit
FIG. 6 is a waveform explanatory diagram illustrating a data detection process assuming a case where there is no shift. The recording medium 40 moves in the direction of the arrow X, and the recording head 41 records the recording data D at
Data D is recorded by inverting the MNRZI recording signal W according to the 0011'' pattern, and the reproducing head 42 reproduces the magnetization inversion, which is amplified by the amplifier 43 to generate a reproduced signal R.

The equalized signal 1 is a signal obtained by phase-equalizing the reproduced signal R by the equalizer 44. This equalizer 44 has, for example, the gain and phase characteristics shown in FIG.
．． Amplify 5f0 and 3f0. (The third of the reproduction frequency FO
The harmonic component is also 3f0. The third harmonic component 4.5f0 of 1.5f0 is attenuated, and the equalized signal 1 whose phase is equalized by the Ω equalizer 44 is converted to the equalized signal 1 by the zero-crossing detector 45VC.
When the signal 2 crosses zero, an H (High) pulse is generated in the signal 2.

The discriminator 46 selects the signal 3 (3f) according to the pulse interval of the signal 2.
0 component), signal 4 (1.5f0 component), and signal 5 (FO component). The discriminator 46 may be one that measures and discriminates normal pulse intervals. Pattern generator 41 generates signal 4
If the pulse interval corresponding to 1.5f0 is obtained, the output '
012 pattern. That is, one H pulse is generated on signal 1, and then one H pulse is generated on signal 6. Pattern generator 48 produces a SOOlI pattern at its output if a pulse interval corresponding to FO is obtained in signal 5. That is, two H pulses are generated on signal 9, and then one H pulse is generated on signal 8.
produces a pulse. Signals 3 and 8 are connected to the 0R circuit 50rc to generate an H pulse in the signal 10 and record the t1 pattern in the register 51. Signals 7 and 9 are connected to an 0R circuit 49 to generate a signal 11 and record an O or 100'' pattern in the register 51. If data reproduction is performed normally,
'110011010011'' pattern of recorded data D and contents 12 of register 51 '11001101001'
1″ pattern matches.

Next, the case where a bit shift occurs in the reproduced signal will be explained using the waveform explanatory diagram of FIG. 4 and the example of the data detection device of FIG. 6.

A 110011010011'' pattern of recording data D was recorded, and its equalized signal 1 was detected to include a bit shift compared to the ideal equalized signal 35.

The output signal 2 of the zero-crossing detector 45 is ΔTl, ΔT2, ΔT3, ΔT4, ΔT from the original position indicated by the broken line.
It was detected with a shift like 5. Regarding signals 3, 4, and 5, what should have been signal 3 a was mistakenly recognized as signal 4 b.
Similarly, if c is erroneously detected as d, e is erroneously detected as FVClg is erroneously detected as h, the contents 12 of register 51 are 1010.
0101001011'' pattern, recording data D
(The pattern will be different from the D whisper 110011010011I pattern.) In other words, the conventional data detection device uses the zero-crossing pulse interval as the source of data detection, so it has the drawback of making such serious erroneous detections. SUMMARY OF THE INVENTION An object of the present invention is to provide a highly redundant system for correcting errors by adding new devices to improve the shortcomings of conventional data detection systems.

The most distinctive feature of the present invention is that by recognizing the waveform of the equalized signal, the 1001'' pattern can be recognized even if a bit shift occurs, and the 1001'' pattern that occurs one before or one after the 1001'' pattern can be recognized. The trick is to anticipate the increase in bit shifts and correct the error.

The embodiment of the present invention is constructed by adding a device surrounded by a broken line A to the conventional data detecting device example shown in FIG. 6, and a waveform explanatory diagram is shown in FIG.

FIG. 5 shows an equalized signal 1 obtained by recording and reproducing the VllOOllOlOOll'' pattern of the recording data D, which is the same as that shown in FIG. 4, and whose phase is equalized by the equalizer 44.

Bit shifting is also described as being the same as used in FIG. Equalized signal 1 is delayed by delay circuit 52 to produce signal 20 shown by the dashed line. Comparator 53 generates an H pulse in signal 21 at the position where equalized signal 1 and signal 20 intersect. Signal 20, on the other hand, is rectified by rectifier 54 to produce signal 22. The pulser 55 provides a slice level 23 for the signal 22, and when the signal 22 is greater than the slice level, the signal 2
4 is at H level, and when it is low, signal 24 is at L level. The number of pulses of signal 21 that occur during the H level of signal 24 varies depending on the data pattern. It can be seen that in the case of the 11001'' pattern, three H pulses are generated in the signal 21.

For '11'' pattern and '101I pattern, signal 21
VC generates one H pulse. 1100 due to this
It will be seen that it is possible to distinguish between the 1I pattern, the 11'' pattern, and the 101'' pattern. Counter 5
6 generates an H pulse in the signal 25 when the pattern is '1001''. Also, an H pulse is generated in the signal 26 when the pattern is the whisper 11I pattern and the pattern '101''. The discriminator 46VC has a function of generating a hold signal 27 near the boundary for discriminating whether the pulse interval of the signal 2 is a ζ11 pattern, a 1101I pattern, or a 1001'' pattern.・The maximum amount of shag is 2t in both cases.
Assuming that the 11I pattern interval is T, the 11'' pattern interval ST becomes T-2t<ST<T+2t, and Sl
The interval S2T in the Ol'' pattern is 2T-2t<S2T<
2T+2t. ．． The interval S3T in the S1001 pattern is 3T-2t<S3T<3T+2t. t=0.25
If T, then 0.5T<ST<1.5T11.5T
<S2T<2.5T 12.5T<S3T (3.5T), and there is a great possibility that ST-5S2T will be misidentified near 1.5T. At around 2.5T, there is a great possibility that S2T and S3T will be mistakenly recognized.

Fig. 8 shows →l in the case of providing a reservation zone t'' according to the present invention. do.

When the pulse interval of the signal 2 increases or decreases and the pulse interval falls within this reservation zone, it is set to a reservation state and a reservation signal 2T is generated.
Even with the present invention, if the pulse interval of signal 2 exceeds the reservation zone, it cannot be corrected. Further, in the present invention, the following conditions are attached. ()(1) The 1001I pattern can be recognized regardless of the size of the bit shift. (2)ゞ100
A state in which the Sll pattern before or after one turn is incorrect generates a pending state and is mistakenly recognized as a 101i pattern. (3) If the TlOlI pattern before or after the 1001I pattern is incorrect, a pending state will occur and it will be mistakenly recognized as the SlOOl'' pattern. (4) If the TlOlI pattern is incorrect before or after the 1001I pattern, it will be mistaken as a SlOOl'' pattern. An error between the pattern and the Sll'' pattern will not occur. After setting the above conditions, the method for correcting the data error will be explained next.
! ! I misunderstood it as a pattern. Naturally, this ゜101'' pattern is stored as も01I in the registers 51 and 58.Next, when the SlOOl'' pattern is normally detected, the discriminator 51
learns the signals 25 and 26, the pending signal 27, and the contents of the register from the signal 33, and the signals 28 and 29vc 1001I pattern is generated, and the contents of register 58 are m01001'' of 30.
Modify the pattern to ゜1001'' like n in content 31. Next, use j to change the content 12 of register 51 and register 5.
8 content 30 should be ゞ11I pattern'101
It was mistakenly detected as an I pattern. At this time, since the previous state was the SlOOl'' pattern, the o゜01I of the contents 30 of the register 58 is modified to も1〃 as shown in the p of the contents 31. Next, with k, the whisper 012 should be changed to the whisper 001I. I made a mistake.Next, I mistakenly read l' (which should be "001" as "SOl").At this time, an H pulse is generated at u of signal 25, so
SOl〃 is ゞ001″, that is, ゜101″ pattern is Vh
It can be seen that it is a lOObi pattern. For this reason, register 5
8 content 30 rゞ0010I is content 31 SlOlO
According to the present invention, the recorded data D110011010011'' pattern is modified to the content 12S101001010 of the register 51 in the conventional device.
I mistakenly thought it was the 01011I pattern, but I put this in sequential register''
The contents of the register 58 are modified as shown in the SllOOllOlOOll'' pattern of the contents 31. In the present invention, the use of the output data 32 of the register 51 and the output data 34 of the register 3t58 is not mentioned, but it is processed by the subsequent device.
Conventionally, pattern detection has been performed by demodulating recorded data using pulse intervals (there is also a discrimination method using peak detection). The reliability of data detection can be significantly improved by a method that effectively utilizes differences in waveforms.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of modulated NRZ recording, FIG. 2 is a diagram showing an example of the gain and phase characteristics of an equalizer, FIGS. 3 and 4 are waveform explanatory diagrams of an example of a conventional data detection device, and FIG. FIG. 6 is a diagram illustrating waveforms of an embodiment of the invention, FIG. 6 is a diagram illustrating an embodiment of a conventional data detection device and an embodiment of the device of the present invention, and FIGS. 7 and 8 are diagrams explanatory of pattern intervals. . 1... Equalization signal, 27... Holding signal,
44...Equalizer, 46...Discriminator, 5
3... Comparator, 55... Counter, 57
...Discriminator, 51, 58... Lujista.

Claims (1)

[Claims] 1 a first signal with a predetermined period and 1/1 of the first signal.
In a data detection device for reproducing and demodulating data from a recording medium, the data consists of a combination of a second signal having 5 periods and a third signal having 1/3 period of the first signal.
, an equalizer that enhances the respective frequency components of the second and third signals and attenuates the third harmonic component of the second signal; 2. means for discriminating the third signal and generating a holding signal near the boundary of each signal period;
, a means for generating pulses in a predetermined pattern in response to the second and third signals, and creating reproduced data of a combination of the pulses; a register for storing the reproduced data; and a register for storing the reproduced data; It comprises means for monitoring the output waveform and generating a discrimination signal corresponding to the pattern of recorded data, and means for modifying the stored contents of the register based on the discrimination signal, the suspension signal, and the contents of the register. A data detection device characterized by: