JPS5987851A - Semiconductor integrated circuit and its manufacture - Google Patents

Semiconductor integrated circuit and its manufacture

Info

Publication number
JPS5987851A
JPS5987851A JP57196983A JP19698382A JPS5987851A JP S5987851 A JPS5987851 A JP S5987851A JP 57196983 A JP57196983 A JP 57196983A JP 19698382 A JP19698382 A JP 19698382A JP S5987851 A JPS5987851 A JP S5987851A
Authority
JP
Japan
Prior art keywords
insulating film
vertical
emitter
base
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57196983A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakai
坂井 弘之
Kenji Kawakita
川北 憲司
Tsutomu Fujita
勉 藤田
Toyoki Takemoto
竹本 豊樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57196983A priority Critical patent/JPS5987851A/en
Publication of JPS5987851A publication Critical patent/JPS5987851A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8228Complementary devices, e.g. complementary transistors
    • H01L21/82285Complementary vertical transistors

Abstract

PURPOSE:To improve the high-frequency characteristics of both a vertical type NPN transistor and a vertical type PNP transistor while increasing their speed and density by forming the integral structure of the vertical NPN transistor and the vertical type PNP transistor. CONSTITUTION:A nitride film 26, a foundation oxide film 25 and an N type epitaxial layer are etched while using a resist film 27 as a mask. The nitride film 26 is patterned again, and an oxide film 29 is formed between a base and a collector-contact in the vertical type NPN transistor (Tr) and an oxide film 29 around an emitter in the vertical type PNP Tr. Poly Si 32 is formed to the whole surface, a nitride film 33 is formed on the poly Si, and the nitride film 33 is patterned and the poly Si 32 and the N type epitaxial layer 24 are etched through a photolithography method. High-concentration N<+> regions 35a-35c are formed while using the resist film as a mask. The regions 35a, 35b each form an emitter and the collector-contact in the vertical type NPN Tr, and the region 35c forms a base-contact in the vertical type PNP Tr.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は絶縁分離方式で高速化・高密度化を図った半導
体集積回路およびその製造方法に関するものであシ、従
来困難とされていた縦形IN P IN )ランリスタ
(以下縦形NPNTrと称す・る)と縦形PNP)ラン
リスタ(以下縦形PNPTrと称する)の一体化構造を
縦形NPNTtの特性を劣化させることなく、しかも簡
便な方法で非常に四速で高密度な縦形P N P 、 
’I’rを製造可能としたものである。
[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a semiconductor integrated circuit that achieves high speed and high density using an insulation isolation method and a method for manufacturing the same. The integrated structure of IN) run lister (hereinafter referred to as vertical NPNTr) and vertical PNP) run lister (hereinafter referred to as vertical PNPTr) can be achieved in a very simple manner at four speeds without deteriorating the characteristics of vertical NPNTt. Dense vertical PNP,
This makes it possible to manufacture 'I'r.

従来例の構成とその問題点 近年、半導体集積回路はまず1す高速・高密度化の方向
に進み、絶縁分離方式による半導体集積回路の研究が活
発に行なわれている。
Conventional Structures and Their Problems In recent years, semiconductor integrated circuits have been moving in the direction of higher speeds and higher densities, and research on semiconductor integrated circuits using the insulation isolation method has been actively conducted.

本出願人はすでに従来の絶縁分離方式による縦形NPN
Trを改良し、構造的・特性的・プロセス的にも非常に
優れた縦形NPNTrの提案をし、更にはその縦形NP
NTrと横形PNPTrとの一体化構造も提案してきた
。その縦形NPNTrと横形PNPTrとの一体化構造
を第1図に示す。
The applicant has already developed a vertical NPN using the conventional insulation isolation method.
We improved the Tr and proposed a vertical NPNTr with excellent structure, characteristics, and process, and further developed the vertical NPNTr.
We have also proposed an integrated structure of an NTr and a horizontal PNPTr. The integrated structure of the vertical NPNTr and horizontal PNPTr is shown in FIG.

第1図において、1はたとえばP型半導体基板、2はn
+埋込み層、3は高濃度P領域で、素子間分離酸化膜形
成時に生じるn型反転層を打ち消すだめのチャネルΦス
トッパーである。4 ii ’n型エピタキシャル層、
5は素子間分離酸化膜である。
In FIG. 1, 1 is, for example, a P-type semiconductor substrate, and 2 is an n-type semiconductor substrate.
+Buried layer 3 is a heavily doped P region and serves as a channel Φ stopper for canceling out the n-type inversion layer generated when forming the element isolation oxide film. 4 ii 'n type epitaxial layer,
5 is an element isolation oxide film.

これで、高量分離は完了している。以下、縦形NPNT
rについて、先に説明する。なお、同一工程で形成され
る領域は同−香りで示し、横形PNPTrについては全
て′をっけて示す。縦形NPNTrにおいて、6はベー
スとコレクタ・コンタクトを分離している酸化膜(ベー
ス・コレクタ間分離酸化膜)、7はコレクタ・ウオール
、8は低濃度p−領領域活性ベースを形成している。
High-volume separation is now complete. Below, vertical NPNT
r will be explained first. Note that regions formed in the same process are indicated by the same color, and horizontal PNPTrs are all indicated by ''. In the vertical NPNTr, numeral 6 forms an oxide film separating the base and collector contact (base-collector isolation oxide film), 7 forms a collector wall, and 8 forms a low concentration p-region active base.

9はA6電極引き出し用のpoly St、 10はエ
ミッタとベース・コンタクトを分離している酸化膜(エ
ミッタ・ベース間分離酸化膜)、11a。
9 is polySt for drawing out the A6 electrode, 10 is an oxide film separating the emitter and base contact (emitter-base isolation oxide film), and 11a.

11bは高濃度n+領領域11aはエミッタ、11bけ
コレクタ・コンタクトを形成している。12は高濃度p
+領領域不活性ベース饋域を形成しており、エミッタ・
ベース間分離酸化膜下部は深く、ベースコンタクト部は
浅く、しかも連続して形成されている。13はAl電極
配線である。
11b, the high concentration n+ region 11a forms an emitter, and 11b forms a collector contact. 12 is high concentration p
+ area forms an inert base area, emitter
The lower part of the base isolation oxide film is deep, and the base contact part is shallow and continuous. 13 is an Al electrode wiring.

この縦形NPNTtの特長は、エミッタ・ベース接合、
コレクタ・べ〜ス接合およびコレクタ領域の側面がすべ
て酸化膜で覆われている1、ので、寄生容量が極力小さ
くなっていること、−態度不活性ベース12をイオン注
入によって、エミツタ118端部より自己整合的に形成
することによりベース抵抗を小さくしていることである
。それ故、高周波特性を改吾し、高速化ならびに高密度
化を図ることができる。
The features of this vertical NPNTt are the emitter-base junction,
Since the sides of the collector-base junction and the collector region are all covered with an oxide film 1, the parasitic capacitance is as small as possible. By forming the base in a self-aligned manner, the base resistance is reduced. Therefore, it is possible to improve the high frequency characteristics and achieve higher speed and higher density.

次に、第1図の横形PNPTrについて説明する。7′
はコレクタ・ウオール7と同一工程で形成される計領域
でベース抵抗を小さくしている。
Next, the horizontal PNPTr shown in FIG. 1 will be explained. 7′
The base resistance is reduced in the total region formed in the same process as the collector wall 7.

8’a 、 s’bは低濃度p−領領域活性ベース)8
と同一工程で形成される横形PNPTrのエミッタ、コ
レクタの一部となるp″領域9′はpolySt 9と
同一工程で形成されており、縦形NPN醜 Trと同様にへl電極引き出し用のpoly Stであ
る。10′は縦形NPNTrのエミッタ拳ベース間分離
酸化膜10と同一工程で形成される横形P N P T
rのエミッタとコレクタを分離している酸化膜、11′
は縦形N P IJ Trのエミッタ11a1コレクタ
・コンタクト11bと同一工程で形成される横形NPN
Trのベース・コンタクト、12′a 、 12’bは
高濃度p ’l−領域(不活性ベース)12と同一工程
で形成されるp″−領域で、エミッタ及びコレクタの一
部を構成するものである。13′はAe電極配線である
8'a, s'b are low concentration p-region active bases)8
The p'' region 9', which becomes part of the emitter and collector of the horizontal PNPTr, is formed in the same process as the polySt 9, and like the vertical NPN ugly Tr, the polySt for leading out the l electrode is formed in the same process. 10' is a horizontal PNPT formed in the same process as the emitter-base separation oxide film 10 of the vertical NPNTr.
oxide film separating the emitter and collector of r, 11'
is a horizontal NPN formed in the same process as the emitter 11a1 collector contact 11b of the vertical NPIJ Tr.
The base contacts 12'a and 12'b of the Tr are p''-regions formed in the same process as the high concentration p'l-region (inactive base) 12, and constitute part of the emitter and collector. 13' is an Ae electrode wiring.

一般的に横形PNPTrQ問題点としては次のような頓
目がある。
Generally, the problems with horizontal PNPTrQ are as follows.

■ 電流(少数キャリア)が表面近傍を流れるので表面
の影響を非常に受けやすく、表面近傍における生成−再
結合によるリーク電流が多く、電流増幅率hFEがあま
り高くできない。
(2) Since the current (minority carriers) flows near the surface, it is very susceptible to the influence of the surface, and there is a lot of leakage current due to generation and recombination near the surface, so the current amplification factor hFE cannot be very high.

■ エミッタ接合にバイアス電圧をかけたとき、空乏層
は横方向ベースに向かって伸びるだめ、横方向ベース幅
(図中aで示している)が短いとパンチスルーを起こし
やすい。
(2) When a bias voltage is applied to the emitter junction, the depletion layer does not extend toward the lateral base, so if the lateral base width (indicated by a in the figure) is short, punch-through is likely to occur.

■ 電流が横方向に流れるので、デバイス!1¥性を決
めるディメンジョンが横方向で決定される。ずなわぢ、
フォトリソグラフィー、エツチング等の加工技術、およ
び拡散における横方向広がりによってデバイスの特性が
決められる。そのため、特性を決めるのに重要であるベ
ース幅が3〜41zmと縦形NPNTrに比べ1ケタ大
きくなってしまう。
■ Since the current flows horizontally, the device! 1 The dimension that determines gender is determined in the horizontal direction. Zunawaji,
Processing techniques such as photolithography, etching, and lateral extent of diffusion determine device properties. Therefore, the base width, which is important in determining the characteristics, is 3 to 41 zm, which is one order of magnitude larger than that of the vertical NPNTr.

■ 周波数特性d、ベース幅が広く、また縦形NPNT
rのようにドリフト電界もないので、周波数特性が悪く
、利得帯域幅積■1を高くすることができない。
■ Frequency characteristics d, wide base width, and vertical NPNT
Since there is no drift electric field like r, the frequency characteristics are poor and the gain bandwidth product (1) cannot be made high.

■ 電流が横方向に流れるので、Tr而面も横方向で決
まってしまい、Tr内面積縦形NPNTrに比べて非常
に大きくなる。
(2) Since the current flows in the horizontal direction, the Tr surface is also determined in the horizontal direction, and the internal area of the Tr is much larger than that of a vertical NPNTr.

このように、横形P 1’J P i’rの欠点(l−
1,電流が横方向に流れるため、ベース幅が広くなり高
周波特性が良くないことと、Tr内面積大きくなってし
まうことである。実h、本出願人が提案した第1図のも
り形PNPTrの面積は縦形N P N ’ryに比べ
て、約3倍も大きくなっている。
In this way, the drawback (l-
1. Since the current flows in the lateral direction, the base width becomes wide, resulting in poor high frequency characteristics, and the internal area of the transistor becomes large. In fact, the area of the cylindrical PNPTr shown in FIG. 1 proposed by the present applicant is about three times larger than that of the vertical N P N 'ry.

IC,LSIの役割においては、回路膜d1土blPN
 Tr 、 PNP Trの両方f更用できることが望
捷しい。しかし横形PIすP Tr fJ、縦形□VI
PNTrに比べて高周波特性が非常に悪く、しかもTr
而面が大きいのでIC,LSIの回路膜用における回路
特性を十分発揮することができないため、横形PINP
Trを使うのを避けて、縦形IN’ P iすTrのみ
を使用して回路設割をすることか多い。ぞのため、回路
設剖−ヒ、大きな制約を受けることになる。IC,LS
Iの役割においては、縦形NPNTrと同程度の特性を
有する縦形P N P Trを使用することができれば
、回路設言1が容易で、しかも回路特性を十分発揮する
ことが可能となる。よって、縦形NPNTrと同程度の
特性を発揮する縦形P N P Trの製造が可能な構
造およびプロセスが望まれる。
In the role of IC, LSI, circuit membrane d1 earth blPN
It is desirable that both Tr and PNP Tr can be used. However, horizontal type PI Tr fJ, vertical type □VI
The high frequency characteristics are very poor compared to PNTr, and Tr
Horizontal PINP is not suitable for IC and LSI circuit films due to its large surface area.
It is often the case that circuits are designed using only vertical IN'Pi transistors, avoiding the use of transistors. Therefore, the circuit design is subject to major restrictions. IC,LS
In the role of I, if a vertical PNPTr having characteristics comparable to those of the vertical NPNTr can be used, circuit proposition 1 can be easily achieved and the circuit characteristics can be sufficiently exhibited. Therefore, a structure and process that can manufacture a vertical PNPTr that exhibits characteristics comparable to those of the vertical NPNTr are desired.

発明の目的 本発明はこのような問題の検討に鑑み、縦形NPNTr
の周波数特性が非常に良く、高速で高密度、しかも製造
が簡単であるという利点を十分に生かし、しかも同−j
JjJ造工程で高周波牛j性が縦形NPNTrと同程度
で、面績的にも縦形1(P NTrとあまシ違わない縦
形PNPTrを形成しつる一体化構造およびその製造方
法を提供するものである。
Purpose of the Invention In view of the above-mentioned problems, the present invention provides a vertical NPNTr.
It takes full advantage of the advantages of very good frequency characteristics, high speed, high density, and easy manufacturing.
The present invention provides an integrated structure that forms a vertical PNPTr whose high frequency resistance is on the same level as a vertical NPNTr in the JJ manufacturing process, and which is exactly the same as a vertical NPNTr in terms of performance and a method for manufacturing the same. .

発明の構成 本発明は第1の絶縁膜により素子間分離された島領域に
、縦形NPNTrと縦形P N P Trを同一工程で
形成するものであり、縦形NPNTrではエミッタの周
囲が第1.第2.第3の絶縁膜で榎われており、縦形P
NPTrではエミッタの周囲は第4.第5の絶縁膜(第
2の絶縁膜と同一工程で形成されるン、エミッタ・コレ
クタ間にi:第4の絶縁膜に接して第6の絶縁膜(第3
の絶縁膜と同一工程で形成される)が形成されており、
半導体集積回路の高密度かつ高速化を実現し、縦形NP
NTrではMl;3の絶縁膜下部、縦形P N P T
rでは第6の絶縁膜下部は他の部分より深くP型半導体
領域を自己整合的に形成された半導体集積回路及びその
製造方法である。
Structure of the Invention According to the present invention, a vertical NPNTr and a vertical PNP Tr are formed in the same process in an island region separated between elements by a first insulating film, and in the vertical NPNTr, the emitter is surrounded by the first. Second. It is covered with a third insulating film, and the vertical P
In NPTr, the area around the emitter is the 4th. A fifth insulating film (formed in the same process as the second insulating film) between the emitter and collector: a sixth insulating film (the third
) is formed in the same process as the insulating film of
Achieving high density and high speed semiconductor integrated circuits, vertical NP
In NTr, lower part of insulating film of Ml; 3, vertical P N P T
In r, a semiconductor integrated circuit and a method for manufacturing the same are provided in which a P-type semiconductor region is formed in a self-aligned manner in a lower part of a sixth insulating film deeper than in other parts.

実施例の説明 第2図に縦形NPNTrど縦形PNPTrを一体化した
本発明(の一実施例)の半導体集積回路の構造を示す。
DESCRIPTION OF EMBODIMENTS FIG. 2 shows the structure of a semiconductor integrated circuit according to the present invention (one embodiment) in which a vertical PNPTr is integrated.

第2図において、縦形N P N Trは第1図の縦形
NPNTrと構造は全く同じなので、第1図と同一番号
で示す。縦形PINP’l’rについては同一製造工程
で形成される領域は同一番号で示し、全て“をつけて示
す。同図において、3″a、 3”bは高濃度P領域で
あυ、3“aは原子間分離酸化膜6〃の直下に形成され
ており、チャネル・ストッパーの役目の果たしている。
In FIG. 2, the vertical NPN Tr has the same structure as the vertical NPNTr in FIG. 1, so it is indicated by the same number as in FIG. For the vertical PINP'l'r, regions formed in the same manufacturing process are indicated by the same number, and all are marked with ". In the figure, 3"a and 3"b are high concentration P regions υ, 3 "a" is formed directly under the atomic isolation oxide film 6, and serves as a channel stopper.

3“bは本発明の特長であり、縦形PNPTtの島預域
全体に形成されている。なおn十埋込層2は縦形NPN
Tr、縦形PNPTrとも島領域全体に形成されている
。この高濃度P領域3 、3”a、 3”bはn型エピ
タキシャル層4を形成する前に形成されている。その後
、n型エピタキシャル層4、素子間分離酸化膜6,6〃
を形成すると、この高濃度P領域は上方向に拡散してい
く。しかしながら3.3“αの領域には素子間分離酸化
膜6,6“が形成されるので上方向に拡散していった高
濃度P領域は酸化膜になる。ところが、3“bの領域は
島領域であるので、高濃度P領域3”bはn型エピタキ
シャル層4中を上方向へ拡散していく。縦形PNPTr
の島領域にはn+埋込層2〃および高濃度P領域3“b
とが形成されているが、高濃度P領域3“bはn型エピ
タキシャル層4を形成する前には熱処理をしないので、
まだ拡散はされていない。n型エピタキシャル層4、素
子間分離酸化膜5,6“を形成するときに高濃度P領域
3″bは拡散されていく。たとえはn 埋込層2“をA
s、高濃度P領域3″bをBで形成すると、1000℃
におけるAsの拡散係数は約2×1015crl/ s
eC,Bの拡散係数は約1.2 X 10  o+Vs
ecでBの拡散係数は八8の拡散係数の約6倍である。
3"b is a feature of the present invention, and is formed in the entire island deposit area of the vertical PNPTt. Note that the buried layer 2 is a vertical NPN
Both the Tr and the vertical PNPTr are formed over the entire island region. These high concentration P regions 3, 3"a, 3"b are formed before forming the n-type epitaxial layer 4. After that, the n-type epitaxial layer 4, the element isolation oxide films 6, 6
, this high concentration P region diffuses upward. However, since inter-element isolation oxide films 6, 6" are formed in the region of 3.3"α, the high concentration P region that has diffused upward becomes an oxide film. However, since the region 3"b is an island region, the high concentration P region 3"b diffuses upward in the n-type epitaxial layer 4. Vertical PNPTr
An n+ buried layer 2 and a high concentration P region 3"b are in the island region
However, since the high concentration P region 3"b is not heat-treated before forming the n-type epitaxial layer 4,
It has not spread yet. When forming the n-type epitaxial layer 4 and the element isolation oxide films 5 and 6'', the high concentration P region 3''b is diffused. For example, n buried layer 2” is A
s, when the high concentration P region 3″b is formed of B, the temperature is 1000°C.
The diffusion coefficient of As in is about 2×1015 crl/s
The diffusion coefficient of eC,B is approximately 1.2 x 10 o+Vs
In ec, the diffusion coefficient of B is about 6 times that of 88.

そのため、n型エピタキシャル層4、素子間分離酸化膜
6,5“形成時に、高濃度P領域3tがn+埋込み層2
〃に比べて、上方向へ大きく拡散していくわけである。
Therefore, when forming the n-type epitaxial layer 4 and the element isolation oxide films 6 and 5'', the high concentration P region 3t is removed from the n+ buried layer 2.
Compared to 〃, it diffuses significantly upward.

仁のようにして、素子間分離酸化膜5,5”形成後、縦
形NPNTrの島領域はn型エピタキシャル層4のみが
形成されておシ、縦形PNPTrの島領域にはn型エピ
タキシャル層4中に高濃度P領域が大きく持ち上がって
いることになる。6“a、6“bは縦形NPNTrのベ
ース・コレクタ間分離酸化膜6と同一工程で形成される
縦形P 1′4P Trのエミッタを分離している酸化
膜、8“は活性ベース8と同一工程で形成さJLる縦形
P1すPl“rのコレクタの一部となるp−領域、9“
はpoly St、 10“はエミッタ・ベース間分離
酸化膜10と同一工程で形成される酸化膜で、6“bの
酸化膜に接してコレクタの所定領域に形成されている。
After forming the element isolation oxide films 5, 5'' as shown in FIG. 6"a and 6"b separate the emitter of the vertical P1'4P Tr, which is formed in the same process as the base-collector isolation oxide film 6 of the vertical NPNTr. The oxide film 8" formed in the same process as the active base 8 is the p-region 9" which becomes part of the collector of the vertical P1 and Pl"r.
is polySt, 10'' is an oxide film formed in the same process as the emitter-base isolation oxide film 10, and is formed in a predetermined region of the collector in contact with the oxide film 6''b.

11“はエミッタ11a1コレクタ・コンタクト11b
と同一工程で形成される縦形P14PTrのベース・コ
ンタクト、12”a、 12“bは高濃度p+領領域不
活性ベース)12と同一工程で形成される高濃度p 領
域で12”aはエミッタ、12”bはコレクタ・コンタ
クトを形成している。この高温度p+領領域2”a、1
2“bを形成することが本発明の特長であシ、ベース・
コンタクト11“上をレジスト膜で覆って、イオン注入
によシ、エミッタ12″a1酸化膜6“b、1o”。
11" is emitter 11a1 collector contact 11b
The base contact of the vertical P14PTr is formed in the same process as 12"a and 12"b are the high concentration p + region (inactive base), the high concentration p region is formed in the same process as 12, and 12"a is the emitter, 12''b forms a collector contact. This high temperature p+ region 2”a, 1
The feature of the present invention is to form 2"b.
Contact 11'' is covered with a resist film and ion implantation is performed to form emitter 12''a1 oxide film 6''b, 1o''.

コレクタ8“上に形成している。6”bの酸化膜は60
00人、10“の酸化膜は1800人形成しているので
、イオン注入のイオン飛柱upを約2000八になるよ
うBを注入すると酸化膜6″b上に打ち込捷れたBはn
型エピタキシャル層4中には拡散しないので、エミッタ
とコレクタはこの酸化膜6“bによって自己整合的に分
離される。また、poly St 9”の膜厚は200
0人であるので、Bはコレクタ領域上で、酸化膜10“
の直下の低濃度が領域とpoly St 9“とn型エ
ピタキシャル層4の境界近辺に打ち込まれる。その後、
熱処理によって、酸化膜10“の直下にす]ぢ込1れた
高濃度p+領領域2“bは下から持ち上がったきた高濃
度P領域3″bとつなが9、コレクタ・コンタクトを形
成する。一方、エミッタ上に打ち込まれた高濃度p+領
領域2″aはRpが浅いので高濃度P領域3“bとつな
がらないので、自己整合的にベース幅(図中すで示す)
を形成する。このベース幅すはpoly St 9”と
酸化膜1o〃の段差によって決するので0.2μmと非
常に薄くできる。それ故、高周波特性を改善し、非常に
高速な縦形PNPTrを形成することが可能になる。1
だ、同じ設計ルールでも縦形N P N Ttに比べて
、この縦形PNPTrの面積は約1.2倍と従来の横型
PNPTrに比べると大幅に面積を小さくすることがで
き、高密度化に大いに寄与する。13″はA4電極配線
であり、こhで素子が完成してぃる。
It is formed on the collector 8".The oxide film of 6"b is 60
Since the oxide film of 00 and 10" is formed by 1800 people, when B is implanted so that the ion beam up of the ion implantation becomes about 20008, the B implanted and broken on the oxide film 6"b is n.
Since it does not diffuse into the type epitaxial layer 4, the emitter and collector are separated in a self-aligned manner by this oxide film 6"b. Furthermore, the film thickness of the polySt 9" is 200 mm.
0, B has an oxide film 10" on the collector region.
A low concentration immediately below is implanted near the boundary between the region and the n-type epitaxial layer 4. Then,
By heat treatment, the highly doped p+ region 2''b, which is indented directly under the oxide film 10'', is connected to the high doped P region 3''b raised from below to form a collector contact. , the high concentration P+ region 2''a implanted on the emitter has a shallow Rp and is not connected to the high concentration P region 3''b, so the base width (already shown in the figure) is adjusted in a self-aligned manner.
form. This base width is determined by the step difference between the polySt 9" and the oxide film 1o, so it can be made as extremely thin as 0.2 μm. Therefore, it is possible to improve the high frequency characteristics and form a very high-speed vertical PNPTr. It will become.1
However, even with the same design rules, the area of this vertical PNPTr is approximately 1.2 times that of the vertical N P N Tt, which is significantly smaller than the conventional horizontal PNPTr, and greatly contributes to higher density. do. 13'' is A4 electrode wiring, and the device is completed with this.

以下、第3図A−Gとともに本発明の一体化構造を適用
した半導体集積回路の具体的な製造方法の一実施例を示
す。
An embodiment of a specific method for manufacturing a semiconductor integrated circuit to which the integrated structure of the present invention is applied will be shown below with reference to FIGS. 3A to 3G.

第3図Aにおいて、21はたとえばP型半導体基板、2
2はn+即込み層で島領域となる部分に形成されている
。23は高濃度P領域で、縦形NPNTrにおいては素
子間分離領域上のみ、縦形PNPTrにおいては素子間
分離領域および島領域上に形成されている。24はn型
エビタギンヤル層で1.27m形成している。25は下
地酸化膜で500人、26は窒化膜で1000人形成し
ている。27はレジスI・膜でパターニングされている
。その後、このレジスト膜27をマスクとして、窒化膜
26、下地酸化膜25、そしてn型エピタキノヤル層を
0.75 Ixnエツチングしている(第3図(B))
In FIG. 3A, 21 is, for example, a P-type semiconductor substrate, 2
Reference numeral 2 denotes an n+ implant layer, which is formed in a portion that will become an island region. A high concentration P region 23 is formed only on the element isolation region in the vertical NPNTr, and on the element isolation region and the island region in the vertical PNPTr. 24 is an n-type Evitaginyar layer with a thickness of 1.27 m. 25 is a base oxide film formed by 500 people, and 26 is a nitride film formed by 1000 people. 27 is patterned with resist I/film. Thereafter, using this resist film 27 as a mask, the nitride film 26, base oxide film 25, and n-type epitaxial layer are etched by 0.75 Ixn (FIG. 3(B)).
.

第3図Cにおいては、窒化膜26をマスクとして選択酸
化により素子間分離「襞化膜28を1.6/1m形成し
ている。このときの選択酸化は高圧酸素子間分離酸化膜
が形成される。そして、高濃度P領域23bの持ち土が
りは約0.65μmである。
In FIG. 3C, a 1.6/1 m long folded film 28 is formed by selective oxidation using the nitride film 26 as a mask. At this time, a high-pressure oxygen isolation oxide film is formed by selective oxidation. The high-concentration P region 23b has an overhang of approximately 0.65 μm.

その後、窒化膜26を再ひパターニングして、縦形’N
 P N Trにおいてはベースとコレクタ・コンタク
トの間に、縦形PNPTrにおいてはエミッタの周囲に
酸化膜29を6000人形成する。そして、縦形NPN
Tr[おいてはコレクタ・ウオール30を形成する。そ
れから、イオン注入により低濃度p−領域31を縦形N
 P N Trにおいてはベース領域、&形PNPTr
においてはコレクタ・コンタクト部に0.4μmの深さ
まで形成する(第3図(D))。
After that, the nitride film 26 is patterned again to form a vertical 'N'
An oxide film 29 of 6,000 layers is formed between the base and collector contact in the P N Tr, and around the emitter in the vertical PNP Tr. And vertical NPN
A collector wall 30 is formed in the Tr. Then, by ion implantation, the low concentration p-region 31 is formed into a vertical N
In P N Tr, the base region, &PNP Tr
In this case, it is formed to a depth of 0.4 μm in the collector contact portion (FIG. 3(D)).

第3図Eにおいては、全面にpoly St 32を2
000人形成し、その土に窒化膜33を600人形成し
ている。そして、フットリソ法により窒化膜33をパタ
ーニング、そしてpoly St 32及びn型エビタ
キンヤル層24を0.1 ltmエツチングする。それ
から、この窒化))9E 33をマスクとして選択酸化
により酸化膜34を1800人形成している。この酸化
膜34は縦形NPNTrにおいてはエミッタとベース間
、縦形PNPTrにおいては、酸化膜29上からコレク
タ・コンタクト部の一部に形成されており、poly 
St 32と酸化膜34の段差は約2000人ついてい
る。
In Figure 3E, poly St 32 is applied 2 times over the entire surface.
000 people formed the soil, and 600 people formed the nitride film 33 on the soil. Then, the nitride film 33 is patterned by foot lithography, and the polySt 32 and n-type epitaquin layer 24 are etched by 0.1 ltm. Then, 1800 oxide films 34 are formed by selective oxidation using the nitrided 9E 33 as a mask. This oxide film 34 is formed between the emitter and the base in the vertical NPNTr, and is formed on a part of the collector contact part from above the oxide film 29 in the vertical PNPTr.
The difference in level between the St 32 and the oxide film 34 is about 2,000.

その後、レジスト膜をマスクとして、高龜度計領域35
a 、35b 、35cを0.2 μm (7)深さま
で形成する。35a 、 3sbは縦形1すPlすTr
におけるエミッタおよびコレクタ・コンタクトを各々形
成しており、35 cは縦形P14PTrにおけるベー
ス・コンタクトを形成しでいる。そして、再びイオン注
入により、高濃度p十領域36d。
After that, using the resist film as a mask, the high-accuracy meter area 35
Form a, 35b, and 35c to a depth of 0.2 μm (7). 35a, 3sb are vertical type 1P1Tr
35c forms the base contact in the vertical P14PTr. Then, by ion implantation again, the high concentration p10 region 36d is formed.

3eb 、36Cを形成する。36aは縦形N P N
T rにおける不活性ベースを形成しておシ、ベース抵
抗rbb/を下げる効果を有している。36b。
3eb, forming 36C. 36a is vertical type N P N
It forms an inert base in T r and has the effect of lowering the base resistance rbb/. 36b.

36cは縦形PNPTrにおけるエミッタ、コレクタ・
コンタクトを各々形成しており、36bと36cは酸化
膜29によって自己整合的に分離されている。また、イ
オン飛程Rpはpoly St 32と酸化膜34の段
差が2000人あるので、酸化膜34直下の高濃度p+
領領域6cは、下方向から持ち上がってきた高濃度P領
域23bとつながり、コレクタ・コンタクトを形成する
。一方、エミッタに形成された高濃度p 領域3.6b
は高濃度P領域23bとつながらないので非常にれシい
n型エピタキ7.ヤル層のベースが自己整合的にできる
。しかも、エミッタ接合の(011面が酸化膜29て覆
われるので、接合容量も極力小さくなっている。
36c is the emitter and collector in the vertical PNPTr.
Contacts are formed respectively, and 36b and 36c are separated by an oxide film 29 in a self-aligned manner. In addition, since the ion range Rp has a step difference of 2000 between the poly St 32 and the oxide film 34, the high concentration p+ directly below the oxide film 34
The region 6c is connected to the high concentration P region 23b raised from below to form a collector contact. On the other hand, high concentration p region 3.6b formed in the emitter
7. is not connected to the high concentration P region 23b, so the n-type epitaxy is very weak. The base of the layer is created in a self-consistent manner. Moreover, since the (011 plane) of the emitter junction is covered with the oxide film 29, the junction capacitance is also minimized.

(第3図(F))。(Figure 3 (F)).

第3図Gにおいては、へl電極配線37を形成して・縦
形NPN 1°rと縦形PNPTrが完成している。
In FIG. 3G, a vertical NPN 1°r and a vertical PNPTr are completed by forming the electrode wiring 37.

以上述べてきたように本発明のホ11[形N P N 
Trと縦形PNP’l”rの一体化41′う造を用いん
半;17it体集積回路は、縦形N P N Txにお
いては素子間分画酸化膜、ベース・コレクタ間分子41
1酸化膜、エミッタ・ベース間分肉1酸化11々を形成
することに」、す、周波数特性を悪ぐする要因となって
いる接合界11ニーのうち、側面における接合容量を極
力小さくし、高速化を図ることができる。寸メこ、高め
度p1−領域(不活性ベース)がエミッタ端部より自己
整合的に形成されるので、ベース抵抗rbblを小さく
し、更に高速化を図ることが可能となる。捷だ縦形PN
PTrにおいては縦形i’J P N ’I’rの構造
、プロセスと全く同一工程で製造することか可能なので
、プロセス的には全く増えることがなく、従来チャネル
・ストッパーとして使われていた高濃度耐領域を縦形P
NPTrの島領域に形成することにより、素子量分#i
酸化膜形成終了後はかなり上方向に持ち土がってくる。
As described above, the present invention has the following advantages:
Integration of Tr and vertical PNP'l''r 41' 17-bit integrated circuit uses a 41'structure; in vertical N P N
By forming the 1 oxide film and the emitter-base thickness 1 oxide 11, we minimized the junction capacitance on the sides of the junction field 11 knee, which is a factor that deteriorates the frequency characteristics, as much as possible. It is possible to increase the speed. Since the relatively high p1- region (inactive base) is formed in a self-aligned manner from the emitter end, it is possible to reduce the base resistance rbbl and further increase the speed. Vertical PN
PTr can be manufactured in exactly the same process as the structure and process of vertical i'J P N 'I'r, so there is no increase in the process, and the high concentration that was conventionally used as a channel stopper can be manufactured. The resistance area is vertical P
By forming it in the island region of NPTr, the element amount #i
After the oxide film is formed, the soil will be lifted upwards considerably.

また、やや深い酸化膜(ベース・コレクタ間ば化膜)と
浅い酸化膜(エミッタ・ベース間酸化膜)の段差を利用
して菌濃度p 領域をイオン注入により形成するので、
やや深い酸化膜の直下には高濃度p+領領域形成されな
く、浅い酸化膜の直下には高濃度耐領域が形成されるの
で、高濃度耐領域はやや深い酸化膜によって自己整合的
に分離され、岐形P zIIPTrにおけるエミッタと
コレクタ・コンタクトが形成される。巣に、?I# l
/’1 m化膜の段差をオリ用して高kkp”−領域を
形成しているので自己整合的に薄い酸化膜の直下は深く
、コレクタコンタクト部直下は浅く形成されることにな
る。この薄い酸化膜直下に形成された高濃度耐領域は、
縦形PNPTrの島領域に形成されて上方向に持ち土が
ってきた高濃度耐領域とつながり、コレクタ・コンタク
トを取ることが可能となる。一方、エミッタ直下に形成
された高濃度p+tt域は」二方向に持ち土がってきた
高濃度耐領域とつながらないので非常に短いベース幅を
自己整合的に形成することができ、縦形NPNTrと同
程度の高周波特性が得られ、非常に高速化を図ることが
できる。また、電流が縦方向に流れるので、横形Pin
P’rrのように大きな面積にならず、縦形N P N
 ’l″rとほぼ同程度の大きさで形成できるので非′
帛に高密度化を図ることができる。
In addition, the bacteria concentration p region is formed by ion implantation by utilizing the step between a slightly deeper oxide film (base-collector interspace film) and a shallower oxide film (emitter-base interlayer oxide film).
The high concentration p+ region is not formed directly under the slightly deep oxide film, but the high concentration resisting region is formed directly under the shallow oxide film, so the high concentration resisting region is separated by the slightly deeper oxide film in a self-aligned manner. , emitter and collector contacts in the branched P zIIPTr are formed. In the nest? I#l
Since the high kkp''-region is formed by using the step of the /'1m film, the area directly under the thin oxide film is formed deep in self-alignment, and the area directly under the collector contact portion is shallow. The high concentration resistant region formed directly under the thin oxide film is
It is connected to the high concentration resistant region formed in the island region of the vertical PNPTr and lifted upward, making it possible to make collector contact. On the other hand, the high-concentration p+tt region formed directly under the emitter is not connected to the high-concentration resistance region that has been lifted in two directions, so a very short base width can be formed in a self-aligned manner, which is the same as that of a vertical NPN Tr. It is possible to obtain high frequency characteristics of a certain degree, and it is possible to achieve extremely high speeds. Also, since the current flows vertically, the horizontal Pin
It does not have a large area like P'rr, but is vertical N P N
Since it can be formed with approximately the same size as 'l''r,
It is possible to achieve high density.

発明の効果 以上のように、本発明の縦形1iPNTrと縦形PN’
PTrの一体化構造は、縦形i(Pi4 Tr、 ii
<形PNPTr両方とも非常に高周波特性に保れ、高速
でしかも高密度であるので、IC,LSIの設剖におい
ても役割が容易でしかも回路特性を子分に発揮すること
ができるので、今後の超LSI化に大きく寄与し、工業
的価値の非常に高いものである。
Effects of the Invention As described above, the vertical 1iPNTr and vertical PN' of the present invention
The integrated structure of PTr is vertical i (Pi4 Tr, ii
<Both types of PNPTr can maintain very high frequency characteristics, are high speed, and have high density, so they can easily play a role in the anatomy of ICs and LSIs, and can demonstrate their circuit characteristics to their subordinates, so they will be useful in the future. It has greatly contributed to the development of VLSI and has extremely high industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本出願人がすでに提案した絶縁分離方式による
縦形N’ P N Trと横形P1〜P Trとの一体
化構造断面図、第2図は本発明の縦形NPNTrと縦形
PNPTrの一体化構造断面図、第3図A〜Gは本発明
の一実施にかかる半導体集積回路の要部製造工程図であ
る。 3.3“a、3“b、23.23a 、23b −・−
・・・高濃度P領域、6,5“、28・・・・・・素子
間分離酸化膜、6,6“a、6“b、29・・・・・・
ベース・コレクタ間分離酸化膜、10,10“、34・
・・・・・エミッタ・ベース間分版酸化膜、12゜12
”a、12”b、36a 、36b 、、、96c *
**+・・高濃度耐領域。
FIG. 1 is a sectional view of an integrated structure of a vertical N'P N Tr and horizontal P1 to P Tr using the insulation isolation method already proposed by the applicant, and FIG. 2 is a cross-sectional view of an integrated structure of a vertical NPNTr and a vertical PNPTr of the present invention. Structural cross-sectional views and FIGS. 3A to 3G are manufacturing process diagrams of essential parts of a semiconductor integrated circuit according to one embodiment of the present invention. 3.3"a, 3"b, 23.23a, 23b ---
... High concentration P region, 6,5", 28...... Inter-element isolation oxide film, 6,6"a, 6"b, 29...
Base-collector isolation oxide film, 10, 10", 34.
...Emitter-base separation oxide film, 12°12
"a, 12"b, 36a, 36b,,,96c*
**+・・High concentration resistance area.

Claims (3)

【特許請求の範囲】[Claims] (1)第1の絶縁膜により素子間分離されたバイポーラ
半導体集積回路であって、前記第1の絶縁膜と第2の絶
縁膜との間にコレクタ・コンタクトが一 形成され、前記第1の絶縁膜力3の絶縁膜との1bJに
ベースコンタクト部が形成され、エミッタの111j面
のすべての領域が少くとも前記第2の絶縁膜及び前記第
3の絶縁膜を含む絶縁被膜により覆われ、かつ前記第3
の絶縁膜下部で深く、前記ベースコンタクト部で浅く、
シかも連続して形成されている不活性ベースを有してい
る縦形l→PN)ランリスタと、エミッタが前記ベース
コンタクト部下の不活性ベースと同一濃度、同−深さに
形成され、かつ該エミッタの側面が前記第2の絶縁刀莫
と同−深さの第4.第5の絶縁膜によ!ll覆われ、前
記エミッタおよびコレクタコンタクト部は前記第4の絶
縁膜により分p+ttされ、前記第1.第4の絶縁膜と
の間に前記コレクタコンタクトが形成され、前記第1.
第6の絶縁膜との間にベースコンタクト部が形成されて
いる縦形PNP )ランリスタを有していることを特徴
とする半導体集積回路。
(1) A bipolar semiconductor integrated circuit in which elements are isolated by a first insulating film, wherein a collector contact is formed between the first insulating film and the second insulating film, and a collector contact is formed between the first insulating film and the second insulating film; A base contact portion is formed at 1bJ with an insulating film having an insulating film strength of 3, and the entire region of the 111j plane of the emitter is covered with an insulating film including at least the second insulating film and the third insulating film, and the third
deep at the bottom of the insulating film, shallow at the base contact part,
A vertical (l→PN) run lister having an inert base formed continuously in a continuous manner, and an emitter formed at the same concentration and depth as the inert base under the base contact, and the emitter The fourth insulating blade has the same depth as the second insulating blade. By the fifth insulating film! The emitter and collector contact portions are covered by the fourth insulating film p+tt, and the emitter and collector contact portions are covered by the first insulating film. The collector contact is formed between the fourth insulating film and the first insulating film.
1. A semiconductor integrated circuit comprising a vertical PNP run lister in which a base contact portion is formed between the semiconductor integrated circuit and the sixth insulating film.
(2)第1.第4の絶縁膜との間に、前記第1.第4の
絶縁膜よりも浅くかつ前記第4の絶縁膜に接して形成さ
れた第6の絶縁膜を有し、コレクタコンタクト部は前記
第6の絶縁j膜下で深いことを特徴とする特許請求範囲
第1項記載の半導体集積回路。
(2) First. between the fourth insulating film and the first insulating film. A patent characterized in that the sixth insulating film is shallower than the fourth insulating film and is formed in contact with the fourth insulating film, and the collector contact portion is deep under the sixth insulating film. A semiconductor integrated circuit according to claim 1.
(3)縦形N P N l・ランリスタ及び縦形PNP
 トランジスタの一体化製造工程であり、第1の絶縁膜
によシ素子間分囲tされ、縦形PNP、縦形N’ P 
Nトランジスタをそれぞれ形成する第1.第2の島領域
を形成し、前記第1の島領域全体にP型半専体領域を形
成する工程と、前記第2の島領域内においてはベースと
コレクタコンタクト部間に第2の絶縁膜、エミッタとペ
ースコンタク]・部間に第3の絶縁膜、かつ前記第1の
m、領域内においてd、エミッタの周囲に第4.第5の
絶縁J模、エミノタとコレクタコンタクト部間と、前記
第4の絶縁膜に接して、第6の絶縁膜を形成する工程と
、前記第2の島領域においては前記第3の絶縁膜下部は
深く、前記ベースコンタクト部は浅く、しかも連続して
不活性ベースを形成し、前記第1の島領域においてはエ
ミッタ領域及びコレクタコンタクト部は前記第2島領域
のベースコンタクトと同じ深さ、同じ濃度で形成し、前
記コレクタコンタクト部は前記第6の絶縁膜下部では他
の部分より深く、形成する工程とを含むことを特徴とす
る半導体集積回路の製造方法。
(3) Vertical N P N l / Run lister and vertical PNP
This is an integrated manufacturing process for transistors, in which the first insulating film divides the transistors into vertical PNP and vertical N'P transistors.
The first.N transistors are formed respectively. forming a second island region and forming a P-type semi-dedicated region over the entire first island region, and forming a second insulating film between the base and the collector contact portion in the second island region; , emitter and pace contact] - A third insulating film between the parts, and a fourth insulating film in the first m and d regions, and a fourth insulating film around the emitter. forming a sixth insulating film between the emitter and the collector contact portion and in contact with the fourth insulating film; and forming a sixth insulating film in the second island region; The lower part is deep, and the base contact part is shallow and continuous to form an inactive base, and in the first island region, the emitter region and the collector contact part have the same depth as the base contact of the second island region. A method for manufacturing a semiconductor integrated circuit, comprising the step of forming the collector contact portion at the same concentration, and forming the collector contact portion deeper below the sixth insulating film than other portions.
JP57196983A 1982-11-10 1982-11-10 Semiconductor integrated circuit and its manufacture Pending JPS5987851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57196983A JPS5987851A (en) 1982-11-10 1982-11-10 Semiconductor integrated circuit and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57196983A JPS5987851A (en) 1982-11-10 1982-11-10 Semiconductor integrated circuit and its manufacture

Publications (1)

Publication Number Publication Date
JPS5987851A true JPS5987851A (en) 1984-05-21

Family

ID=16366878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57196983A Pending JPS5987851A (en) 1982-11-10 1982-11-10 Semiconductor integrated circuit and its manufacture

Country Status (1)

Country Link
JP (1) JPS5987851A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521726A (en) * 1991-06-27 1993-01-29 Samsung Electron Co Ltd Bicmos device and manufacture thereof
US5369042A (en) * 1993-03-05 1994-11-29 Texas Instruments Incorporated Enhanced performance bipolar transistor process
JP2003017577A (en) * 2001-07-04 2003-01-17 Denso Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521726A (en) * 1991-06-27 1993-01-29 Samsung Electron Co Ltd Bicmos device and manufacture thereof
US5369042A (en) * 1993-03-05 1994-11-29 Texas Instruments Incorporated Enhanced performance bipolar transistor process
JP2003017577A (en) * 2001-07-04 2003-01-17 Denso Corp Semiconductor device

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