JPS5987846A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPS5987846A JPS5987846A JP19711382A JP19711382A JPS5987846A JP S5987846 A JPS5987846 A JP S5987846A JP 19711382 A JP19711382 A JP 19711382A JP 19711382 A JP19711382 A JP 19711382A JP S5987846 A JPS5987846 A JP S5987846A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- frame
- resin
- semiconductor device
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000008188 pellet Substances 0.000 abstract description 19
- 239000011347 resin Substances 0.000 abstract description 19
- 229920005989 resin Polymers 0.000 abstract description 19
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はリードフレームのベッドに搭載する半導体ペ
レットが大きくなった場合に発生するモールド樹脂のひ
び割れを防止す木ようにした半導体装置及びその製造方
法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a wood-shaped semiconductor device that prevents cracks in mold resin that occur when semiconductor pellets mounted on the bed of a lead frame become large, and a method for manufacturing the same. Regarding.
従来より半導体装置に用いられるリードフレームにはエ
ツチングフレーム及びプレスフレームの２種類がある。There are two types of lead frames conventionally used in semiconductor devices: etching frames and press frames.
このようなリードフレームにおいては半導体ペレットが
搭載されるベッド部とインナーリード部との厚さが同じ
に構成されている。In such a lead frame, the bed portion on which the semiconductor pellet is mounted and the inner lead portion have the same thickness.
第１図において、従来から使用されているリードフレー
ムに半導体ペレットを固着して樹脂封止を行なった場合
、リードフレーム１または半導体ペレット２と樹脂３と
の間には半導体ペレット固着時、ビンディングワイヤ接
続時、樹脂封止時等の熱工程による歪が発生するという
欠点がある。例えば、樹脂封止が１７０℃前後の雰囲気
で行なわれた後、鉄−ニッケルを主成分とするリードフ
レーム（熱膨張係数５〜６Ｘ６
１０ ）と半導体ペレツ）（Ｓｉ熱膨張係数５〜６ｘ
１０−’ ）と樹脂（エポキシ系熱膨張係数２．Ｉ Ｘ
１０−’ ）はそれぞれ冷却され常温になると塾・う
５蟻率の違いからそれぞれ歪をうける。そのＩｉ”ｒｊ
果、設も弱い樹８げに（場合により半導体ペレット自体
）クラックが発生して、このクラック部より水分等が侵
入し半導体ペレット内に異常を発生する原因となってい
る。また、このような問題は従来半導体ペレットサイズ
が小さい８合に：ま将に間；１になら々いが近年素子数
の増加に伴ない、ペレットサイズが大きくなった為に新
たに問題となって来ている。In FIG. 1, when a semiconductor pellet is fixed to a conventionally used lead frame and sealed with resin, there is a binding wire between the lead frame 1 or the semiconductor pellet 2 and the resin 3 when the semiconductor pellet is fixed. There is a drawback that distortion occurs due to thermal processes such as during connection and resin sealing. For example, after resin sealing is performed in an atmosphere around 170°C, a lead frame (thermal expansion coefficient of 5 to 6 x 6 10 ) mainly composed of iron-nickel and semiconductor pellets (Si thermal expansion coefficient of 5 to 6 x
10-') and resin (epoxy thermal expansion coefficient 2.I
10-') are each cooled to room temperature, and each undergoes distortion due to the difference in the cram rate and the rate of growth. That Ii”rj
As a result, cracks occur in the weak wood (in some cases, the semiconductor pellet itself), and moisture and the like enter through the cracks, causing abnormalities within the semiconductor pellet. In addition, this kind of problem has traditionally been as small as the 8th semiconductor pellet size, but it has become a new problem as the pellet size has increased in recent years as the number of devices has increased. It's coming.
この発明は上記の点に鑑みてなされたもので、その目的
はリードフレームで発生する樹脂クラックやベレットク
ランクを従来のフレーム製造工哩を変更することなくフ
レーム形状の変更のみで梅脂クラックやペレットクラッ
クを防止することができる半導体装置及びその製造方法
を提供することにある。This invention was made in view of the above points, and its purpose is to eliminate resin cracks and pellet cranks that occur in lead frames by simply changing the frame shape and eliminating resin cracks and pellet cranks that occur in lead frames. An object of the present invention is to provide a semiconductor device that can prevent cracks and a method for manufacturing the same.
リードフレームのペツ゛ド１１３のａＥ面な凸状に−［
ることによりＭＬｔ１１旨クラックやペレットクランク
の発生を防止している。-[
This prevents the occurrence of MLt11 cracks and pellet cranks.
以下、図面を参照してこの発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第２図はこの発明に係る半導体装置を示す断面図である
。同図において、１１はリードフレームのベッド部で、
このベッド部１ノの底部には凸部１２が形成されている
。そして、上記ベッド部１１には半導体ペレット１３が
マウントされており、この半導体ペレット１３とインナ
ーリード１４とはワイヤ１５ζ二より接続されている。FIG. 2 is a sectional view showing a semiconductor device according to the present invention. In the same figure, 11 is the bed part of the lead frame,
A convex portion 12 is formed at the bottom of this bed portion 1. A semiconductor pellet 13 is mounted on the bed portion 11, and the semiconductor pellet 13 and the inner lead 14 are connected by wires 15ζ2.
さらに、上記半導体ペレット１３及びその周辺部は樹脂
１６によりモールドされる。このようにリードフレーム
のベッド部の底面に凸部を形成するよう：二したので、
樹脂モールド時（；、樹脂が収縮するが、ベッド部１１
上面側ではペレット側壁により収縮が押えられ、またベ
ッド部１１の下面側では凸部側壁により収縮が押えられ
る。すなわち、樹脂の収縮はベッド１１の上、下面でバ
ランスがとれた状態になり、従来、リードフレームのベ
ッド部の下側外周で発生していた樹脂クラックを防止さ
せることができる。またこの樹脂クラックをより良く防
止するために、凸部１２の形状寸法は、ペレット１３と
同−Ｃ二し、ベッド１１を中心に対称的形態をとること
が好ましい。Further, the semiconductor pellet 13 and its surrounding area are molded with resin 16. In order to form a convex part on the bottom of the bed part of the lead frame like this:
During resin molding (;, the resin shrinks, but the bed part 11
On the upper surface side, shrinkage is suppressed by the pellet side wall, and on the lower surface side of the bed portion 11, shrinkage is suppressed by the convex side wall. That is, the shrinkage of the resin is balanced between the upper and lower surfaces of the bed 11, and resin cracks that conventionally occur at the lower outer periphery of the bed portion of the lead frame can be prevented. Further, in order to better prevent resin cracks, it is preferable that the shape and dimensions of the convex portion 12 be the same as those of the pellet 13, and be symmetrical with respect to the bed 11.
次に、この発明に係る半導体装置の製造方法を第３図を
用いて説明する。第３図（Ａ）ζ二おいて、２１は加工
されていないＦｅ−Ｎｉ系フレームである。まず、この
フレーム２１の表面及び裏面にレジスト２２を塗布する
。このレジスト２２を露光現像して第３図（Ｂ）に示す
ようにパターニングする。この場合ζ二おいてフレーム
２１の表面のレジスト２２１よりもフレーム２１の裏面
のレジスト２２２の方を小さくしておく。次に、第３図
（Ｃ）に示すように通常のエツチング液にて上６己レジ
スト２２をマスクにしてエツチングする。ここで、レジ
スト２２１よりもレジスト２２２を小さくしているので
、ベッド部２３の底面に凸部が形成される。また、２４
はインナーリード、２５はアウターリードとなるフレー
ムである。Next, a method for manufacturing a semiconductor device according to the present invention will be explained with reference to FIG. In FIG. 3(A) ζ2, 21 is an unprocessed Fe-Ni frame. First, a resist 22 is applied to the front and back surfaces of the frame 21. This resist 22 is exposed and developed to be patterned as shown in FIG. 3(B). In this case, the resist 222 on the back side of the frame 21 is made smaller than the resist 221 on the front side of the frame 21 at ζ2. Next, as shown in FIG. 3(C), etching is performed using a normal etching solution using the upper resist 22 as a mask. Here, since the resist 222 is made smaller than the resist 221, a convex portion is formed on the bottom surface of the bed portion 23. Also, 24
2 is a frame that serves as an inner lead and 25 as an outer lead.
なお、上記実施例においてはフレームとしてＦｅ−Ｎｉ
系合金を用いたが、これ（二限らずＣｕ系等でも強度に
問題なければさしつかえない。In addition, in the above embodiment, the frame is made of Fe-Ni.
Although a Cu-based alloy was used, it is also possible to use a Cu-based alloy as long as there is no problem with strength.
以上詳述したようにこの発明によれば、リードフレーム
のベッド部の底面に凸部を形成したので、樹脂封止した
後樹脂クラックの発生を防止することができる。As detailed above, according to the present invention, since the convex portion is formed on the bottom surface of the bed portion of the lead frame, it is possible to prevent resin cracks from occurring after resin sealing.
第１図は従来の半導体装置を示す図、第２図はこの発明
の一実施例を示す半導体装置を示す図、第３図はこの発
明の一実施例を示す半導体装置の製造方法を示す図であ
る。
２１・・・フレーム、２２・・・レジスト、２３・・・
ベッド部、２４・・・インナーリード、２５・・・アウ
ターリード。1 is a diagram showing a conventional semiconductor device, FIG. 2 is a diagram showing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. It is. 21... Frame, 22... Resist, 23...
Bed part, 24...inner lead, 25...outer lead.
Claims (2)
たことを特徴とする半導体装置。(1) A semiconductor device characterized in that the bottom surface of the bed portion of the lead frame is convex.
布するレジスト塗布工程と、上記レジスト塗布工程によ
り塗布されたレジストのうちベッド部予定領域に塗布さ
れたレジストを表面より裏面を小さくパターニングする
ノ９ターニングニオ呈と、上記パターニング工程により
パターニングされたレジストをマスクにして上記フレー
ム部材をエツチングする工程とを具備したことを特徴と
する半導体装置の製造方法。(2) A resist coating step in which resist is applied to the front and back surfaces of the frame member, and a turning step in which the resist applied in the area intended for the bed portion is patterned to be smaller on the back surface than the front surface. 1. A method for manufacturing a semiconductor device, comprising the steps of etching the frame member using a resist patterned in the patterning step as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19711382A JPS5987846A (en) | 1982-11-10 | 1982-11-10 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19711382A JPS5987846A (en) | 1982-11-10 | 1982-11-10 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5987846A true JPS5987846A (en) | 1984-05-21 |
Family
ID=16368941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19711382A Pending JPS5987846A (en) | 1982-11-10 | 1982-11-10 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5987846A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0249834A2 (en) * | 1986-06-20 | 1987-12-23 | Siemens Aktiengesellschaft | Production of fine structures for the establishment of contacts on semi-conductors |
-
1982
- 1982-11-10 JP JP19711382A patent/JPS5987846A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0249834A2 (en) * | 1986-06-20 | 1987-12-23 | Siemens Aktiengesellschaft | Production of fine structures for the establishment of contacts on semi-conductors |
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