JPS5986332A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the input electrostatic dielectric strength by inserting a PNP transistor (TR) whose emitter is connected to an input terminal, whose collector is connected to a ground terminal and whose base is connected to the input terminal via a resistor. CONSTITUTION:When a positive electrostatic voltage is applied to an input terminal 1, a collector-base junction of a TR8 of a electrostatic destruction preventing circuit provided freshly is biased reversely, and a reverse bias leakage current flows to a ground terminal 3 via a base-collector junction. Then, the said leakage current is increased with the increase in the voltage at the input terminal 1, and when the potential drop of the resistor 9 by the current reaches a forward threshold voltage between base and emitter of the TR8, the TR8 is conductive, and most of the electrostatic discharge current flowing to the input terminal flows to a ground terminal as an emitter-collector current at the conductive state of the TR8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having an electrostatic breakdown prevention circuit.

In recent years, integrated circuits, large-scale integrated circuits, and very large-scale integrated circuits have been used in extremely large quantities in the electronics industry.
When handling these parts, damage due to static electricity often occurs, which has become a major problem.Moreover, in recent years, in order to increase the density of semiconductor integrated circuits and increase the speed of switching, circuit components have become finer. Dimensional and shallow (・
Due to the bonded configuration, static box damage is more likely to occur.

For example, in the conventional circuit shown in Figure 1, if a negative electrostatic voltage is applied to the input terminal 1 with respect to the ground terminal 3, the reflected wave generated by the mismatch between the integrated circuits will be negative. In order to suppress the voltage of 5 (hereinafter referred to as input game) (abbreviated as SBD) is preserved from static electricity,
When a voltage is applied to the input terminal 1, the above input clamp °5BD
4 has no effect on the 18', B effect on the input circuit, and the input clamp 5I3D4 will be destroyed if it is separated from the input circuit.

This will be explained in detail below.

In the conventional circuit (not shown in Figure 1), for the ground terminal 3,
Negative static electricity on input terminal 1 5. When pressure is applied, a discharge current of static electricity flows through the input clamp 8BD4 in the forward direction, so that the input circuit is protected from static electricity.

However, on the contrary, there is a grounding terminal 3 (・ means input bad when a large positive electrostatic voltage is applied to input terminal 1 with respect to power supply terminal 2) SBD 5 and input clamp 5
BD4 becomes extremely reverse biased. Here, in order to reduce the input leakage current during normal operation of the circuit and to increase the input withstand voltage, the manual clamp S'BD4 normally uses an SBD with a guard ring structure, and its withstand voltage is about 30 volts. However, In order to prevent the threshold voltage of the circuit from becoming low, input voltage may be low (・
5lll), and with the same structure area, the forward voltage is low (and it is constructed with an SBD without a guard ring).

Therefore, the breakdown voltage of the SBD 5 is low, about 15V.

In such an integrated circuit structure, when a positive electrostatic voltage is applied to the input terminal 1 as described above, the input gate 8BD5
breaks down violently, and the electrostatic charge is discharged from the input terminal 1, through the input gate 5BD5, through the input resistor 6, to the power supply terminal 2, and from the input gate 5BD5 to the base of the next stage transistor 7. At this time, the electrostatic voltage applied to the input is high (if the input is high, the input is automatically bad).8 The electrostatic charge discharge current flowing in the opposite direction through BD5 becomes thick. In extreme cases, even the input clamp 5BD4 may be destroyed.

In order to improve this, it is possible to increase the area of the input IHD5, but increasing the area of the 8BD5 means increasing the capacitance of its diode, and in the case of a multi-input circuit configuration, the following The capacitance at the base point of the stage transistor 7 increases, which leads to a decrease in the switching speed of the circuit, which is undesirable (also, the input is bad).
Increasing the 0 area will lead to an increase in chip area/area, which is extremely disadvantageous to achieving high integration density. Moreover, it is not possible to expect much effect from increasing this area.

As mentioned above, in the conventional circuit as shown in Fig. 1, when a positive electrostatic voltage is applied to the input terminal with respect to the ground terminal or the power supply terminal, the input will go out.
It has a major drawback that the input circuit elements of 1 are easily destroyed.

The present invention has been made in view of these circumstances, and an object of the present invention is to provide a semiconductor integrated circuit equipped with an electrostatic breakdown prevention circuit that is effective against positive electrostatic voltage applied to an input terminal. do.

According to the present invention, the PNI transistor has an emitter connected to an input terminal, a collector connected to a ground terminal or a power supply terminal, and a base connected to the input terminal via a resistor, A semiconductor integrated circuit with improved width can be obtained.

Next, the present invention will be explained in detail according to embodiments thereof and with reference to the drawings.

FIG. 2 is a circuit connection diagram showing one embodiment of the present invention. The circuit car of the present invention is different from the conventional circuit shown in FIG.
This involves newly inserting a PNP transistor whose emitter is connected to the input terminal, whose collector is connected to the ground terminal, and whose base is connected to the input terminal via a resistor.

The operation of the static breakdown prevention circuit of the present invention will be described below.

If a positive electrostatic voltage is now applied to the input terminal 1, the collector and base junction of the transistor 8 of the electrostatic breakdown prevention circuit newly added according to the present invention becomes reverse biased, and the reverse bias leakage current flows through the resistance. 9-base-collector junction to the ground terminal 3. Next, as the voltage at the input terminal 1 increases, the leakage current increases, and when the potential drop force of the resistor 9 due to the current increases and the forward threshold voltage between the base and emitter of the transistor 8 is reached, the transistor 8 Most of the electrostatic discharge current that has flowed into the conductive input terminal flows out to the ground terminal as emitter and collector current when the transistor 8 is in the conductive state.

Here, if the transistor 8 is considered only for the purpose of preventing electric current t+a, it is desirable to open the base.In this case, in the normal operating state of the semiconductor integrated circuit (when the input terminal becomes high level, It is assumed that if any amount of leakage current flows through the base-collector junction of the transistor 8, a collector current that is hFE times the leakage current will flow. In normal operation, when a high-level voltage is applied to the input, the high-level input current ■□□ increases, which is undesirable.

On the other hand, if a resistor is not connected between the base and emitter of transistor 8 as in the circuit of the present invention, some reverse bias will be applied to the base-collector junction of transistor 8 when a high level is applied to the input terminal. Even if a leakage current occurs, the potential drop of the resistor through which the current flows reaches the forward bias voltage between the base and emitter of the transistor 8. The transistor 8 will not become conductive, especially when a high level input current occurs. (・.In other words, regarding the function of the above-mentioned resistor (・), regarding the transistor collector-ememic breakdown voltage BVcE, BVcEO<B
vc), commonly known as R, is also evident from L.

In the above explanation, the case where the collector of the PNP transistor 8 for preventing electrostatic damage is connected to the ground terminal 3 has been described, but as shown in FIG. 3, the PNP transistor for preventing electrostatic damage
It goes without saying that even when the collector of the NP transistor 8' is connected to the power supply terminal 2, the transistor 8' similarly exhibits the effect of preventing electrostatic damage.

As described above, according to the circuit of the present invention, it is possible to obtain a semiconductor integrated circuit with extremely high electrostatic withstand voltage without substantially increasing the number of elements or chip size.

[Brief explanation of the drawing]

FIG. 1 is a circuit connection diagram showing a conventional semiconductor integrated circuit input section, FIG. 2 is an input circuit connection diagram showing one embodiment of the present invention, and FIG. 3 is an input circuit connection diagram showing another embodiment of the present invention. It is a diagram. In the figure, 1"...B input terminal, 2
...Power terminal, 3...Ground terminal, 4,
5...5BI), 6,9...Resistance, 7
, 8, 8'...transistors. V 1st eye 22nd interval 3rd eye

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising a PNP transistor having an emitter connected to an input terminal, a collector connected to a ground terminal or a power supply terminal, and a base connected to the input terminal via a resistor.