JPH035686B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having an electrostatic breakdown prevention circuit.

BACKGROUND OF THE INVENTION In recent years, integrated circuits, large-scale integrated circuits, and ultra-large-scale integrated circuits have been used in extremely large quantities in the electronics industry, but when handling these components, damage due to static electricity often occurs, which has become a serious problem. Moreover, in order to increase the integration density of semiconductor integrated circuits and increase the speed of switching,
As circuit components become smaller in size and have shallower junction structures, electrostatic damage is becoming more likely to occur.

For example, in a conventional circuit as shown in Figure 1,
When a negative electrostatic voltage is applied to the input terminal 1 with respect to the ground terminal 3, in order to suppress the negative voltage of the reflected wave caused by the mismatch between the integrated circuits, The input gate shot key barrier diode 5 (hereinafter referred to as input gate SBD) is protected from static electricity by the input clamp shot key barrier diode 4 (hereinafter referred to as input clamp SBD) connected between the , when a positive electrostatic voltage is applied to input terminal 1 with respect to ground terminal 3 or power supply terminal 2, the input clamp
SBD4 has almost no protective effect on the input circuit, and the input gate SBD5 or, in extreme cases, even the input clamp SBD4 will be destroyed.
This will be explained in detail below.

In the conventional circuit shown in Fig. 1, when a negative electrostatic voltage is applied to the input terminal 1 with respect to the ground terminal 3, the static electricity discharge current flows through the input clamp SBD4 in the forward direction, so that the input circuit is not affected by the static electricity. protected from

However, on the contrary, if a large positive electrostatic voltage with respect to the ground terminal 3 or the power supply terminal 2 is applied to the input terminal 1, the input gate SBD5 and the input clamp SBD4 will be in an extremely reverse biased state. Here, the normal input clamp SBD4 has a guard ring structure to reduce the input leakage current during normal operation of the circuit and to increase the input withstand voltage.
SBD is used and its withstand voltage is about 30 volts. However, in order to prevent the threshold voltage of the circuit from becoming low, the input gate SBD5 needs to be an SBD with a low forward voltage, and is constructed of an SBD with a low forward voltage and no guard ring in the same configuration area. Therefore, the breakdown voltage of the input gate SBD5 naturally becomes low and becomes about 15V.

In such an integrated circuit structure, when a positive electrostatic voltage is applied to the input terminal 1 as described above, the input gate SBD5 breaks down violently, and the electrostatic charge is transferred from the input terminal 1 to the input gate SBD5 and the input terminal 1. It is discharged through the pull-up resistor 6 to the power supply terminal 2, or from the input gate SBD5 to the base of the next stage transistor 7. At this time, if the electrostatic voltage applied to the input is high, the input gate SBD will naturally
The electrostatic charge discharge current flowing in the opposite direction through SBD5 becomes large and the input gate SBD5 is destroyed. In extreme cases, even the input clamp SBD4 may be destroyed.

In order to improve this, it is possible to increase the area of input gate SBD5, but increasing the area of SBD5 means increasing the capacitance of its diode, and in the case of a multi-input circuit configuration, the following This increases the capacitance at the base point of the stage transistor 7, which undesirably leads to a decrease in the switching speed of the circuit. Furthermore, increasing the area of the input gate SBD4 increases the chip area, which is extremely disadvantageous for achieving high integration density. Moreover, it is not possible to expect much effect from increasing this area.

As mentioned above, in the conventional circuit shown in Figure 1, when a positive electrostatic voltage is applied to the input terminal with respect to the ground terminal or power supply terminal, the input gate SBD
A major drawback was that input circuit elements such as the input clamp SBD were easily destroyed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit equipped with an electrostatic breakdown prevention circuit that is effective against positive electrostatic voltage applied to an input terminal. .

According to the present invention, in addition to the conventional configuration shown in FIG. 1, the present invention includes a PNP transistor whose emitter is connected to the input terminal, whose collector is connected to the ground terminal or power supply terminal, and whose base is connected to the input terminal via a resistor. Accordingly, it is possible to obtain a semiconductor integrated circuit with significantly improved input electrostatic discharge voltage.

Next, the present invention will be explained in detail according to embodiments using the drawings.

FIG. 2 is a circuit connection diagram showing one embodiment of the present invention. The difference between the circuit of the present invention and the conventional circuit shown in FIG. 1 is that a PNP transistor is newly inserted, the emitter of which is connected to the input terminal, the collector of which is connected to the ground terminal, and the base of which is connected to the input terminal via a resistor. .

The operation of the electrostatic breakdown prevention circuit of the present invention will be described below.

If a positive electrostatic voltage is now applied to the input terminal 1, the collector and base junction of the transistor 8 of the electrostatic breakdown prevention circuit newly added according to the present invention becomes reverse biased, and the reverse bias leakage current flows through the resistance. 9 - Ground terminal 3 via base-collector junction
flows to. Next, as the voltage at the input terminal 1 increases, the leakage current increases, and the resistance 9 due to the current increases.
When the potential drop of transistor 8 reaches the base-emitter forward threshold voltage of transistor 8, transistor 8
When the transistor 8 becomes conductive, most of the electrostatic discharge current that has flowed into the input terminal flows out to the ground terminal as emitter and collector current when the transistor 8 is conductive.

Here, it is desirable to open the base of the transistor 8 only for the purpose of preventing electrostatic discharge damage, but in this case, when the input terminal becomes a high level while the semiconductor integrated circuit is in the normal operating state, the transistor 8
If any leakage current flows through the base-collector junction of , a collector current that is h _FE times the leakage current will flow. That is, leaving the base of the transistor 8 open is undesirable because it leads to an increase in the high-level input current I _IH when a high-level voltage is applied to the input during normal operation of the semiconductor integrated circuit.

Conversely, if a resistor is connected between the base and emitter of transistor 8 as in the circuit of the present invention, some reverse bias leakage current will occur at the base-collector junction of transistor 8 when a high level is applied to the input terminal. Even if this occurs, the transistor 8 will not become conductive until the potential drop across the resistor through which the current flows reaches the forward bias voltage between the base and emitter of the transistor 8, and the high level input current will not particularly increase. In other words, regarding the function of the above resistance, the collector of the transistor
Regarding emitter breakdown voltage BV _CE BV _CEO
<This is clear from the fact that it is commonly known as BV _CER .

In addition, in the above explanation,
Although we have described the case where the collector of the PNP transistor 8 is connected to the ground terminal 3, the same applies to the case where the collector of the PNP transistor 8' for preventing electrostatic discharge damage is connected to the power supply terminal 2 as shown in FIG. It goes without saying that 8' exhibits the effect of preventing electrostatic damage.

As described above, according to the circuit of the present invention, a semiconductor integrated circuit having an extremely high electrostatic breakdown voltage can be obtained without substantially increasing the number of elements or chip size.

[Brief explanation of the drawing]

FIG. 1 is a circuit connection diagram showing a conventional semiconductor integrated circuit input section, FIG. 2 is an input circuit connection diagram showing one embodiment of the present invention, and FIG. 3 is an input circuit connection diagram showing another embodiment of the present invention. It is a diagram. In the figure, 1...signal input terminal, 2...
Power terminal, 3...ground terminal, 4, 5...SBD,
6, 9...Resistor, 7,8,8'...Transistor,
It is.

Claims (1)

[Claims] 1 A PNP transistor whose emitter is connected to the input terminal, whose collector is connected to the ground terminal or power supply terminal, and whose base is connected to the input terminal via a resistor, whose cathode is connected to the input terminal, and whose anode is connected to the ground terminal or power supply terminal. The first shot key
A semiconductor integrated circuit comprising a barrier diode and a second Schottky barrier diode having a cathode connected to the input terminal and an anode connected to the base of the input transistor.