JPS5985128A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To attain the conversion with high accuracy and speed by applying negative feedback control to the maximum power of an integrating circuit in parallel with A/D conversion so as to make the count value coincident with a full scale of the counter. CONSTITUTION:The converter is in the waiting mode at a period T1. A switch 150 is closed to the position (a) at a period T2, and when a current is applied from a capacitor 70 from a variable constant current source 10, a counter 40 starts counting at the same time. When a voltage of the capacitor 70 reaches Vi, an output of a comparator 20 changes from 1 to 0, and the count value in this case is held at a latch circuit 50. A switch 250 is changed over to the position (b) at the same time, and when the voltage of the capacitor 70 reaches a voltage Vref, the output of the comparator 20 changes from 1 to 0, and this change is transmitted to a T-V converting circuit 30. When the value of the counter 40 reaches 2n, this timing is given to the converting circuit 30 and the shift between said timing and the integrating time is compensated. Since the converting operation and calibrating operation are performed at the same time, the conversion is attained with high accuracy and at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides an analog-to-digital converter with a high speed and a high M degree suitable for use in measurement control. Regarding Inu Igital Summer Exchange.

[Prior art]

Analog signal computer processing unit (I2) cJ:
, an analog-to-digital converter (hereinafter referred to as a F A-L converter) is required, and in particular, it is necessary to use an analog-to-digital converter (hereinafter referred to as a F A-L converter), and especially for those that require an S-digital A-D converter. ; is Nagatsuki Jσ.

Conventional counting type A-D converters include //Glu slope method and multi-slope method, but the former inputs the charge voltage of the conode nosa? ii IjEko'U;= L <
Since the bottom of the groove is a counter that measures the time until the Ir is reached, there is a drawback that errors may occur if the capacitor, charging acid flow, and clock frequency of the counter are not constant. Also DU
The AL slope type has capacitors and clock changes a.
Although the improved tl-bandai can eliminate the influence of υ variation, it has the disadvantage that it requires twice the counting time and the conversion speed is slow. The T I (, I P I YOE slope and QUAD slope methods), which are capable of extracting pressure up to full scale adjustment and ono-seso adjustment, further slow down the speed.

Furthermore, since the integral waveform of the multi-slope type changes depending on the input pressure, it is easily affected by the dielectric absorption phenomenon of the capacitor, and since the comparator does not yet perform one-way comparison, it is affected by the operating time of the comparator. The disadvantage was that it was easy to receive.

[Object of the Invention] The object e of the present invention, which has been made based on the above circumstances, is to provide a highly accurate and high-speed counting type analog-to-digital converter.

[Summary of the invention]

In order to achieve such an object, the present invention operates the counting type A and -D converters periodically; Negative feedback control is performed so that the maximum value of the position dividing circuit matches the full scale of the counter.

[Embodiments of the invention] Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1 is a circuit block diagram showing an embodiment of the A, -D converter according to the present invention, and FIG. 2 is an operational diagram showing the main operating parts of the A-1) converter. In FIG. 1, a capacitor 70 that generates an integral pressure has one end grounded and the other end connected to the input terminal of the comparator 20, and also connects a variable constant current through a switch 150. source 10
It is connected to the. The (g) input terminal of the comparator 20 is connected via a switch 250 to an input signal voltage V+ and base thread voltage sources (a) and (f). The output of the comparator 30 is connected to a control circuit 40 and one input signal terminal 30C of a time-voltage conversion circuit (hereinafter referred to as a TV conversion circuit) 30. The control output circuit 40 is a logic circuit (R) that generates a required periodic control signal from a plurality of counter stages operated by the clock CLK and the signals of each counter stage. The signal from the other input terminal 30b of the -V conversion circuit 30 is supplied.A-1]
A binary counter signal and a latch signal are supplied from the suppression circuit 40 to the output launch circuit 50 which holds the converted output data, and outputs and holds the output data N.

The TV conversion circuit 30 is a type of sample and hold circuit, and has two control input signal terminals 30b and 30c and one output signal terminal 30h. Control input signal 30b
The timing corresponds to the full scale of A-D conversion,
In other words, in binary n-bit A-Di conversion, a timing of 2'' period is given. A periodic timing signal is given. That is, the timing when the integrated voltage v0 of the capacitor 70 input to the comparator 20 reaches the reference voltage V r e f is given. j output 30h is 2 of side leg inputs 30b and 30c
Voltage 'I according to the slowness and speed of the two timings
This is H. The polarity of the two inputs 30b and 30c with respect to the output 30h of the T-V converter circuit 30 is determined by negative feedback control of the closed loop formed by the variable constant current source 10→canceller 70→comparator 20. The polarity is such that

The operation of A-1) converter with this different configuration will be explained based on Fig. 2. As shown in the operating waveform diagram in Figure 2, approximately 3 of T+, T2, and T3
It can be divided into , that is, if C corresponds to the heavy pressure of the integrating capacitor 70 which is the basic signal, then T1 is the discharge time,
T2 is integration time T3 is retention time T1 *'
12 + T3 is generated by a counter in the control circuit 40 that operates repeatedly. , 1ψ is also a simple timing generation method, using a count stage with a maximum count of 2 pals, T2 = 2 '' tcLK = T+ - + - T3
---(1) That is, T, 1. +
3 each has a period of 1/2 of Tl.

During the period Tl, the selector switch 150 in FIG.
The pressure V is discharged and is zero. In addition, since the changeover switch 250 is closed to the a side, the input signal voltage V'+ is applied to the input terminal of the monitor 20.
(→There is no Ov at the input terminal, and furthermore, the output of the comparator 20 becomes the "I, TI" level, and the period continues in this state.

Next, in the period Tl, the selector switch 150 is closed to the a side, a constant current flows from the variable constant current source 20 into the capacitor 70, and the terminal voltage Vo increases linearly from OV. Further, at the same time as the switch 150 is switched to the a side, the counter of the control circuit 40 starts counting from O. Charging voltage of capacitor 70 ■. gradually increases and reaches the input signal 'voltage V+, the output of the comparator 20 changes from n, u to n O++, and the output latch circuit 50 receives a latch signal together with the binary counting output from the control circuit 40. The count number at that time is held.

At the same time, the output circuit 40 detects that the output of the comparator 20 changes from n1++ to II OI+, and the changeover switch 2
50 all b I'll, switched to l, V r * I is applied to the (g) input terminal of the divider 20/"L - C,
The output of the comparator 20 returns to the state of °゛1'', while
Capacitor 70 beams! 1. When the pre-voltage ν'6 reaches the reference voltage v1°, the ratio...
The output of the data converter 20 changes from l" to "0" again, and the change signal is transmitted to the control circuit 40 and one of the human input signal terminals 30C of the TV conversion circuit 30. This state is T2 in FIG. /.Next, when the count number of the counter of the control output circuit 49 reaches 2'' (Tl in FIG. 2), this timing occurs when all the control input terminals 30b of the TV conversion circuit 30;! In can be conveyed.

Two input terminals 30b of the TV conversion circuit 30.

The evening/timing input of 30c is Tl in Figure 2, +P2/
With the relationship, that is, 'l'2'< T 2, the integral direct pressure ■
. If the time when V r * t is reached is shorter than the time of 2'' on the counter, the voltage proportional to Tl T2'-ΔT is converted and held as a decrease at the output terminal 30h, and is variable during the period of T3. Set value of output current of constant DC 10 as Δ
'J,'' / T Lower to the value according to 2. Then Tl
period. This correction operation is a negative feedback operation of sampling control. Therefore, after the power is turned on, the difference between Tl and T2' decreases as the operating cycle passes, and T2'=T2 in steady state. In this state, the input voltage V+
Assuming that a count output N corresponding to is obtained, the following relationship holds true, where the capacitor capacitance is C1's constant current value and the clock period is tcLK.

C-V,,t-=I・T2'''VIT(Nl=NtcLx)'I'2,
'rNl is measured almost simultaneously using the same integration circuit;
etc. can be considered constant with no fluctuation.

Therefore, from equation (2), the input/output relationship of AD conversion is as follows.

n N-□・V+ ・・・・・・・・・(3)
V r e f In other words, the output N of the above-mentioned A-D converter is equal to the input ridge pressure V
+ with an accurate gain, and is not affected by fluctuations in the constant current value of the capacitor C1, the clock frequency MLCLK, etc. Moreover, since the calibration operation (T2/→T2 mentioned above) and the conversion 1st operation are performed simultaneously, the required operation time can be shortened and the operation can be made faster.

Furthermore, since the slope of the integrated voltage is always constant and the comparison operating conditions of the comparator are simple and unidirectional comparison, even a simple comparator can easily perform accurate comparison. Furthermore, since the operating waveform of the capacitor is a constant drying waveform, it is possible to enjoy other advantages such as less error caused by the dielectric absorption phenomenon that varies depending on the influence of the previous pressure history when applying the voltage to the capacitor. Examples will be explained in more detail in the first issue.

FIG. 3 is a circuit diagram showing another embodiment of the A-1) converter according to the present invention, and FIG. 4 is an operating waveform diagram of the circuit of FIG. 3.

In Figure 3, items that are the same as those in Figure 1 and have the same effect are given the same symbols.
'1 comparators 20a, 20t), their output holding circuits 4:31, 432, 433, control circuit 40, output latch circuit 50, and TV conversion circuit 30. First, the variable constant source 10 includes P-channel τv10S type field effect transistors (hereinafter referred to as TMO8FET) 102 and 103 that operate as current changeover switches.
1 to 10S transistor pairs 104, 105, 106, 107 for switching the gate upper voltage, a resistor 101 for constant current output, an operational amplifier 108 for constant LD current negative feedback control,
8-■ The fil is generated from the inverter gate 109 for switching the OS switch. The interconnection of each MO8F'J T switch is such that the switching gate 1090 input signal is
When it is '0', MO8FETI 05 and 106 are turned on and MO8FETI 104 and 107 are turned off, allowing current to flow through MOSFET 102, and when it is '0', MOSFETs 104.1.
07 is on, 105 and 106 are off and MO8FETI
The connection and polarity are such that the current is switched to O3. M.O.
The drain of SFET 102 is connected to a parallel circuit of an integrating capacitor 70 and its discharge switch 150. Comparator 20b1 and human power box 7 pressure V+ are added to it The output terminal of the comparator 201 is connected to each input terminal of the comparator 20a.
One of the human powers;
The output of 0a is R and S composed of gates 431 and 432.
7 is connected to the latch input terminal of the output latch circuit 50 via a lip latch. Output lunch time i-5
The flip-flop array constituting 0 has n bits of A
This is a collective circuit of n latch type flip-flop circuits of 51 to 5n-1, 4 corresponding to the conversion output of -D Jl''.

The control circuit 40 includes counter flip-flops 41 to 4n-0 and gates 401 to 40 for generating periodic l-side leg signals.
In this embodiment, the counter stage of the control circuit 40 has one bit more than the A (I) conversion f) v scale. - A substantial start signal for D conversion is created. A 2fi counting timing signal is created from the signals of the upper two bits via the signals 403 and 404. Furthermore, a reset (discharge) signal for the 1d capacitor 70 is generated from the upper 3 bits of the signal via the gates 401 and 402.

The T-V conversion circuit 30 consists of gates 301 to 304.
A time difference detection section consisting of two gates 305 and 306 that match the numbers of the S7 rethop 70 and its output, and an MO8FET switch 307 and 308, an inverter gate 310, and a cabaret gate 311. The TV conversion circuit 30 is composed of an integral circuit section and an integrated circuit section.
The operation is to convert it into a signal metal pressure according to the time difference between the timing of the 2'' count of the input signal terminal C and the detection timing of V e "' vr a f of the input signal terminal C, and output it as an output. be. The entire correction loop is negative returning and its loop gain is set to approximately unity.

That is, if a time difference of 1% occurs in the time counted by O~2'', the C of the integrating circuit of
B value (capacity of capacitor 311 is MO8F'ET307
．． 308 on-resistance) was selected. This integral resistor uses the on-resistance of a MOSFET, and operates as a current switch in order to increase speed.

The operation of this embodiment configured as above will be explained using the operation waveform diagram shown in FIG. 4. First, the operation of the circuit shown in FIG. 2, that is, the initialization period TI%It period T2 including the start timing corresponding to the integrated voltage waveform V6
, hold period T3, and TloJUiJ, which is T4 between discharge loops J, are created by the NAND condition of the upper 3 bits of the counter of the open side 1 circuit 40, which is obtained by dividing the clock, and in this period, the variable constant current source 10 In the current switch, MOSFET 103 is on and MOSFET 104 is off,
Integral '+tC pressure V of capacitor 70. is O.

Next, in synchronization with the end of T1, that is, the rise of the output of gate 4.05, the counter starts counting from 0, and at the same time, the output J of Goo 1-421 switches, and MOSFET 103
is turned off, J02 is turned on, a constant current is applied to the capacitor 70, and integration is started. When the voltage vc of the capacitor 70 reaches the input voltage V+, the comparator 20a is inverted and generates the latch signal l through the gates 431 and 432, which latches the output latch circuit 50 to hold the output data. In this case, the integrated voltage V. If the value at time 2'' corresponds to V r # f, the output data N will be the value of the relationship expressed by equation (3) above.

Then the count number of the counter reaches 2°, goo) 40
The output signal of No. 4 becomes OIl. The cut v6 is V r @
f reaches, the output C of the comparator 20b is inverted and becomes 0", and the output j of the gate 421 is also "0"K; l) MO8FETrrJ of the variable constant current source 10.

103 is on, 102 is off, and the integrated voltage V of the capacitor 70. moves to hold. Then T4 is gate 4
The capacitor 70 is discharged at the output No. 1n of 02.

Integral voltage ν′ in FIG. The slope of variable constant current source 1
Depending on the size of 0, it changes as 1, 2.3 in the figure. That is, waveform 1. is ■ at 2''. is V'-6rK
Waveform 2 shows a state in which constant current control is neglected, and waveform 3 shows a case where the constant rd current is larger than that, and waveform 3 shows a case where the constant current value is small. Describing the operation when the five flows of the variable stationary flow source 10 are larger than a predetermined value, that is, when v6 is 2, the comparator's V r e f at the time of detection i
jj? 'i becomes a short inverse waveform C as shown in 2. Therefore, an external pulse is generated as shown in waveform f 2, and this is the integral 1. Holds low pressure like h2' Yuba,
do. The constant current value in the variable constant current source 10 is determined by the resistor 101.
Since the terminal voltage of the resistor 101 is controlled by increasing the terminal voltage of the resistor 101, as the voltage of the signal increases, the terminal voltage of the resistor 101 becomes small and the constant current value becomes small. When Vo is waveform 3, the opposite is true.

As mentioned earlier, the constant current transient control basic gain is approximately 1, that is, approximately 1% correction is applied to a 1% deviation, so the deviation becomes approximately 0 after several cycles of corrective action. Moreover, since the correction is performed substantially in parallel with the A/D conversion operation, the correction operation becomes faster. In fact, since the pressure conversion circuit part of the TVJ & conversion circuit 10 is made up of 111 yen in the voltage division and tower, the correction integration continues as long as the deviation) curve occurs. In other words, the steady loop gain is substantially always large, and in combination with the detection method based on the time width of the deviation, highly accurate control becomes possible. In this case, the 1diA difference such as the offset voltage of the operational amplifier in the modified closed loop is not a cause.

Honji, A- in Nya example! ]The converter is a capacitor 7
All except 0 can be constructed using MO8LSI technology.
+5■ Can be operated with a single Vcc power supply.

In this case, the basic performance is 0 to 371 input resolution of 14 bits, conversion time of 1 ms, and accuracy of 1/2 LSB, and since it is a relatively non-pulling configuration, it can be made small.

In the A, -D converter of the present invention, several modifications and
Improvements can be made.

FIG. 5 shows the configuration of a comparator that compares the integrated voltage V of the capacitor at two points, the input voltage V+ and the reference voltage V r *f, using one chopper amplifier. Further, FIG. 6 shows the operation timing waveform in FIG. 5. The comparator includes an inverter amplifier 20 having a feedback switch and an interstage coupling capacitor, and input changeover switches 81 to S3.

A chopper-type comparator with an AC amplifier and a switch of Il:I is normally known as a synchronous comparator with a fixed comparison timing, but in Fig. 5, it is operated in an asynchronous manner with no fixed comparison timing. (Details of this type of comparator are disclosed in Japanese Patent Application Laid-Open No. 55-11626 by the applicant.
).

As shown in FIG. 6, the comparator operates as shown in FIG. Set to comparison period state. V
Immediately after the comparison signal of e, -'V+ is output, the comparison output is launched (v2o).

821 off, Sl, on + So + on V r * t
When the comparison is completed, each switch immediately returns to its initial state.The advantage of the comparison method shown in Fig. 5 is that only one comparator is required. Therefore, 2 of input voltage V1 and reference voltage V r s t
The relative comparison accuracy of points is improved.

Since the comparator can be made up of 114 inverter gates, switches, and MO8 connectors, the circuit is simple and the dependence of accuracy on element sensitivity can be reduced.

Furthermore, since the input parallel switch is essentially a multiplexer, it is easy to provide multiple input channels.

In this case, the problem can be solved by decoding the input channel and switching back the VI every -conversion period.

Various modifications of the closed-loop control TV conversion circuit are also common. The first method is to detect and control the time deviation as a pulse number by adding a reversible counter or a digital comparator.

However, this method requires high-speed logic operations. The second method is to compare the deviation using voltage.

In other words, the charging voltage of the capacitor is held at the point of 2'', and the constant current is set to 1+11 by the difference between this held vc and the reference voltage V r @ f.This allows the iii'i unit of the timing circuit to can be achieved.

Regarding variable constant power supply, in addition to the method shown in 'S example,
This can be achieved using a constant current circuit using transistors.

In this method, the high internal impedance of the constant current source can be achieved using the internal impedance of the element itself, so no operational amplifier is required. In terms of power supply, the embodiment of FIG. 3 is also somewhat larger.

In addition, it goes without saying that the sampling circuit for timing creation can be changed to any periodic control 01() timing as needed by decomposing 11H of 1 clock period according to the logic conditions of each stage of the counter. do not have.

〔Effect of the invention〕

As is clear from the above description, A-
According to the D converter, high precision and high speed can be obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram showing one embodiment of the A-D converter according to the present invention, Fig. 2 is a waveform diagram showing the operation of Fig. 1, and Fig. 3 is an A-D converter according to the present invention. FIG. 4 is a time chart showing the operation of the circuit of FIG. 3, and FIG. 5 is a diagram showing the operation of the circuit of FIG. 3. A circuit diagram showing another embodiment, FIG. 6 is a diagram showing operating waveforms of the circuit of FIG. 5.
Comparator, 30...TV conversion circuit, 40...Hou J +
IIx+ circuit, 50...output latch circuit, 70...
Capacitor, 150°250... changeover switch. 20th ≠ 4 Mouth fraud 1 Mero mouth

Claims (1)

[Scope of Claims] 1. An integrating circuit consisting of a condenser, a constant current circuit, a centrifuge, and a reset switch, and a comparator that compares the magnitude of the dipping voltage I!!i4 iu pressure and the input 1 living pressure; a counter that counts the time from the start of integration to the reversal of the comparator;
In a counting type analog-to-digital converter that obtains a counting output according to the magnitude of the input voltage, there is provided a means for generating a signal that repeatedly performs a conversion operation at a constant cycle, and a means that corresponds to the full scale value of the counter. The output of the integrating circuit at the time of j3. 1. An analog-to-digital converter comprising current adjusting means for adjusting the current of the constant current circuit so that the difference value compared to the current is constantly zero. 2. 2″ full scale of counter and analog V r
The analog system according to claim 1, wherein the correspondence with the full scale of 41 is detected and controlled by a time difference.
Digital converter. 3. Counter 2n full school and analog ~'r
The full school correspondence of ef is expressed as the integral voltage V, and ＼nor＠
Detection control based on the amplitude difference of j) 1], 7-1
:Claim 11! The analog-to-digital converter according to item 1 below.