JPH0366852B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an analog-to-digital converter,
In particular, the present invention relates to a counting type analog-to-digital converter suitable for use in measurement control and capable of achieving high precision and high speed.

[Prior art]

When processing analog signals by computer, an analog-to-digital converter (hereinafter referred to as an A-D converter) is required, and in cases where high precision and high resolution are required, a counting type A-D converter is used. is frequently used.

Conventional counting type A-D converters include single slope type and multi slope type.
Since the former method uses a counter to measure the time until the charging voltage of the capacitor becomes equal to the input voltage, it has the disadvantage that errors may occur if the capacitor, charging current, and counter clock frequency are not constant. The DUAL slope method is an improved directional method that can eliminate the effects of fluctuations in capacitors and clocks, but it has the drawbacks of requiring twice the counting time and slow conversion speed. The TRIPLE slope and QUAD slope methods, which can correct up to full scale adjustment and offset adjustment, are even slower. Furthermore, since the integral waveform of the multi-slope type changes according to the input voltage, it is easily affected by the dielectric absorption phenomenon of the capacitor, and because the comparator does not perform a one-way comparison, it is easily affected by the operating time of the comparator. There were flaws.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly accurate and high-speed counting type analog-to-digital converter.

[Summary of the invention]

In order to achieve such an object, the present invention provides a first integrating circuit consisting of a capacitor, a constant current circuit, and a set/reset switch, and a first integrating circuit that compares the voltage of the first integrating circuit with the input voltage. a comparator; a second comparator that compares the first integrating circuit voltage with a predetermined reference voltage; and counting the time from the start of integration of the first integrating circuit to the inversion of the first comparator. (a) timing signal generating means for generating a timing signal to repeatedly perform a conversion operation at a constant cycle; , (b) opening and closing the constant current circuit in conjunction with the operation of the set/reset switch.
MOSFET; (c) a second integrating circuit that performs positive and negative integration according to the sign of the difference time during the difference time between the time when the second comparator is inverted and the time when the counter reaches the full scale value; (d) means for adjusting the current of the constant current circuit so as to constantly reduce the differential time to zero using the output voltage of the second integrating circuit; (e) the set/reset switch; is composed of a MOSFET connected in parallel to the capacitor and driven to open and close by the timing signal, and (f) the second integrating circuit is composed of an amplifier and a capacitor connected in parallel.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1 is a circuit block diagram showing an embodiment of an A-D converter according to the present invention, and FIG. 2 is an operational diagram showing the main operating parts of the A-D converter. In FIG. 1, a capacitor 70 for generating an integral voltage has one end grounded, and the other end connected to the (-) input terminal of a comparator 20 that also serves as the first and second comparators. The set/reset switch and the variable constant current source 10, which is a constant current circuit, are opened and closed in conjunction with the operation of the set/reset switch.
It is connected to the variable constant current source 10 via a switch 150 that also serves as a MOSFET. A first integrating circuit includes the capacitor 70, the variable constant current source 10, and the switch 150.

A switch 250 is connected to the (+) input terminal of the comparator 20.
is connected to the input signal voltage V _i and the reference voltage source V _ref via. The output of the comparator 20 is sent to the control circuit 40
And it is connected to one input signal terminal 30c of a time-voltage conversion circuit (hereinafter referred to as a TV conversion circuit) 30, which is a second integration circuit. Control circuit 40 serving as timing signal generating means and counter
consists of a plurality of counter stages that are operated by being supplied with a clock CLK, and a logic circuit that generates a periodic control signal, which is a predetermined timing signal, from the signals of each counter stage. From this control circuit 40, T-
A signal from the other input terminal 30b of the V conversion circuit 30 is supplied. A binary counter signal and a latch signal are supplied from the control circuit 40 to an output latch circuit 50 that holds the A-D conversion output data, and outputs and holds the output data N.

The TV conversion circuit 30 is a kind of sample hold circuit, and has two control input signal terminals 30b and 3.
0c and one output signal terminal 30h. The control input signal 30b is given a timing corresponding to the full scale of AD conversion, that is, a timing of 2 ⁿ cycles in binary n-bit AD conversion. A timing signal having a period corresponding to the full scale V _ref of the analog voltage of the comparator 20 is applied to the other control input signal 30c. That is, comparator 20
The timing at which the integrated voltage V _c of the capacitor 70 input to the capacitor 70 reaches the reference voltage V _ref is given. The control output 30h is the control input 30b and 30c.
This is a voltage signal that corresponds to the relative slowness and speed of the two timings. Output 30h of TV conversion circuit 30
The polarities of the two inputs 30b and 30c are such that the closed loop formed by the variable constant current source 10→capacitor 70→comparator 20 becomes negative feedback control.

The current of the variable constant current source 10 is adjusted by a current adjusting means built into the variable constant current source 10 according to a signal output from the output signal terminal 30h.

The operation of the AD converter having such a configuration will be explained based on FIG. 2. In an A/D converter that operates repeatedly on a periodic basis, its operating cycle can be roughly divided into three periods, T ₁ , T ₂ , and T ₃ as shown in the operating waveform diagram of FIG. 2. That is, corresponding to the voltage of the integral capacitor 70 which is a basic signal, T ₁ is a discharge time, T ₂ is an integration time, and T ₃ is a holding time.
T ₁ , T ₂ , and T ₃ are generated by a counter in the control circuit 40 that operates repeatedly. In the simplest timing generation method, using a counting stage with a maximum count of 2 ⁿ⁺¹ , T ₂ = 2 ⁿ t _CLK = T ₁ + T ₃ ...(1) That is, T ₁ and T ₃ are Each has a period of 1/2 of T ₂ .

During the period _T1 , the changeover switch 150 in FIG. 1 is closed to the b side, and the terminal voltage _Vc of the capacitor 70 is discharged to zero. Further, the changeover switch 250 is closed to the a side. Therefore, the input signal voltage V _i is applied to the (+) input terminal of the comparator 20, and 0V is applied to the (-) input terminal.
Furthermore, the output of the comparator 20 becomes "L" level and waits in this state.

Next, when entering the period _T2 , the changeover switch 15
0 is closed to the a side, a constant constant current flows into the capacitor 70 from the variable constant current source 20, and the terminal voltage _Vc thereof increases linearly from 0V. Also, at the same time as the switch 150 is switched to the a side, the control circuit 4
A counter of 0 starts counting from 0. When the charging voltage V _c of the capacitor 70 gradually increases and reaches the input signal voltage V _i , the output of the comparator 20 changes from “1” to “0” and the output latch circuit 50
A latch signal is sent from the control circuit 40 together with a binary count output, and the count number at that time is held. At the same time, the output of the comparator 20 changes from “1” to “0”
After detecting that the switch 250 has changed to the b side, the control circuit 40 switches the changeover switch 250 to the b side, and V _ref is applied to the (+) input terminal of the comparator 20, so that the comparator 2
The output of 0 returns to the state of "1" again. On the other hand, the capacitor 70 continues to be charged and its terminal voltage
When V _c reaches the reference voltage V _ref , the output of the comparator 20 changes from "1" to "0" again, and the change signal is sent to one input signal terminal of the control circuit 40 and the TV conversion circuit 30. This will be communicated to 30c. This state is the final point of T ₂ ' in FIG. Next, control circuit 4
When the count number of the 0 counter reaches 2 ⁿ (T ₂ in FIG. 2), this timing is determined by the T-V conversion circuit 30.
is transmitted through the control input terminal 30b. T-
Two input terminals 30b and 30c of the V conversion circuit 30
The timing input of is based on the relationship between T ₂ and T ₂ ′ in Figure 2, that is, if T ₂ ′ < T ₂ and the time point at which the integrated voltage V _c reaches V _ref is shorter than the time point 2 ⁿ of the counter, then T ₂ −
The voltage proportional to T ₂ ′=ΔT is converted and held at the output terminal 30h as a decrease, and the set value of the output current of the variable constant current 10 is lowered to a value corresponding to ΔT/T ₂ during the period T ₃ . Next, the process moves to period _T1 . This correction operation is a negative feedback operation of sampling control.
Therefore, the difference between T ₂ and T ₂ ′ decreases as the operating cycle passes after the power is turned on, and in steady state T ₂ ′ =
It becomes T ₂ . Assuming that a count output N corresponding to the input voltage V _i is obtained in this state, the capacitor capacity is C, the constant current value is I, and the clock period is t _CLK.
The following relationship holds true.

C・V _ref ] I・T ₂ CV _i = I・T _(N) T ₂ = 2 ⁿ t _CLK T _(N) = Nt _CLK ...(2) Measurements of T ₂ and T _(N) are performed using the same integral Since they are measured almost simultaneously using a circuit, the capacitor capacity C, constant current value I, clock period t _CLK , etc. during both periods T ₂ and T _(N) can be regarded as constant without fluctuation. Therefore, from equation (2), the input/output relationship of AD conversion is as follows.

N=2 ⁿ /V _ref・V _i ...(3) That is, the output N of the above-mentioned A-D converter is proportional to the input voltage V _i with an accurate gain, and the capacitor capacity C, constant current value, and clock Not affected by fluctuations in period t _CLK , etc. Also, the calibration operation (T ₂ ′ → T ₂ described above)
Since the conversion operation and conversion operation are performed substantially simultaneously, the required operation time can be shortened and the operation can be made faster. Furthermore, since the slope of the integrated voltage is always constant and the comparison operating conditions of the comparator are simple and unidirectional comparison, even a simple comparator can easily perform accurate comparison. Further, since the operating waveform of the capacitor is a constant repeating waveform, it is possible to enjoy the advantage that errors due to different dielectric absorption phenomena are less likely to occur due to the influence of the previous history of the voltage applied to the capacitor.

Next, other embodiments will be described in more detail.

FIG. 3 is a circuit diagram showing another embodiment of the A-D converter according to the present invention, and FIG. 4 is an operating waveform diagram of the circuit of FIG. 3. In FIG. 3, parts that are the same as those in FIG. 1 or have equivalent effects are given the same reference numerals. This device is
variable constant current source 10, first comparator 20a, second comparator 20b, and its output holding circuit 431,
432, 433, a control circuit 40, an output latch circuit 50, and a TV conversion circuit 30. First, the variable constant power source 10 is a P-channel MOS field effect transistor (hereinafter referred to as MOSFET) 10 that operates as a current switching switch.
2,103 and each gate voltage switching MOS
Transistor pairs 104, 105 and 106, 10
7. Consists of a resistor 101 for constant current detection, an operational amplifier 108 for constant current negative feedback control, and an inverter gate 109 for switching MOS switches.
The interconnection of each MOSFET switch is made when the input signal of the switching gate 109 is “1”.
MOSFET105,106 turns on, 104,1
07 turns off and current flows through MOSFET102,
In the case of "0", MOSFET104, 107 are on, MOSFET105, 106 are off, and MOSFET103 is turned on.
The connection and polarity are used to switch the current.
The drain of MOSFET 102 is connected to a parallel circuit of an integrating capacitor 70 and a discharge switch 150 which is its set/reset switch. Further, the non-grounded terminal V _c of the capacitor 70 is connected to each input terminal of the comparator 20 b to which the reference voltage V _ref is applied, and the comparator 20 a to which the input voltage V _i is applied. The output terminal of the comparator 20b is connected to one of the inputs of the TV conversion circuit 30. Further, the output of the comparator 20a is the gate 431,
The output latch circuit 50 is connected to the latch input terminal of the output latch circuit 50 through an RS flip-flop constructed as 432. The flip-flop array constituting the output latch circuit 50 is a collective circuit of n latch-type flip-flop circuits 51 to 5n-1 corresponding to n-bit A/D conversion outputs.

The control circuit 40 is composed of counter flip-flops 41 to 4n-0 and gates 401 to 405 for generating periodic control signals. In this embodiment, the counter stage of the control circuit 40 has one bit more than the full scale of the A/D conversion. A substantial start signal for A/D conversion is then generated from the upper 3 bits of the signal via gate 405. Furthermore, ²ⁿ counting timing signals are generated from the upper 2 bits of the signal via gates 403 and 404. Furthermore, the signals of the upper 3 bits are input to the gates 401 and 402.
Resetting (discharging) the integral capacitor 70 via
It is designed to create a signal.

The TV conversion circuit 30 includes two RS flip-flops consisting of gates 301 to 304 and two gates 305 and 306 that match the output signals.
A time difference detection section consisting of a MOSFET switch 3
07, 308, an inverter gate 310, and a capacitor 311. The operation of this TV conversion circuit 30 is to convert a signal corresponding to the time difference between the ²ⁿ count timing of the input signal terminal b and the detection timing of V _c =V _ref of the input signal terminal C into a voltage, and output h. This allows for more output. The entire correction loop is negative feedback and its loop gain is set to approximately unity. That is, if a time difference of 1% occurs between the times counted from 0 to ²ⁿ , the CR value of the integrating circuit of the TV conversion circuit 30 (capacitance of the capacitor 311, MOSFET307,
308 on-resistance) was measured. This integral resistor uses the on-resistance of the MOSFET, and operates as a current switch to increase speed.

The operation of this embodiment configured as above will be explained using the operation waveform diagram shown in FIG. 4. First, the third
The operation of the circuit shown in the figure is as shown in _FIG .
It can be considered divided into ₄ periods. That is, an initialization period T ₁ including the start timing, an integration period T ₂ , and a hold period corresponding to the integral voltage waveform V _c
T ₃ , and a discharge period T ₄ . First, the period _T1 is created by the NAND condition of the upper 3 bits of the counter of the control circuit 40, which is obtained by dividing the clock.
During this period, the current switch of the variable constant current source 10 is
When MOSFET 103 is on and MOSFET 104 is off,
The integrated voltage V _c of the capacitor 70 is zero. next
At the end of _T1 , that is, in synchronization with the rise of the output of gate 405, the counter starts counting from 0, and at the same time, the output j of gate 421 switches, and the MOSFET
When 103 is turned off and 102 is turned on, the capacitor 70 flows a constant current and starts integration. When the voltage V _c of the capacitor 70 reaches the input voltage V _i , the comparator 20a is inverted and generates a latch signal l through the gates 431 and 432, which latches the output latch circuit 50 to hold the output data. In this case, if the value of the integrated voltage V _c at time 2 ⁿ corresponds to V _ref , then
The output data N becomes the value of the relationship in equation (3) above.

Then, the count number of the counter reaches ²ⁿ , and the output signal b of the gate 404 becomes "0". Also V _c
reaches V _ref , the output C of the comparator 20b is inverted and becomes "0", and the output j of the gate 421 also becomes "0", and the MOSFET 103 of the variable constant current source 10 is turned on and the MOSFET 102 is turned off. The integrated voltage V _c of the capacitor 70 moves to a hold state. Then T ₄ is gate 4
The capacitor 70 is discharged by the output signal k of 02. At this time, MOSFET 102 is off, and the voltage of capacitor 70 is 0V. As mentioned earlier, the capacitor 70 starts integration from 0V, and the counter starts counting from 0 when integration starts, so the voltage V _c and the count value of the counter are proportional and can be converted without performing complicated calculations. Data is output.

The slope of the integrated voltage V _c in FIG. 4 changes as indicated by 1, 2, and 3 in the figure depending on the size of the variable constant current source 10. In other words, waveform L is V _c at time 2 ⁿ
Waveform 2 shows a state where the constant current is controlled so that it is equal to V _ref , waveform 2 shows a case where the constant current is larger than that, and waveform 3 shows a case where the constant current value is smaller. When the current of the variable constant current source 10 is larger than a predetermined value, that is,
Describing the operation when V _c is 2,
The detection time of V _ref of the comparator becomes shorter and the 2 of waveform C
become that way. Therefore, a pulse as shown in waveform f 2 is generated, which is integrated and held, and the voltage rises as shown in h 2. Variable constant current source 1
Since the constant current value at 0 is controlled by detecting the terminal voltage of the resistor 101, as the voltage of the signal h increases, the terminal voltage of the resistor 101 decreases and the constant current value decreases. When V _c has waveform 3, the opposite is true.

As mentioned above, the constant current transient control gain is approximately 1, that is, approximately 1% correction is applied to a 1% deviation, so the deviation becomes approximately 0 after several cycles of correction operation. Coupled with the fact that the correction is performed substantially in parallel with the A-D conversion operation, the correction operation is fast. Further, since the voltage conversion circuit section of the TV conversion circuit 10 is constituted by an integrating circuit, the corrective integration continues as long as the deviation pulse is generated. In other words, the steady loop gain has become substantially large, and in combination with the detection method based on the time width of the deviation, highly accurate control becomes possible. In this case, the offset voltage of the operational amplifier in the modified closed loop does not become an error factor.

The A-D converter in this embodiment, except for the capacitor 70, can be constructed entirely by MOSLSI technology and can be operated by a single +5V Vc.c. power supply.
In this case, the basic performance is 0 to 3 V input, 14 bit resolution, 1 ms conversion time, and 1/2 LSB accuracy, and because it has a relatively simple configuration, it can be made compact.

Several modifications and improvements can be made to the A-D converter of the present invention.

Figure 5 shows the integrated voltage V _c of the capacitor as the input voltage
The configuration of a comparator that can perform two-point comparison between V _i and the reference voltage V _ref using one chopper amplifier is shown. Further, FIG. 6 shows the operation timing waveform in FIG. 5. The comparator is constituted by an inverter amplifier 20 having a feedback switch and an interstage coupling capacitor, and input changeover switches _S1 to _S3 .

Such a chopper type comparator using an AC amplifier and a switch is generally known as a synchronous comparator with a fixed comparison timing, but in Fig. 5, it is operated in an asynchronous manner where the comparison timing is not fixed ( Details of this type of comparator are disclosed in Japanese Patent Application Laid-Open No. 11626/1983 by the applicant of the present invention). The operation of the comparator is as shown in Figure 6.
After turning on S ₀ and S ₁ to charge the input V _i to the capacitor, turn off the switches in the order of S ₀ and S ₁ , and then immediately turn on S ₂ to enter a standby state for comparison of V _c . V _c
Immediately after the comparison signal of V _i is output, the comparison output is latched (V ₂₀ ), S ₂ , off, S ₃ , on, S ₀ ,
When turned on, V _ref is charged and V _c V _ref can be compared.

Immediately after the comparison is completed, each switch returns to its initial state. The advantage of the comparison method shown in FIG. 5 is that since only one comparator is required, the accuracy of the relative comparison between the two points of input voltage V _i and reference voltage V _ref is improved. Also, the comparator is connected to the inverter gate and switch.
Since it can be constructed with MOS capacitors, the circuit is simple and the accuracy of the element sensitivity can be reduced.
Furthermore, since the input parallel switch is essentially a multiplexer, it is easy to convert the input into multiple channels. In this case, this is done by decoding the input channel and switching V _i every conversion period.

The portion corresponding to the closed-loop control TV conversion circuit can also be modified in various ways. The first method is to add a reversible counter or a digital comparator to detect and control the time deviation as a pulse number.
However, this method requires faster logic operations. The second method is to compare the deviation in terms of voltage.
That is, this is a method in which the charging voltage of the capacitor is held at a time point of 2 ⁿ , and the constant current is controlled by the difference between this held V _c and the reference voltage V _ref . This allows the timing circuit to be simplified.

In addition to the method shown in the embodiment, the variable constant current source can also be constructed using a constant current circuit of transistors. With this method, the high internal impedance of the constant current source can be achieved using the internal impedance of the element itself, so no operational amplifiers are required. However, in order to obtain good constant current characteristics, a cascode configuration of 2 to 3 stages is required, and the operating power supply In this respect, it is somewhat larger than the embodiment shown in FIG.

Furthermore, it goes without saying that the timing generation control circuit can also be changed to any periodic control timing as necessary, with a resolution of one clock cycle, depending on the logical conditions of each stage of the counter.

〔Effect of the invention〕

As described above, according to the A-D converter according to the present invention, the conversion gain of the second integrating circuit that outputs the signal voltage for adjusting the current of the constant current circuit is independent of the output voltage of the integrating circuit. By determining , dynamic fluctuations in the conversion gain are eliminated, current adjustment is performed with high precision, and the integrator circuit that outputs the integrated voltage V _c that is compared with the input voltage V _i starts integration from voltage zero. Therefore, since the conversion result can be directly read from the counter, it is possible to perform A-D conversion with high precision and high speed, and there is an effect that only one reference voltage is required.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the A-D converter according to the present invention, FIG. 2 is a waveform diagram showing the operation of FIG. 1, and FIG. 3 is a circuit block diagram showing an embodiment of the A-D converter according to the present invention.
A circuit diagram showing another embodiment of the converter, FIG.
FIG. 5 is a circuit diagram showing another embodiment of the voltage comparator of the A-D converter according to the present invention. FIG. 6 is a time chart showing the operation of the circuit shown in FIG. It is a diagram. 10...variable constant current source, 20, 20a, 20b
... Comparator, 30 ... TV conversion circuit, 40 ...
Control circuit, 50... Output latch circuit, 70... Capacitor, 150, 250... Changeover switch.

Claims (1)

[Claims] 1. A first integrating circuit consisting of a capacitor, a constant current circuit, and a set/reset switch; a first comparator that compares the first integrating circuit voltage with the input voltage; a second comparator that compares the magnitude of the integrating circuit voltage with a predetermined reference voltage, and a counter that counts the time from the start of integration of the first integrating circuit to the inversion of the first comparator. , a counting type analog device that obtains a counting output according to the magnitude of the input voltage.
In a digital converter, (a) a timing signal generating means for generating a timing signal for repeating a conversion operation at a constant cycle; and (b) a MOSFET for opening and closing the constant current circuit in conjunction with the operation of the set/reset switch. (c) during the difference time between when the second comparator inverts and when said counter reaches its full scale value;
The second step performs positive and negative integration according to the sign and negative of the difference time.
(d) means for adjusting the current of the constant current circuit so as to constantly reduce the differential time to zero by using the output voltage of the second integrating circuit as an input; e) the set/reset switch comprises a MOSFET connected in parallel to the capacitor and driven to open and close by the timing signal; (f) the second integration circuit comprises a capacitor connected in parallel to an amplifier; An analog-to-digital converter characterized by: