JPS5984855U - semiconductor storage device - Google Patents
semiconductor storage deviceInfo
- Publication number
- JPS5984855U JPS5984855U JP15854683U JP15854683U JPS5984855U JP S5984855 U JPS5984855 U JP S5984855U JP 15854683 U JP15854683 U JP 15854683U JP 15854683 U JP15854683 U JP 15854683U JP S5984855 U JPS5984855 U JP S5984855U
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- semiconductor storage
- circuit
- effect transistor
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による半導体記憶装置の製造工程を示す
断面図、第２図は前記半導体記憶装置の結線実施例、第
３図及び第４図は本考案にか力鵡ＲＯＭの構成を示す結
線図である。
第１図乃至第４図に於いて、１１・・・・・・半導体基
板、１３−１・・・・・・Ｐ−ウェル。FIG. 1 is a sectional view showing the manufacturing process of a semiconductor memory device according to the present invention, FIG. 2 is a wiring example of the semiconductor memory device, and FIGS. 3 and 4 are diagrams showing the configuration of a ROM according to the present invention. It is a wiring diagram. In FIGS. 1 to 4, 11...semiconductor substrate, 13-1...P-well.
Claims (1)
応じてバイポーラトランジスタのベースが対応するワー
ド線に、エミッタが対応するビット線に接続されており
、該ワード線が相補型ＭＩＳ電界効果トランジスタ回路
よりなるゲート回路により駆動され、且つ該ビット線の
出力が相補型ＭＩＳ電界効果トランジスタ回路よりなる
ゲート回路に入力される様に構成されていることを特徴
とする半導体記憶装置。The bipolar transistor has a plurality of word lines and bit lines, and depending on the information to be stored, the base of the bipolar transistor is connected to the corresponding word line and the emitter is connected to the corresponding bit line, and the word line is connected to the complementary MIS electric field. 1. A semiconductor memory device, characterized in that it is driven by a gate circuit comprising an effect transistor circuit, and configured such that the output of the bit line is input to the gate circuit comprising a complementary MIS field effect transistor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854683U JPS5984855U (en) | 1983-10-13 | 1983-10-13 | semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854683U JPS5984855U (en) | 1983-10-13 | 1983-10-13 | semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5984855U true JPS5984855U (en) | 1984-06-08 |
Family
ID=30349242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15854683U Pending JPS5984855U (en) | 1983-10-13 | 1983-10-13 | semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984855U (en) |
-
1983
- 1983-10-13 JP JP15854683U patent/JPS5984855U/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| ELECTRONICS=1970US * |
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