JPS598363A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS598363A
JPS598363A JP11722382A JP11722382A JPS598363A JP S598363 A JPS598363 A JP S598363A JP 11722382 A JP11722382 A JP 11722382A JP 11722382 A JP11722382 A JP 11722382A JP S598363 A JPS598363 A JP S598363A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
leads
corners
protection frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11722382A
Other languages
Japanese (ja)
Inventor
Hideo Noguchi
野口 英夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11722382A priority Critical patent/JPS598363A/en
Publication of JPS598363A publication Critical patent/JPS598363A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To improve efficiency of packing for shipping and realize automatic measurement by forming the guide for alignment at the area near the three corners of a square protection frame which protects a plurality of leads extended outward from the side surfaces of sealed package. CONSTITUTION:A plurality of leads 23 and extended in four directions from the side surface of a resin sealed layer 21 and a protection frame 24 is provided, being isolated from the end of lead 23, at the outside of the lead 23. A protection frame 24 is connected to an upper mount substrate 22 through the bridges 251-254 at the areas corresponding to four corners of the resin sealed layer 21. Since the cut-away portions 271, 272, 28 which are used as the guides for alignment to the automatic measuring apparatus during the measurement of characteristics, are provided at the positions near three corners of the protection frame 24 in such a manner as destroying symmetry of the whole, the direction can be confirmed very easily.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置に関し、特にフラットタイプの半
導体装置における出荷段階の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a structure of a flat type semiconductor device at the shipping stage.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置は一般に内部に半導体装置全封入した封止容
器の側面からリードが外方に延出した形態を有しておシ
、このIJ−ドが屈曲されていないものはフラットタイ
プと呼ばれてい心。
Semiconductor devices generally have a form in which leads extend outward from the side of a sealed container in which the semiconductor device is completely enclosed, and devices in which the IJ leads are not bent are called flat types. heart.

フラットタイプの半導体装置で代表的なものは封止容器
が樹脂封止層で、該樹脂封止層側面から四方向にリード
を延設したクラド2ル・インリード・・母ッケーノ(以
下QIPという)型の半導体装置である。以下このQI
P型半導体装置を例に説明する。
In a typical flat type semiconductor device, the sealing container is a resin sealing layer, and leads are extended in four directions from the side of the resin sealing layer. ) type semiconductor device. Below is this QI
A P-type semiconductor device will be explained as an example.

第1図はQIP型半導体装置の一例を示す斜視図でりる
。同図において、1は封止容器である。
FIG. 1 is a perspective view showing an example of a QIP type semiconductor device. In the figure, 1 is a sealed container.

該封止容器1の中には図示しない半導体素子が封入され
ている。この封止容器1の側面からは四方向に複数のリ
ード2が延出され1おシ、峨リード2は側止容器内部で
前記図示しない半導体素子に接続さJしている。
A semiconductor element (not shown) is sealed in the sealed container 1. A plurality of leads 2 extend in four directions from the side surface of the sealed container 1, and the leads 2 are connected to the semiconductor element (not shown) inside the side container.

上記QIPm半導体装置では、リード幅か・よびリード
ピッチが狭く、そのために加工46度のかねあいから、
リードの厚芒も薄くなっている。
In the above-mentioned QIPm semiconductor device, the lead width and lead pitch are narrow, and because of this, the machining angle is 46 degrees.
The thick awn of the reed is also thinner.

従=、て、QIP型半導体装置のリードは機械的弧度が
弱く、容易に曲げ、iIi等の変形を生しるという問題
があった。ここで、このような半導体装置の製造過程や
枢9扱いに一ついて触れておくと、その話題のために多
数の半導体装置に対応する一連のユニットを有する多連
リードフレームを用意し、各ユニット毎の中央部に位置
するベッドに半導体チップを取付りる上程、この半畳体
チップとその周りに位置するリード片とをワ・イヤボン
ディングする工程、このユニット毎に樹脂モールドによ
シ封止容器を形成する工程、上記封止後のリード片をフ
レームから切り離す工程、その後上記各ユニット毎にリ
ード片に測定子を当tて各半導体装置の電気的物性測定
を行なう工程とがある。また、このような測定は製造者
側で行なうが、客先側でも測定を行なう場合もあシ、近
来その傾向が高まってさている。
However, there is a problem in that the leads of the QIP type semiconductor device have a weak mechanical arc and are easily bent, causing deformation such as iIi. Here, I would like to touch on the manufacturing process and handling of such semiconductor devices. For this topic, we prepare a multi-lead frame that has a series of units that correspond to a large number of semiconductor devices, and each unit The process of mounting the semiconductor chip on the bed located in the center of each unit, the process of wire-bonding this semi-folded chip and the lead pieces located around it, and the process of sealing the container with a resin mold for each unit. , a step of separating the sealed lead piece from the frame, and a step of applying a probe to the lead piece for each unit to measure the electrical properties of each semiconductor device. Furthermore, although such measurements are carried out by the manufacturer, there are also cases where measurements are carried out by the customer, and this trend has been increasing recently.

このように柚々の工程を経るψで、半導体装置及びその
部品が多数の搬送工程をもつことv’Cなる。従って客
先が半尋体銑置衾最終装品として取扱うまでの間、特に
特性測定時などに1ノP変形が生じると、その作業性な
どに著しい支障を来す。この問題のために、QIP型牛
型体導体装置扱いには細心の注意が必要とされ、特に出
荷に除してはリードの変形を防止するために従来から特
別の包装方法が採用されている。
As ψ passes through numerous processes in this way, it becomes v'C that semiconductor devices and their components have a large number of transport processes. Therefore, if the 1-P deformation occurs, especially during characteristic measurements, until the customer handles the product as a final product, workability will be significantly hindered. Because of this problem, extreme care is required when handling QIP type cow-shaped conductor devices, and special packaging methods have traditionally been adopted to prevent deformation of the leads, especially during shipping. .

従来においては、第2図に示すような治具が用いられて
いるので、これについて説明す芯。
Conventionally, a jig as shown in FIG. 2 has been used, so this will be explained below.

この治具はゲラステック製の絶縁板1ノで形成され又お
シ、その中央部に第1図に示された半導体装置の封止容
器1を収納できる開孔をMし、その半導体装置のリード
2.・・・、2配列に対応した多数のスリット12.・
・・、12を有しでいる。このようにして、半導体装置
を上記治具に収納しかつ着脱目在に保持させることによ
って、上記スリット12内にリード2を位置させて、半
導体装置管保護し、これら全体を特性測定装置に取付け
て測定を行なったり、客先へ出荷したυ、また客先にて
再度測定を行ない、応用機   ・器へ使用している。
This jig is made of an insulating plate made of Gerastec, and has an opening M in its center that can accommodate the sealed container 1 of the semiconductor device shown in FIG. 2. ..., a large number of slits 12 corresponding to two arrays.・
..., 12. In this way, by storing the semiconductor device in the jig and holding it in the attachment/detachment position, the leads 2 are positioned in the slit 12 to protect the semiconductor device tube, and the whole is attached to the characteristic measuring device. The products are then measured, shipped to the customer, and then measured again at the customer and used in applied equipment.

〔背景技術の問題点〕[Problems with background technology]

しかしながら、このような格別な治具を使用する必・要
があるため、この治具に半導体装置を着脱する着脱装置
が必要となうたり、手作業を要したル、繁雑さや製品の
コスト上昇を生じている。また、治具に取付ける際にリ
ードが変形することもあり、その取扱いに注意を要する
という欠点があった。
However, since it is necessary to use such a special jig, an attachment/detachment device is required to attach and detach the semiconductor device to this jig, which requires manual labor, complexity, and increases the cost of the product. is occurring. Furthermore, the lead may be deformed when attached to the jig, so there is a drawback that care must be taken when handling it.

〔発明の目的〕[Purpose of the invention]

この発明は上記の点に鑑みてなされたもので、フラット
タイプの樹脂封止型半導体装置におけるリードを保護す
る構造、特にQIP型半導体装置に有効なリードの保護
構造を備え、その出荷包装の効率化および測定の自動化
を可能とした半導体装置を提供することにおる。
The present invention has been made in view of the above points, and includes a structure for protecting leads in a flat type resin-sealed semiconductor device, particularly effective for a QIP type semiconductor device, and improves the efficiency of shipping and packaging. Our objective is to provide a semiconductor device that enables automated measurement and measurement.

〔発明の概要〕[Summary of the invention]

封止容器の側面から外方に延出した複数のリードを保護
する四角の保護枠の3つの角付近に位置合わせ用ガイド
を形成している。
Positioning guides are formed near three corners of a square protection frame that protects a plurality of leads extending outward from the side surface of the sealed container.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照してこの発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第3図はこの発明の一実施例になるQIP型半導体装置
の平面図である。同図において、21は樹脂封止層であ
る。上記樹月旨封止)−21の内部にはマウント基板(
ベッド)22上士にマウントされた図示しない半導体チ
ップ(封入されている。この樹脂封止層21のa置方・
らは四方向に複数のり−ド23力玉延出されて、いる(
なお、各リード23の樹脂封止層21で被覆された部分
の図示は省略しである)。上i己す−ド23は樹脂封止
層21の内部で上り己図示しない半導体素子に接続され
ている。また、1ノード23の外側には保護枠24が+
) −)1” 23の先&iMから離間して設けられて
いる。上B己保腰枠24はリード23と同−元材料の金
属板を打抜いてノ杉崩されたもので、樹脂封止j−21
の四隅に対重6する位置でブリッジ25.〜254を介
して上記マウント基板22に連結されている。この結果
、保護枠24はリード23とIIjj−レベルに設けら
れ、かつ外見上はm )I旨A’l止7421の四隅に
固定された状態になりている。また、樹月旨封止jIi
i21の四隅における一辺@11力為ら保+屓枠24に
切込棉261〜264を設けてあり、従りて保護枠24
は樹脂封止層の他辺側においてのみ上記プリツノ部25
1〜254 と連結している。
FIG. 3 is a plan view of a QIP type semiconductor device according to an embodiment of the present invention. In the figure, 21 is a resin sealing layer. The inside of the above-mentioned Jugetsuji seal)-21 has a mount board (
A semiconductor chip (not shown) mounted on the bed) 22 (sealed).
They are extended in multiple directions in four directions (
Note that the portion of each lead 23 covered with the resin sealing layer 21 is not shown). The upper board 23 is connected inside the resin sealing layer 21 to a semiconductor element (not shown). In addition, a protective frame 24 is provided outside the 1 node 23.
) -) 1" It is provided at a distance from the tip of 23 & iM. The upper B self-protection frame 24 is made by punching out a metal plate made of the same original material as the lead 23 and breaking it down with resin. stop j-21
Bridge 25 at a position opposite to the four corners of 6. It is connected to the mount substrate 22 via .about.254. As a result, the protective frame 24 is provided at the IIjj-level with the leads 23, and is apparently fixed at the four corners of the stops 7421. Also, Kizukiji sealing jIi
Incisions 261 to 264 are provided in the protection frame 24 on one side @ 11 at the four corners of i21, so that the protection frame 24
The pre-shaped portion 25 is formed only on the other side of the resin sealing layer.
1 to 254 are connected.

更に、この連結部の保護枠24表面゛または鉄面□には
樹脂封止層21に沿って図示しない折シ切シのための溝
が設けられている。また、保護枠24の一辺外縁には二
つの切欠凹孔271,272が形成されておシ、他方、
その対向辺の外縁には一つの切欠凹孔28が形成されて
いる。なお。
Furthermore, a groove (not shown) for breaking is provided along the resin sealing layer 21 on the surface of the protective frame 24 or the iron surface □ of this connecting portion. In addition, two cutout holes 271 and 272 are formed on the outer edge of one side of the protective frame 24.
One notch hole 28 is formed on the outer edge of the opposite side. In addition.

上記保護枠24は樹脂封止型半導体装置の製造に通常用
いられるリードフレームの外枠を切り離さないでそのま
ま用い1必る。
The protective frame 24 must be used as it is without cutting off the outer frame of a lead frame that is normally used in the manufacture of resin-sealed semiconductor devices.

上記実施例においては全体の対称性を損うように保護枠
24の3つの角付近に特性測定時に自動測定装置への位
置合わせ用ガイドとして用いられる切欠凹孔271.2
72.28を設けであるから、その方向を極めて容易に
確認することができる。ところで、上記実施例のQIP
 W半導体装置を実際に使用する場合には保護枠24を
取シ除かなければならない。しかし、保護枠24は簡単
な装置で封止層2ノの四隅においてプリツノ部251〜
254を切断して切り離すことができるから、この作業
は出荷先のユーザーサイドで容易に行なうことができる
。また、保護枠24の連結部に折シ切りのための溝を設
けた上記実施例では特別の装置を用い乞ことなく保護枠
24を折シ取ることもできる。
In the above embodiment, notch holes 271.2 are provided near the three corners of the protective frame 24 so as to impair the symmetry of the whole, and are used as guides for positioning the automatic measuring device during characteristic measurement.
72.28, the direction can be confirmed very easily. By the way, the QIP of the above example
When the W semiconductor device is actually used, the protective frame 24 must be removed. However, the protective frame 24 can be formed using a simple device at the four corners of the sealing layer 2.
254 can be cut and separated, this work can be easily performed at the user's side at the shipping destination. Further, in the above-mentioned embodiment in which the connecting portion of the protective frame 24 is provided with a groove for breaking the protective frame 24, the protective frame 24 can be broken without using a special device.

第4図は第3図実施例における半導体装置をイ4するま
での途中段階における形態を示す平面図である。半導体
製造者側では、゛まず保護枠24個々のユニットとして
を多数連結したとみなぜるいわゆる多連リードフレーム
を用意する。尚初においてリード23は保強枠24に連
結して形成ちれておシ、リードフレームの各ユニットの
中央部にあるベッドへ半導体系子を取t」け、その素子
の電極と上記リード2゛3とをボンディングワイヤに列
接続し、その後上記素子やり−ドを樹脂的止層21によ
シ被い、各リード23     ′を保り枠24から切
夛離すと共に、各保護枠24毎にリードフレームから切
p出し第3図の如き形状金得る。即ち、半導体装置の製
造においては上述の如く多くの工程を必要とするが、常
にリードフレームを構成する保岐枠24がリード23を
保護することになる。そして本発明にふ・いては、半導
体装置の特性測定段階でも、上記保強枠24を残してお
く、しかもその四角形状の保護枠24自体の3つの角付
近に位置合わせIイド271.27..28を形成しで
あるので、その非対称性を保ち、測定装置への位置合わ
せを間違いなく行なえる。
FIG. 4 is a plan view showing the semiconductor device in the embodiment of FIG. 3 at an intermediate stage up to A4. The semiconductor manufacturer first prepares a so-called multi-lead frame in which a large number of protective frames 24 are connected as individual units. At first, the leads 23 are connected to the reinforcing frame 24 and formed, and then a semiconductor device is placed on the bed in the center of each unit of the lead frame, and the electrodes of the device and the leads 2 are connected to each other. 3 are connected to bonding wires in a row, and then the above-mentioned element leads are covered with the resin stopper layer 21, each lead 23' is separated from the retaining frame 24, and each protective frame 24 is Cut out the lead frame to obtain a shape as shown in FIG. That is, although manufacturing a semiconductor device requires many steps as described above, the lead frame 24 that constitutes the lead frame always protects the leads 23. According to the present invention, the protective frame 24 is left even in the stage of measuring the characteristics of the semiconductor device, and moreover, the I-id 271, 27, . .. 28, the asymmetry can be maintained and alignment to the measuring device can be performed without error.

また、第4図に示す多連形態で測定、出荷も可能である
Further, it is also possible to measure and ship the device in a multiple series configuration as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明によれば、従来のような格
別に製作した旧具を使用することなく全体の対称性を損
うように四角形の保−枠の3つの角付近に特性測定時に
用いらノLる位置合わせ用ガ゛イドを設けたので、その
方向を使めて容易に確認することができる。δうに、谷
リードの外側に保強枠が配設されているから、保強枠を
把持して取扱うことによか取扱いの際にリードが変形す
るのを防止することができる。またそれ故、製造者側及
びユーザー側での自動測定が可能となる。
As described in detail above, according to the present invention, there is no need to use specially manufactured old tools as in the past, and when measuring characteristics, there is a Since a free alignment guide is provided, the direction can be used for easy confirmation. Since the reinforcing frame is disposed on the outside of the valley lead, it is possible to prevent the lead from being deformed during handling by grasping and handling the reinforcing frame. Also, automatic measurements on the manufacturer's side and on the user's side are therefore possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のQIP型半導体装置の斜視図、第2図は
従来用いられていた治具を示す斜視図、第3図はこの発
明の一実施例を示すQIP W半導体装置の平面図、第
4図はこの発明の実施例に係るQIP型半導体装置の製
造の一過程をかす平面図である。 出顔人代理人  弁理士 鈴 江 武 彦!1図 1 第3図 824
FIG. 1 is a perspective view of a conventional QIP type semiconductor device, FIG. 2 is a perspective view showing a conventional jig, and FIG. 3 is a plan view of a QIP W semiconductor device showing an embodiment of the present invention. FIG. 4 is a plan view showing one process of manufacturing a QIP type semiconductor device according to an embodiment of the present invention. Appearance representative Patent attorney Takehiko Suzue! 1 Figure 1 Figure 3 824

Claims (1)

【特許請求の範囲】[Claims] 内部に半導体素子を封入しlこ封止1容器と、該封止容
器の内部で前記半導体素子に接続され、かつ封止容器の
側面から直線状に外方に延出した嶺数のリードと、該リ
ード先端の更に外方に配設され前記封止容器に部分的に
固定された四角形の保護枠とからな9、この保護枠の3
つの角付近に位置合わせ用力゛イドを形=したことを特
徴とする半導体装置。
A sealed container with a semiconductor element sealed therein, and a number of leads connected to the semiconductor element inside the sealed container and extending outward in a straight line from a side surface of the sealed container. , a rectangular protective frame disposed further outward from the lead tip and partially fixed to the sealed container; 3 of the protective frame;
A semiconductor device characterized in that a positioning force field is formed near one corner of the semiconductor device.
JP11722382A 1982-07-06 1982-07-06 Semiconductor device Pending JPS598363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11722382A JPS598363A (en) 1982-07-06 1982-07-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11722382A JPS598363A (en) 1982-07-06 1982-07-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS598363A true JPS598363A (en) 1984-01-17

Family

ID=14706436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11722382A Pending JPS598363A (en) 1982-07-06 1982-07-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS598363A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057924A1 (en) * 2000-02-02 2001-08-09 Infineon Technologies Ag Semiconductor component with contacts provided on the lower side thereof, and method for producing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057924A1 (en) * 2000-02-02 2001-08-09 Infineon Technologies Ag Semiconductor component with contacts provided on the lower side thereof, and method for producing the same

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