JPS5983253A - Storage device for trace - Google Patents

Abstract

PURPOSE:To prevent the influence exerted upon a control calculation time, by performing the control calculation in a CPU, and writing automatically data in a storage device for tracing simultaneously with data inputting outputting to a main storage circuit or an input/output device. CONSTITUTION:A CPU1 inputs or outputs data to a main storage circuit 2 or input/output devices 3 and 4 once through a data bus 5 in every cycle of the control calculation. In this case, not only this data appears on the data bus 5 but a designated address appears on a bus 6. At this time, a code converting circuit 72 grasps the designated state and stores a specific address of the main storage circuit 2 and input/output data of input/output devices 3 and 4 in an auxiliary storage circuit 73. Consequently, programs and the execution time related to the write of diagnostic data are made unnecessary, and the influence exerted upon the speed of the main control calculation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on a data processing system in which the central processing unit (CPU and the CPU) sends and receives data to and from the main memory circuit or the input/output connection 1d according to the periodic lx 11fF- according to the program. , This is related to the trace record for #ft'tr and distributed over the latest several cycles, and is particularly related to the 1-breath device reverse when a device failure occurs. The best way to apply dK is to diagnose the cause by stopping and reproducing it.

Conventionally, the CPU has been used as a trace storage device used in the examination of the late Hitomi, a control device that has a CPU and operates periodically according to a program. iφ, input/output data to one circuit or multiple input/output devices according to a pre-created one-shot program! ! There are ways to express, write, and write. Ivy.

However, with such a device, tracing records are recorded, addresses, and CPU/programming are performed at actual cost, so there is no trace of time, The execution time related to the 1' message is required, and the more points to be traced, the longer this execution time is.
In addition, the short calculation period of the main control calculation puts a burden on the main 'Ai operation, reducing the control calculation time.

The present invention has been made in order to eliminate the drawbacks of the conventional stand-alone system as described above. By writing directly to trace memory 1, there is no need for a program related to writing data during diagnosis and a lifetime, and the trace memory does not affect the calculation speed of the main control example calculation. The storage device is provided for all purposes.

In order to achieve the above object, the present invention performs a counting operation on the trace storage device in synchronization with the cycle of the 1m control calculation operation to detect the number of cycle repetitions of the control operation and to detect the number of cycles to send out a signal. A four-cycle detection circuit that detects that the CFU designates either the number address of the main memory circuit or one of the plurality of input/output 101 paths, and sends out a detection signal for the fltll control stage within each cycle based on the designation. circuit, and
Input the address of the M-period count 1 and the in-cycle stage detection key, and input the input/output data manually through the data bus at the input of the 19th detection in the cycle N1. It was constructed with an auxiliary memory circuit for storing data.

An embodiment of the present invention will be described below with reference to FIGS. 1-3. Among these, FIG. 1 is a block diagram of the unpacking device including the trace storage device ml, and (1) is a CPU that executes control calculations;
+21 is a main memory circuit that stores programs, data, etc. that operate CPU II, (3) and (4) are input/output devices, (5) is a data bus, and (6) is an address bus, which connects CPUf1+ and the main memory. A data bus (5
Data transfer is carried out via the CPLI[11], and designated addresses and the like are exchanged by the CPLI[11] via the address bus (6). Further, (7) is an embodiment of a trace storage device according to the present invention, which is connected to a data bus (5) and an address bus (6), and whose detailed configuration is shown in FIG. The trace storage device (7) in FIG. 2 performs a counting operation from the pulse 5PVc synchronized with the ifi control calculation cycle of the CPU (11) and outputs the binary value B of the count content. The CPU fH connects the binary counter (L4) and either the memory address I/S or the human output device (3)% (4) to the address bus. A code conversion circuit 1, which is a four-stage cycle detection circuit, outputs a binary number B corresponding to the designation, and
It is composed of an auxiliary memory circuit, lJ, which inputs the address of the above picture 21 whistle number I BB and stores the above data input via the data node (s x% y (5). 1
Next, the address bus of Urasuke memory circuit 4 and the above 4
Describing the operation of the illustrated real noise zero example with m-composition,
Figure 1 Whitening consisting of preparation [The device is an input/output model 1. dI:+
1 and (4) to detect the state of the controlled object, and while exchanging information with the upper memory 1 route (2).
An output that reduces the difference between 431j'' and The SP sent out synchronously counts the number of times a series of egg-breaking operations have been repeated, and calculates the number of repetitions B,
Send to all auxiliary storage circuits 4/4. Nafu・、Repetition times 1i
The maximum value N of y 13 is determined, and when this value is exceeded, the system returns to O again as a countermeasure.

On the other hand, the code conversion circuit layer includes the addresses in the main memory circuit (2) and the input/output device (f31) for the CPU 11 to perform control operations, and all address buses for inputting and outputting data in (4). (6) is detected and the binary code B corresponding to the specified content is O for the specifying stage of the auxiliary memory circuit, and ↑ of the input/output device (3).
For the specified stage, it is expressed as 1, and for the specified stage of input/output -11 (4+, it is expressed as 2, and the corresponding 2, 41: code B is output to the auxiliary storage circuit I73.
Auxiliary memory circuit receiving decimal code BB 28%
For y +73, enter these codes into the address 71 L, CP
U (11) inputs and stores data from the data bus (5) which is input/output to the above-mentioned designated device.

Furthermore, this storage (method) is shown by the address structure of a two-dimensional matrix of This will be explained in detail using the auxiliary memory circuit shown in FIG. Main memory circuit (2) and input/output device (3), (4
) is input/output 71 through the data bus (5) once at a time.

Now, suppose that in a certain performance α-Shusuke, the value of the binary counter 1·υ is B = 0, and in that state the CPU
(11 is the main memory, circuit (assuming that data is input (or output) to the special electric address of 21, the address bus (6) has the specified address of the unique circuit (2), the usage, the data bus ( 5) shows the data that should be input (or output). At this time, the code conversion circuit 7'+ (or output) can be seen. At this time, the code conversion circuit
The data on the Z bus (5) is t Yusuke g self 1 episode] mouth 1 route 1.・
→ Matrix C) 'When Ufl+ outputs data to the input/output device (3), the data appears on the data bus (5), and the output y and t
A designation indicating anτ appears on the address bus (6). At this time, the code conversion circuit (/→ outputs Bl according to the voice change code set in advance by W), and the data on the data bus (5) is d). It is stored in the same ←1.
CI) U [11 input/output IE W 711 (7 dl in 41, if input 1 (or output) is performed, the data is stored in the position of matrix key point (2°0), b
Similarly, data for each stage within the 11M period is shown in B-
, -0 addresses are updated and stored.

When the operation of the cycle is finished, the binary count, the special address of the main memory circuit (2), the input from the CPU (11) to the input/output device (3), the input/output device (4), etc. (or output 71) data is stored in the auxiliary memory circuit, the matrix of fluorine (0,1,), (1,1) and (2,1), respectively.
) This action is memorized in the location of each? This is repeated every 1t11 calculations. In addition, B72N
In other words, when the maximum possible period of B (imi) ends, the contents of each matrix element of B, l/, = 0 are changed to BO in the next period.
, nself+l;i is done.

In this way, (
M+1) stage data is stored in the auxiliary storage circuit 173 over the latest (N+1) Zhoubin 1, and if an abnormality occurs in the discount device, the data can be reproduced as t and used for abnormality diagnosis. It is.

By the way, is there a way to reproduce this? Well, first of all, next ti(
J # (# +1=) is stopped, and then, from the value B = 4 of the binary counter l/I on the stop plane, count by one with a pulse haikugo (not shown) that is separate from the pulse haigo SP. A method of reading out the stored data of the auxiliary memory circuit (, 4) is considered. According to this method, the past (N+1) is read out in the order of B-, y+1, v+2°--, N, 0, 1...y. Data for a period can be reproduced.

In the above embodiment, the last input (or output) of the pulse signal SP is generated at the time when the last input (or output) of the pulse signal SP is generated. It is obvious that one input sewing point in the middle of the cutting bell cycle may be used as long as it is synchronized with the shaving bell cycle.

As described above, according to the present invention (I, CPU
ml performance a-? When inputting or outputting data to/from the input/output device (1), the data is automatically written to the trace memory (itK) at the same time.
(Therefore, there is no need for a program related to the writing of diagnostic data, and there is no need for real time, and it has the effect of not forcing one god into the performance of the main character, nine characters, and one character). Since the data to be traced is recorded in synchronization with the a' period, the data to be traced is spaced at equal intervals in time, and the time relationship of several 1 tM m1 worth of data can be clearly seen during playback.
Lose money.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a trace memory device according to the present defense (+if+). Figure 1, Figure 3 Figure 1 is for the second trace.
．． - The address structure of the auxiliary memory circuit is diagrammed and explained in detail. (1): Central processing unit (CPU), (2): Main memory circuit, (3), (4) Two-person output device, (7) d for Nidorase
Self 1. Ei I crack 1 degree, (l〃: Cycle number detection circuit (2J counter), (7J: Intra-cycle stage detection circuit (code converter)
, (7J: Auxiliary d-pin memory circuit. In the figure, the same symbols are shown for PA, YODO and RIS. 1 substitute: Makoto Kuzumachi - M1 Figure 21 Figure 3

Claims (1)

[Claims] When the central processing unit performs periodic control calculation operations according to the program, the latest data exchanged between =M- and the central processing unit is stored in the main memory circuit or the plurality of input/output devices 4. A trace storage device that sequentially records information over several cycles includes a cycle number detection circuit that performs a counting operation in synchronization with the cycle of the control operation operation and sends out a detection signal of the number of cycle repetitions of the control operation; an in-cycle stage detection circuit that detects that the device designates multiple addresses of the main memory circuit or collapse of the multiple input/output circuits, and sends a detection signal of a restraint stage within each cycle based on the designation; The first cycle detection signal and the intra-cycle stage detection signal are manually addressed, and an auxiliary memory circuit stores the exchange data via a data bus when the intra-cycle stage detection signal is manually input. storage device for tracing.