JPS598054B2 - Method of manufacturing an integrated matrix containing a large number of electrical components - Google Patents

Method of manufacturing an integrated matrix containing a large number of electrical components

Info

Publication number
JPS598054B2
JPS598054B2 JP49099064A JP9906474A JPS598054B2 JP S598054 B2 JPS598054 B2 JP S598054B2 JP 49099064 A JP49099064 A JP 49099064A JP 9906474 A JP9906474 A JP 9906474A JP S598054 B2 JPS598054 B2 JP S598054B2
Authority
JP
Japan
Prior art keywords
electrical
inductor
series
circuit
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP49099064A
Other languages
Japanese (ja)
Other versions
JPS50109465A (en
Inventor
エイ ジエニングス ト−マス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hull Corp
Original Assignee
Hull Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hull Corp filed Critical Hull Corp
Publication of JPS50109465A publication Critical patent/JPS50109465A/ja
Publication of JPS598054B2 publication Critical patent/JPS598054B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0397Tab
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672Superposed layout, i.e. in different planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092Integral conductive tabs, i.e. conductive parts partly detached from the substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4635Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 本発明は電気コンポネントに関し、特に統合母体に共同
して組立てた複合電気コンポネントに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electrical components, and more particularly to composite electrical components assembled together into an integrated matrix.

誘導子やコンデンサーや抵抗器が電子回路に使用される
ことはよく知られている。
It is well known that inductors, capacitors, and resistors are used in electronic circuits.

これらのコンポネントを小型エレクトロニクスやその他
のハイブリッド工業界で使用することは、これまでコン
ポネントの大きさや、これらを回路形態に組立てる際に
費される価格やこれらコンポネントを相互に接続するの
に用いた導線の効果によるインダクタンスやキャパシタ
ンスの変化によつて生じた好ましからざる電気回路特性
のために、制限されて来た。この基本的概念に立つて、
本発明は所望の形態と電気特性をもち絶縁材の膜によつ
て分離した電気的に良導性の素子による多数の層膜を形
成して単一の統合母体に組立てられた多数の電気コンポ
ネントを提供するものであり、これら導体の端子は多様
に亘る単一の直列と並列のコンポネント回路配置を形成
するため選択して接続できる。
The use of these components in small electronics and other hybrid industries has traditionally been limited by the size of the components, the cost involved in assembling them into circuit form, and the conductors used to interconnect these components. have been limited due to undesirable electrical circuit characteristics caused by changes in inductance and capacitance due to the effects of Based on this basic concept,
The present invention provides multiple electrical components assembled into a single integrated matrix by forming multiple layers of electrically conductive elements having desired morphology and electrical properties and separated by membranes of insulating material. The terminals of these conductors can be selectively connected to form a variety of single series and parallel component circuit arrangements.

本発明の主要な目的は上述の基本概念に基き、従来個々
の電気コンポネントの使用に関して附随した上記の制御
や欠点を克服することである。本発明の他の重要な目的
は、コンポネント素子を広範囲に互り種々に配置しなが
ら安価に製造できる簡単な構造を持つた複合電気コンポ
ネントを統合形態に形成することである。本発明の上述
その他の目的や利点は好適実施例の付図に関して記述す
る以下の詳細な説明から明らかとなろう。
The main object of the present invention is to build on the above-mentioned basic concept and to overcome the above-mentioned controls and disadvantages traditionally associated with the use of individual electrical components. Another important object of the present invention is to form a composite electrical component in an integrated form having a simple structure that is inexpensive to manufacture, with the component elements being arranged in a wide variety of ways relative to one another. These and other objects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings of the preferred embodiment.

上述の如く統合形態に構成された複合電気コンポネント
は本発明に応じて配置され、電気材料の層膜によつて分
離した一定の電気特性をもつ電気導体からなる多数の積
層膜を相互に接合し、電気端子は種々な直列と並列のコ
ンポネントの回路配置をあたえるため選択的に接続され
、絶縁材の層膜を介して導体の所定のものから導線が延
長される。
A composite electrical component constructed in an integrated form as described above is arranged in accordance with the invention and comprises interconnecting a number of laminated films of electrical conductors having defined electrical properties separated by layers of electrical material. Electrical terminals are selectively connected to provide circuit configurations of various series and parallel components, and wires are extended from certain ones of the conductors through layers of insulating material.

附図の第1図と2図によると、電気的に良導性導体から
なる多数の相互接続された巻回線からなる電気導体10
が示され、この巻回線は絶縁材14の介在層膜によつて
他から分離される。
According to Figures 1 and 2 of the accompanying drawings, an electrical conductor 10 consisting of a number of interconnected windings of electrically conductive conductor is shown.
is shown, and this winding is separated from the others by an intervening layer of insulation 14.

対向せる端部巻回線部16と18はそれぞれ絶縁膜20
と22で被覆される。電気端子24と26は、絶縁膜を
介してそれぞれ端部巻回線部16と18から横に延長す
る。
The opposing end winding portions 16 and 18 each have an insulating film 20.
and 22. Electrical terminals 24 and 26 extend laterally from end turns 16 and 18, respectively, through an insulating membrane.

導体と絶縁材の多重膜は統合母体として接合される。中
央開口部28は母体を通して設けられ、一対の誘導子に
変圧器としての機能を持たせるため、磁気金属ループに
よつて結合せしめる。コイルの巻回線部を形成する層膜
は、例えば金属打抜きで形成した厚い膜層である。
The multiple layers of conductor and insulating material are joined together as an integrated matrix. A central opening 28 is provided through the matrix and a pair of inductors are connected by a magnetic metal loop to function as a transformer. The layer forming the winding portion of the coil is, for example, a thick film formed by stamping metal.

これら層膜は例えば一般のプリント回路技術によつて形
成した薄膜とすることもできる。絶縁材の層膜は、予め
形成したシートと粘着若しくは熱密封によつて接合し減
積層組立部品で形成される。しかし誘導子は、1970
年の3月6田こ出願の目下審査中の米国特許第17,1
57号で記述した方法で電気良導体と絶縁材の蒸着によ
つて形成される。本発明によると、誘導子コイルの端部
巻回部16と18の1方か両方は、残りの巻回部の抵抗
より大きい所定の電気抵抗をもつ如く形成される。この
ようにして巻回線部の結合は直列のRL回路を形成する
さらに、誘導子の端部巻回部16と18の一方若しくは
双方はコンデンサーの極板の1つとして作用し、これに
より直列のLC回路を形成する。
These layers can also be thin films formed by conventional printed circuit techniques, for example. The layers of insulating material are bonded to preformed sheets by adhesive or heat sealing to form a reduced-laminar assembly. However, the inductor was
U.S. Patent No. 17,1, currently under examination, filed on March 6, 2017
It is formed by vapor deposition of an electrically conductive material and an insulating material using the method described in No. 57. According to the invention, one or both of the end turns 16 and 18 of the inductor coil are formed to have a predetermined electrical resistance that is greater than the resistance of the remaining turns. The combination of the windings thus forms a series RL circuit. Furthermore, one or both of the end turns 16 and 18 of the inductor may act as one of the plates of the capacitor, thereby forming a series RL circuit. Form an LC circuit.

このため導体材の層膜30は上記コンデンサー板の1つ
と協働する第2コンデンサー板を形成するため、コイル
の相応する端部に重ねられる。第2極板30は、介在絶
縁膜20か22によつて第1極板16か18からそれぞ
れ電気的に分離される。1つ若しくはそれ以上の電気端
子、望ましいのは1対の端子32と34と第2コンデン
サー薄板30から延長する。
To this end, a layer 30 of conductor material is superimposed on the corresponding end of the coil in order to form a second capacitor plate cooperating with one of the capacitor plates mentioned above. The second plate 30 is electrically isolated from the first plate 16 or 18 by an intervening insulating film 20 or 22, respectively. One or more electrical terminals, preferably a pair of terminals 32 and 34, extend from the second capacitor lamina 30.

絶縁膜36は、第2極板30と統合母体として接合した
組立体にかぶせられる。誘導子の端巻線部16と18が
コンデンサー極板として使用されない時は、絶縁膜36
によつて分離した一対の層膜板30が誘導子10の1方
か両端にかぶせられる。この配置によつて誘導子とコン
テンサ一とは別々のコンポネントとして利用できるし、
端子24と26と32と34とを適当に接続して直列若
しくは並列にこれらコンポネントを接続することが可能
になる。電気良導性の層膜30は、第1図に示す如く誘
導子と抵抗器を別々に選択使用したり、直列若しくは並
列に接続するため所定の電気抵抗を備え誘導子10と連
結する。
The insulating film 36 is placed over the assembly joined to the second electrode plate 30 as an integrated matrix. When the end windings 16 and 18 of the inductor are not used as capacitor plates, the insulating film 36
A pair of laminar plates 30 separated by the above are placed over one or both ends of the inductor 10. This arrangement allows the inductor and capacitor to be used as separate components,
Appropriate connections between terminals 24, 26, 32, and 34 make it possible to connect these components in series or in parallel. The electrically conductive layer 30 has a predetermined electrical resistance and is connected to the inductor 10 so that the inductor and resistor can be used separately or connected in series or in parallel as shown in FIG.

かくて所定数の電気良導性の膜30は、積層の統合母体
に組込まれて、所望数のコンデンサー板・や抵抗器を形
成する。
Thus, a predetermined number of electrically conductive membranes 30 are incorporated into an integral matrix of laminates to form the desired number of capacitor plates or resistors.

これら素子の種々な組合わせは、第3図〜第10図に図
示してある。第3図は第1図の組立状態を示し、第3a
図はこれによつてもたらされる種々な回路の配置を示す
Various combinations of these elements are illustrated in FIGS. 3-10. Figure 3 shows the assembled state of Figure 1, and Figure 3a
The figure shows the various circuit arrangements this results in.

かくて最上端の回路配置は第2極板30と関連したコン
デンサー板として誘導子の端部巻回部18を利用して形
成した直列のLC回路である。次の段の回路配置はコン
デンサー板としての対向端の巻回部18と抵抗器として
の誘導子端の巻回部16を利用して形成したRLC回路
である。以下2つの図面は、誘導子10と関連した抵抗
器として層膜30を利用した図面である。
The topmost circuit arrangement is thus a series LC circuit formed using the inductor end turns 18 as a capacitor plate associated with the second plate 30. The next stage circuit arrangement is an RLC circuit formed using the windings 18 at the opposite ends as capacitor plates and the windings 16 at the inductor ends as resistors. The following two figures illustrate the use of a layer 30 as a resistor in conjunction with an inductor 10.

これらの素子は別個に利用されるか、端子を接続したこ
とを示す破線の1方若しくは両方で示した如く直列若し
くは並列に接続される。誘導子10の端部巻回部16か
18がコンデンサーの極板若しくは抵抗器として用いら
れると、それと誘導子のコイルの近接巻回線部間の導線
の接属は除かれるが、これは別個のコンポネントを接続
するため使用した導線によつて一般に生ずる逆効果の発
生を防止して行なわれることは特記すべきである。
These elements may be used separately or connected in series or parallel as indicated by one or both of the dashed lines indicating connected terminals. When an end turn 16 or 18 of the inductor 10 is used as a capacitor plate or resistor, the connection of conductors between it and the adjacent turns of the inductor coil is eliminated, but this is a separate It should be noted that this is done to avoid adverse effects commonly caused by conductive wires used to connect the components.

さらに導体の層膜30が電気抵抗として使用されその端
子32が誘導子10の端末26に連結される場合には、
これら極めて短い導線の接続から生ずる逆効果は絶対最
少限に抑制される。第4図は単一の誘導子10が示され
、その内部には端部巻回部18(若しくは所望ならば対
向せる端部巻回部16)が、残りの巻回部の抵抗より大
きい所定の電気抵抗を以て形成される。この配置は第4
a図に示した直列のRL回路を形成する。第5図では統
合母体として接合された2個の誘導子10と10′が示
される。これら2個の誘導子は別個の誘導子として別々
に利用されるか若しくは第5a図に示した直列のLC回
路として利用される。従つて上述した様に端部の巻回部
16か18′の何れか丁つを電気抵抗として配置するこ
とによつて第5a図の回路には直列抵抗が含まれること
になる。第6図は誘導子10と一対の導体膜30と30
′を組立てたものである。第6a図に示した如く、この
配置は誘導子と別のコンデンサーを配置するため利用さ
れる。これら素子は別個に利用されるか、直列か並列に
接続して利用される。第6a図は或る配置を示しこれ.
によつて第6図の組立ては別個の抵抗器3『と直列のL
C回路を形成しよう。
Furthermore, when the conductor layer 30 is used as an electrical resistor and its terminal 32 is connected to the terminal 26 of the inductor 10,
The adverse effects resulting from these very short conductor connections are suppressed to an absolute minimum. FIG. 4 shows a single inductor 10 within which an end turn 18 (or an opposing end turn 16, if desired) has a resistance greater than the resistance of the remaining turns. It is formed with an electrical resistance of This arrangement is the fourth
Form the series RL circuit shown in Figure a. In FIG. 5, two inductors 10 and 10' are shown joined as an integrated matrix. These two inductors can be used separately as separate inductors or as a series LC circuit as shown in FIG. 5a. Thus, by arranging one of the end turns 16 or 18' as an electrical resistor as described above, a series resistor is included in the circuit of FIG. 5a. FIG. 6 shows an inductor 10 and a pair of conductor films 30 and 30.
' is assembled. As shown in Figure 6a, this arrangement is used to place an inductor and another capacitor. These elements may be used separately or connected in series or parallel. Figure 6a shows one arrangement.
The assembly of FIG. 6 consists of L in series with separate resistor 3'.
Let's form a C circuit.

これら素子は別個に利用されるか直列か並列に接続して
利用される。第6図の配置は直列のRL回路や別個のコ
ンデンサーを形成する如く接続され、抵抗器として誘導
子の第1巻回部16を形成する。直列RLC回路と別価
の抵抗器とは、第1巻回部16を抵抗器として利用する
ため第6図によつてあたえられ、対向せる端部の巻回部
18は第2コンデスサ一極板30と別個の抵抗器を提供
するため膜30′と関連したコンデンサーの極板として
利用される。第7図では導体層30は誘導子10の端部
の巻回部に接近して配置され、第2導体膜30′は対向
せる端部巻回部18に近接して配置される。
These elements may be used separately or connected in series or parallel. The arrangement of FIG. 6 is connected to form a series RL circuit or a separate capacitor, forming the first turn 16 of the inductor as a resistor. The series RLC circuit and the separately sold resistor are provided as shown in FIG. 6 in order to use the first winding part 16 as a resistor, and the winding part 18 at the opposite end is a second condescender monopolar plate. 30 is utilized as a capacitor plate in conjunction with membrane 30' to provide a separate resistor. In FIG. 7, the conductor layer 30 is placed close to the end turns of the inductor 10, and the second conductor film 30' is placed close to the opposing end turns 18.

第7a図に示す如く、この配置は直列CLC回路と別個
の抵抗器30と31′とを直列若しくは並列に或は別個
に使用するため誘導子10の両端に配置するものであり
又、別の直列若しくは並列の配置における素子として別
の抵抗器3『とLC回路を形成する。第7図の配置は又
直列RL回路と別の抵抗器を形成し若しくは直列RLC
回路を形成する。第8図に示した配置は、第8a図に示
す如く、巻回部16を電気抵抗器として利用することに
より一対の直列LC回路を形成する。
As shown in Figure 7a, this arrangement places a series CLC circuit and separate resistors 30 and 31' across the inductor 10 for use in series, in parallel, or separately. An LC circuit is formed with another resistor 3' as an element in a series or parallel arrangement. The arrangement of FIG. 7 also forms a series RL circuit and a separate resistor or a series RLC circuit.
form a circuit. The arrangement shown in FIG. 8 forms a pair of series LC circuits by utilizing the windings 16 as electrical resistors, as shown in FIG. 8a.

この配置は一対の直列RLC回路をも提供する。いづれ
かの場合に、別の回路が別個に利用されるか若しくは直
列か並列に接続して利用される。
This arrangement also provides a pair of series RLC circuits. In either case, separate circuits are used separately or connected in series or parallel.

さらに導体膜30と30′を電気抵抗器として配置する
と、第8図の配置における如く別個に使用可能であるか
、若しくは種々な直列と並列形態に接続できる一対の抵
抗器と一対の誘導子とが形成できる。第9図の配置では
第8図の素子の再配置を示し、第9a図に示す如く、一
対の別個の誘導子10と10′と別個のコンデンサーを
配置する。これらのコンポネントは別個に利用されるか
種々な直列若しくは並列形態に接続される。又第9a図
に示す如く、誘導子10の端巻回部を抵抗悪として利用
し、反対側の端巻回部18をコンデンサー板として形成
し、導体膜3『を電気抵抗器として利用することによつ
て第9図の配置は直列RL回路と別の直列RLC回路を
形成する。これら素子は別個に利用するか若しくは、直
列又は並列に接続される。さらに導体膜30と3『を電
気抵抗器として利用することによつて、第9図の配置で
は、別個に利用されるか若しくは種々な直列と並列形態
に接続したそれぞれ対をなす誘導子と抵抗器を形成する
Furthermore, if the conductor films 30 and 30' are arranged as electrical resistors, they can be used as a pair of resistors and a pair of inductors, which can be used separately as in the arrangement of FIG. 8 or connected in various series and parallel configurations. can be formed. The arrangement of FIG. 9 shows a rearrangement of the elements of FIG. 8 to provide a pair of separate inductors 10 and 10' and a separate capacitor, as shown in FIG. 9a. These components may be used separately or connected in various series or parallel configurations. Further, as shown in FIG. 9a, the end winding part of the inductor 10 can be used as a resistor, the end winding part 18 on the opposite side can be formed as a capacitor plate, and the conductor film 3' can be used as an electrical resistor. The arrangement of FIG. 9 thus forms a series RL circuit and a separate series RLC circuit. These elements can be used separately or connected in series or parallel. Furthermore, by utilizing the conductive films 30 and 3' as electrical resistors, the arrangement of FIG. Form a vessel.

第10図は導体膜の組立を示し、この膜では層膜30と
3『とがコンデンサー板を形成し、層膜3『は電気抵抗
器として形成される。
FIG. 10 shows the assembly of a conductor membrane in which the layers 30 and 3' form a capacitor plate and the layer 3' is formed as an electrical resistor.

第10a図に示す如く、これらのコンポネントは別々に
利用されるか直列と並列に接続して利用されるかである
。上述のことから本発明は、極めて広範囲の利用が認め
られ別個に或は直列や並列形態で利用できる統合母体の
形態をもつた種々な複合電気コンポネントを形成できる
単純化した構造で廉価な手段を提供できることが理解さ
れよう。
As shown in Figure 10a, these components may be used separately or in series and parallel connections. In view of the foregoing, the present invention provides a simplified and inexpensive means of forming a variety of composite electrical components in the form of an integrated matrix that has a very wide range of applications and can be used separately or in series or parallel configurations. It will be understood that we can provide.

別々の電気コンポネントの接続においてこれまで体験し
た逆効果を除くか減少せしめるかによつて、コンポネン
トを接続する導線はすべて若しくは殆ど除かれる。
All or most of the conductors connecting the components are eliminated, depending on whether the adverse effects previously experienced in connecting separate electrical components are to be eliminated or reduced.

統合母体の物理的寸法は、先行技術によるコンポネント
の寸法より遥に小型になつた。実際我が審査中の特許出
願で開示した製造法を利用すれば、本発明の統合母体は
極めて小型に形成できる。
The physical dimensions of the integrated matrix have become much smaller than those of the prior art components. In fact, by utilizing the manufacturing method disclosed in our patent application under examination, the integrated matrix of the present invention can be made extremely compact.

本発明の精神を逸脱せぬ限り上述した部品の寸法、形態
、型式、数量や配置とその方法に種々な変化を加えるこ
とは本技法に精通した当ノ 業者には明らかであろう。
実施態様 1 電気導体からなる上記多数の層膜の所定数が誘導子の多
数の巻回部を形成するため相互に接続され、巻回部は上
記絶縁材の層膜によつて互に分離する如く配置され、電
気導体からなる上記多数の層膜の1つは上記絶縁材の膜
によつてこれと分離した誘導子の端巻回部の1方にかぶ
せられてコンデンサーの極板を形成し、コンデンサーの
極板に近接する誘導子の端部巻回部はコンデンサーの第
′) 2極板を形成するのに用いられ、一対の電気端子
の1方はコンデンサーの第1極板から延長し他方はコン
デンサーの第2極板を形成する端巻回部に対向した誘導
子の端部巻回部から延長し、これによつて上記一対の端
子間に直列LC回路を形成するが如き上記誘導子とコン
デンサーを含む特許請求の範囲に記載の統合母体の製造
方法。
It will be apparent to those skilled in the art that various changes may be made in the size, form, type, quantity and arrangement of the parts described above without departing from the spirit of the invention.
Embodiment 1 A predetermined number of said multiple layers of electrical conductors are interconnected to form multiple turns of an inductor, the turns being separated from each other by said layers of insulating material. one of the plurality of layers of electrical conductor is placed over one of the end turns of the inductor separated from it by the membrane of insulating material to form the plate of the capacitor; , the end turns of the inductor adjacent to the capacitor plates are used to form the second plate of the capacitor, and one of the pair of electrical terminals extends from the first plate of the capacitor. the other extending from the end turn of the inductor opposite the end turn forming the second plate of the capacitor, thereby forming a series LC circuit between the pair of terminals; A method of manufacturing an integrated matrix as claimed in the claims, including a capacitor and a capacitor.

実施態様 2 電気導体からなる上記多数の層膜所定数が誘導子の多数
の巻回部を形成すべく相互に接続され、上記巻回部は上
記絶縁材の膜によつて互に分離せしめられ上記対をなす
電気導体の多数の膜は上記絶縁材の膜によつてこれとお
互から分離した誘導子の1方の端巻回部にかぶせられて
コンデンサーの極板を形成し、電気端子は誘導子の両端
とコンデンサーの両極板から延長する如く配置され誘導
子とコンデンサーとは別個のコンポネントや直列や並列
の回路として選択的に利用されるが如き上記誘導子とコ
ンデンサーを含む特許請求の範囲に記載の統合母体の製
造方法。
Embodiment 2 A predetermined number of said multiple layers of electrical conductors are interconnected to form multiple turns of an inductor, said turns being separated from each other by said membrane of insulating material. A number of membranes of the paired electrical conductors are placed over one end turn of the inductor separated from each other by the membrane of insulating material to form the plates of the capacitor, and the electrical terminals are Claims that include the above inductor and capacitor, which are disposed so as to extend from both ends of the inductor and the plates of the capacitor, and which are used as separate components or selectively in series or parallel circuits. A method for producing an integrated matrix as described in .

実施態様 3 電気導体からなる上記多数の層膜の所定数が誘導子の多
数の巻回部を形成する如く相互接続され、上記巻回部は
上記絶縁材の膜によつて互に分離され、上記電気導体の
少くとも1方の端巻回路は、残りの巻回部より大きい所
定の電気抵抗をもつ如く形成され、電気端子は両端巻回
路から延長してこれら巻回部間に直列RC回路を形成す
るが如き上記誘導子と抵抗器を含む特許請求の範囲に記
載の統合母体の製造方法。
Embodiment 3 A predetermined number of said multiple layers of electrical conductors are interconnected to form multiple turns of an inductor, said turns being separated from each other by said membrane of insulating material, At least one end-turn circuit of the electrical conductor is formed to have a predetermined electrical resistance greater than the remaining turns, and an electrical terminal extends from the end-turn circuit to form a series RC circuit between these turns. A method of manufacturing an integrated matrix as claimed in the claims, comprising the inductor and resistor forming the inductor and resistor.

実施態様 4 電気導体からなる上記多数の層膜の所定数が誘導子の多
数の巻回部を形成すべき接続され上記巻回部は上記絶縁
材の膜によつて互に分離され、電気導体からなる上記多
数の膜のうちの1つは、上記絶縁材の膜によつてこれか
ら分離した誘導子の1方の端巻回部にかぶせられ、上記
1つの膜は、上記誘導子の巻回部より大きい所定の電気
抵抗をあたえるべく形成され、電気端子が誘導子の両端
と上記1つの膜から延び、誘導子と抵坑器は別個のコン
ポネントや直列回路や並列回路として選択的に利用され
るが如き上記誘導子と抵抗器を含む特許請求の範囲に記
載の統合母体の製造方法。
Embodiment 4 A predetermined number of said multiple layers of electrical conductors are connected to form multiple turns of an inductor, said turns being separated from each other by said membrane of insulating material, said electrical conductor one of the plurality of films consisting of a plurality of films is placed over one end turn of the inductor separated from it by the film of insulating material; electrical terminals extending from both ends of the inductor and from the single membrane, the inductor and resistor being selectively utilized as separate components or in series or parallel circuits. A method of manufacturing an integrated matrix according to the claims, which includes the above-mentioned inductor and resistor.

実施態様 5電気導体の上記多数の対をなす膜は、上記
絶縁材の膜によつて互に分離しコンデンサーの極板を形
成するのに用いられ、電気導体の第3膜が上記絶縁材の
膜によつてこれとは分離した上記コンデンサー極板の1
方にかぶせられ上記コンデンサー極板より大きい所定の
電気抵抗をあたえるべく形成され、これにより電気抵抗
器を形成し電気端子がコンデンサー極板の双方から延び
て上記第3膜を形成し、これによりコンデンサーと抵抗
器は別個のコンポネントや直列や並列回路として選択的
に利用されるが如き上記コンデンサーと抵抗器を含む特
許請求の範囲に記載の統合母体の製造方法。
Embodiment 5 Said multiple pairs of films of electrical conductors are separated from each other by said films of insulating material and are used to form the plates of a capacitor, the third film of electrical conductors being separated from each other by said films of insulating material. one of the above capacitor plates separated from this by a membrane;
The third membrane is formed so as to provide a predetermined electrical resistance greater than the capacitor plates, thereby forming an electrical resistor, and electrical terminals extending from both sides of the capacitor plates to form the third membrane, thereby forming a capacitor. 2. A method of manufacturing an integrated matrix as claimed in claim 1, wherein said capacitor and resistor are selectively utilized as separate components or as a series or parallel circuit.

実施態様 6電気導体からなる上記多数の層膜の第1所
定数が第1誘導子の多数の巻回部を形成するため互に接
続され、上記巻回部は上記絶縁材の膜によつて互に分離
し、電気導体からなる上記多数の層膜の第2所定数が第
2誘導子の多数の巻回部を形成するべく第1誘導子の1
端にかぶせられて互に接続され、上記巻回部は上記絶縁
材の膜によつて互に分離し、電気端子が第1第2誘導子
の両端から延び、上記対をなす誘導子は別個のコンポネ
ントや直列や並列回路として選択的に利用されるが如き
一対の電気導子を含む特許請求の範囲に記載の統合母体
の製造方法。
Embodiment 6 A first predetermined number of said multiple layers of electrical conductors are connected together to form multiple turns of a first inductor, said turns being interconnected by said membrane of insulating material. Separated from each other, a second predetermined number of said plurality of layers of electrical conductor are connected to one of the first inductor to form a plurality of turns of the second inductor.
the turns are separated from each other by the membrane of insulating material, electrical terminals extend from opposite ends of the first and second inductors, and the pair of inductors are separate. A method of manufacturing an integrated matrix as claimed in the claims, comprising a pair of electrical conductors such as those used selectively as a component or in a series or parallel circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明により多数の電気コンポネントを含む統
合母体を提供するため多数の電気コンポネント素子の組
立て法を図示する拡大して示された斜視分解図、第2図
は第1図で示した組立ての電気誘導子コンポネントの好
適な構造を示す横断面図、第3図から第10図までは、
本発明による電気コンポネント素子の種々な配置を示す
側面から見た分解図、第3a図から第10a図まではそ
れぞれ第3図から第10図で示した相応組立から得られ
る単一の直列と並列回路のコンポネント配置を示す概略
電気回路図である。 16・・・・・・端巻回部、18・・・・・・端巻回部
、20・・・・・・絶縁膜、22・・・・・・絶縁膜、
28・・・・・・中央開口部、30・・・・・・導体膜
、32・・・・・・電気端子、34・・・・・・電気端
子、36・・・・・・絶縁膜。
FIG. 1 is an enlarged perspective exploded view illustrating the assembly of multiple electrical component elements to provide an integrated matrix containing multiple electrical components in accordance with the present invention; FIG. 3 through 10 are cross-sectional views illustrating preferred constructions of assembled electrical inductor components.
Exploded views from the side showing various arrangements of electrical component elements according to the invention, FIGS. 3a to 10a respectively a single series and parallel arrangement resulting from the corresponding assembly shown in FIGS. 3 to 10. 1 is a schematic electrical circuit diagram showing the component arrangement of the circuit; FIG. 16... End winding part, 18... End winding part, 20... Insulating film, 22... Insulating film,
28... Central opening, 30... Conductor film, 32... Electric terminal, 34... Electric terminal, 36... Insulating film .

Claims (1)

【特許請求の範囲】[Claims] 1 所定の電気特性を有する多数の電気導体材の薄膜を
1枚ずつ絶縁材の薄膜によつて分離して重ね、前記電気
導体薄膜のうちの所定の薄膜に電気導体端子を接続し該
端子を前記絶縁材の薄膜を通して前記電気導体薄膜から
外向へ延長せしめ、それにより、様々な方法で共に結合
されて様々な形態の回路を形成することが出来るような
種類の電気コンポ※ネントを形成するようにした、多数
の電気コンポネントを含む統合母体の製造方法。
1. A large number of thin films of electrically conductive material having predetermined electrical properties are separated one by one by a thin film of insulating material, and an electrically conductive terminal is connected to a predetermined thin film of the electrically conductive thin films. extending outwardly from the electrically conductive film through the thin film of insulating material, thereby forming electrical components of a type that can be coupled together in a variety of ways to form various forms of circuitry. A method for manufacturing an integrated matrix containing multiple electrical components.
JP49099064A 1974-02-04 1974-08-30 Method of manufacturing an integrated matrix containing a large number of electrical components Expired JPS598054B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43935074A 1974-02-04 1974-02-04
US439350 1974-02-04

Publications (2)

Publication Number Publication Date
JPS50109465A JPS50109465A (en) 1975-08-28
JPS598054B2 true JPS598054B2 (en) 1984-02-22

Family

ID=23744360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49099064A Expired JPS598054B2 (en) 1974-02-04 1974-08-30 Method of manufacturing an integrated matrix containing a large number of electrical components

Country Status (5)

Country Link
JP (1) JPS598054B2 (en)
CA (1) CA1016268A (en)
DE (1) DE2446582A1 (en)
FR (1) FR2260256B1 (en)
GB (1) GB1478354A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62125817U (en) * 1986-02-01 1987-08-10
JP6389998B1 (en) * 2017-11-28 2018-09-19 株式会社野田スクリーン LC resonant element and resonant element array

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5467241U (en) * 1977-10-21 1979-05-12
GB2045540B (en) * 1978-12-28 1983-08-03 Tdk Electronics Co Ltd Electrical inductive device
JPS6031243Y2 (en) * 1980-08-15 1985-09-18 ティーディーケイ株式会社 composite parts
JP3073035B2 (en) * 1991-02-21 2000-08-07 毅 池田 LC noise filter
DE102008004470A1 (en) 2007-12-05 2009-06-10 Rohde & Schwarz Gmbh & Co. Kg Electrical circuit arrangement with concentrated elements in multilayer substrates

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62125817U (en) * 1986-02-01 1987-08-10
JP6389998B1 (en) * 2017-11-28 2018-09-19 株式会社野田スクリーン LC resonant element and resonant element array
WO2019106705A1 (en) * 2017-11-28 2019-06-06 株式会社野田スクリーン Lc resonant element and resonant element array

Also Published As

Publication number Publication date
DE2446582A1 (en) 1975-08-14
FR2260256B1 (en) 1980-04-04
FR2260256A1 (en) 1975-08-29
GB1478354A (en) 1977-06-29
CA1016268A (en) 1977-08-23
JPS50109465A (en) 1975-08-28

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