JPS598000B2 - status detection device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a status detection device.

The status detection device detects the status based on the logical value of the binary status signal.

Therefore, if the logical value of the status signal fluctuates over time due to the influence of noise or the like, an error will occur in the status detection result, so some kind of countermeasure is required. An object of the present invention is to provide a status detection device that has directional hysteresis and operates stably without being affected by temporary fluctuations in a status signal. The present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual block diagram of an embodiment of the present invention. In Figure 1, 1 is a status signal input terminal, 2 is an alarm scanner, 3 and 4 are AND gates, 5 is a counter, and 6
, 7 is a detector, 8 is an alarm flip-flop circuit, and 9 and 10 are a normal signal output terminal and an abnormal signal output terminal, respectively. A status signal is applied to input terminal 1. The status signal is an alarm signal, and when its logical value is "H", it is abnormal, and when its logical value is "L", it is normal. The alarm scanner 2 periodically detects the logical value of the alarm signal and generates an output pulse at the output terminal QB when an abnormality occurs and at the output terminal QA when it is normal. These output pulses are given to the UP input terminal and DOWN input terminal of the counter 5, respectively, and the AND gate 3,
4 to the load terminal and clear terminal of the counter 5, respectively. The counter 5 counts down normal pulses and counts up abnormal pulses. The count value M of the counter 5 is given to detectors 6 and 7, and it is detected whether the count value M has reached zero or a predetermined value N, respectively. The outputs of the detectors 6 and 7 are applied to an alarm flip-flop circuit 8. Alarm flip-flop circuit 8 is set by the front edge of the output of detector 6 and is set by the front edge of the output of detector 7. High level of Q terminal of alarm flip-flop circuit 8
The output is output as an abnormal signal, and the H output of the o terminal is output as a normal signal. The abnormal output and normal output of the alarm flip-flop circuit 8 are applied to AND gates 3 and 4, respectively. The operation of the device configured in this way is as follows.

An explanatory diagram of the operation is shown in FIG. Assume that initially the normal state continues, the count value M of the counter 5 is zero, and the alarm flip-flop circuit 8 has been reset. The alarm flip-flop circuit 8 is reset to produce a normal output from the O terminal. At this time, the AND gate 3 is closed and the AND gate 4 is opened by the output signals from the Q terminal and the O terminal of the alarm flip-flop circuit 8. In this state, when the alarm scanner 2 generates a normal pulse at a certain period, the counter 5 is output through the AND gate 4.
A clear pulse is applied to the counter, thereby clearing the count value, so the count value remains zero. If the input status signal is inverted in such a state, the alarm scanner 2 will generate an abnormal pulse at the output terminal QB accordingly.

This pulse is given to the UP terminal of counter 5, so
The count value M of the counter 5 is no longer zero. While the input status signal indicates an alarm state, the abnormal pulses are counted up in the counter 5 and the count value M increases.
Since the alarm flip-flop circuit 8 is not set until the count value M reaches the predetermined value N, a normal output is generated at the Q terminal. When the count value M of the counter 5 eventually reaches a predetermined value N, the detector 7 detects this and sets the alarm flip-flop circuit 8 to generate an abnormal output at the Q terminal. This confirms the abnormal state.
As the output signal of the alarm flip-flop circuit 8 is changed, the open/closed states of the AND gates 3 and 4 are also changed, so that the AND gate 3 is opened and the AND gate 4 is closed.

If an abnormal pulse continues to come in in this state, a load pulse is given to the counter 5 through the AND gate 3 each time, so that the counter 5 is loaded with a predetermined value N.
is loaded. As a result, the count value of the counter 5 is maintained at N. When the input status signal turns normally, a normal pulse is input to the DOWN terminal of the counter 5, so the count value M of the counter 5 is gradually decreased, and when it reaches zero, the alarm flip-flop is activated by the action of the detector 6. The output of the circuit 8 is inverted to produce a normal output at the Q terminal, and the AND gate 3 is closed and the AND gate 4 is opened, establishing a normal state.

In this way, since abnormality and normality are determined based on the condition that these states have continued for a certain period of time, the state can be detected with a high degree of certainty.

The predetermined value N set in the counter 5 provides hysteresis when changing the established state. The width of the hysteresis is adjusted by choosing the value of N. Now, in such a device, if the alarm scanner 2 generates an abnormal pulse when an abnormal condition is established, a predetermined value N is loaded into the counter 5, and when a normal pulse is generated when the normal condition is established. When this occurs, the count value of the counter 5 is cleared, so some normal parnus may temporarily occur while the abnormal condition is being determined, and the count value of the counter 5 will be cleared.
Even if the count value of counter 5 decreases, if even one abnormal pulse occurs, the count value will be pulled back to N, and some abnormal pulses will temporarily occur while the normal state is being established, and the count value of counter 5 will increase. However, if even one normal pulse occurs, the count value is cleared.

By controlling the count value in this manner, the hysteresis can be given directionality, and emphasis can be placed on ensuring the currently determined state. Although the above is a case where the status signal is an alarm signal, the present invention is generally applicable to status detection when the status is expressed by a binary signal.

As described above, according to the present invention, since directional hysteresis is provided for status detection, highly reliable status detection can be performed without being disturbed by noise or the like.

Due to the hysteresis, temporary status reversals due to noise contamination are ignored, so the same continuous status is not reported over and over again.
Furthermore, since the width and direction of hysteresis can be determined according to the properties of the object to which it is applied, optimal status detection can be performed.

[Brief explanation of drawings]

Figure 1 is a conceptual configuration diagram of an embodiment of the present invention. FIG. 2 is an explanatory diagram of the operation of the apparatus shown in FIG. 1. 1... Status signal input terminal, 2...
...Alarm scanner, 3, 4...And gate, 5...Up-down counter, 6...
...First detector, 7...Second detector, 8...Alarm flip-flop, 9
, 10... Output terminal.

Claims (1)

[Claims] 1. A scanner that periodically generates two types of output pulses corresponding to the logical value of an input binary signal, one of the two types of output pulses of this scanner is input to the UP terminal and counted up. an up/down counter that counts down by inputting the other of the two types of output pulses to the DOWN terminal;
A first and a second detector each detect that the count value of the up/down counter becomes zero or a predetermined value greater than zero and transmit a signal, and the output terminal of the first detector is a reset input terminal. a flip-flop circuit connected to the second detector, the output terminal of the second detector is connected to the set input terminal, and outputs each of the binary signals as a determined status from the set output terminal and the reset output terminal; a set of the flip-flop circuits; a first AND gate whose output terminal is connected to a load terminal for setting a predetermined value of the up/down counter; A status detection device having two inputs, a reset side output and the other of the two types of output pulses of the scanner, and a second AND gate whose output terminal is connected to a clear terminal for setting the up/down counter to zero. .