JPS5819118B2 - status detection device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a status detection device.

The status detection device detects status based on the logical value of the binary status signal.

For this reason, if the logical value of the status signal changes temporarily due to the influence of noise, an error will occur in the status detection result, so some countermeasure is required.

An object of the present invention is to provide a status detection device that has directional hysteresis and operates stably without being affected by temporary fluctuations in a status signal.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual block diagram of an embodiment of the present invention.

In Figure 1, 1 is a status signal input terminal, 2 is an alarm scanner, 3 and 4 are inhibit gates, 3
1.41 is a pulse multiplier, 32, 33°42.
43 is an AND gate, and 3.4 and 44 are OR gates.

5 is a counter, 6 and 7 are detectors, 8 is an alarm flip-flop circuit, and 9 and 10 are normal signal output terminals and abnormal signal output terminals, respectively.

The status signal is applied to input terminal 1.

The status signal is an alarm signal, and when its logical value is rHJ, it is abnormal, and when it is "L", it is normal.

The alarm scanner 2 periodically detects the logical value of the alarm signal and generates an output pulse at the output terminal QB when an abnormality occurs and at the output terminal QA when it is normal.

The abnormal pulse of alarm scanner 2 is detected by AND gate 3.
2 and also to an AND gate 33 through a pulse multiplier 31.

The pulse multiplier 31 increases the number of input pulses to K (>1
).

AND gates 32 and 33 are opened and closed by the normal output and abnormal output of alarm flip-flop circuit 8, respectively, and pass pulses to OR gate 34 and inhibit gate 3.
is applied to the UP terminal of the counter 5 through the UP terminal of the counter 5.

The normal pulse of alarm scanner 2 is AND gate 42
It is also applied to the AND gate 43 through the pulse multiplier 41.

AND gates 42 and 43 are opened and closed by the abnormal output and normal output of alarm flip-flop circuit 8, respectively, and pass pulses to OR gate 44 and inhibit gate 4.
It is applied to the DOWN terminal of the counter 5 through the DOWN terminal of the counter 5.

The counter 5 counts down normal pulses and counts up abnormal pulses.

The count value M of the counter 5 is given to the detector 6.1,
It is detected whether each value becomes zero or a predetermined value N.

The output of the detector 6.1 is applied to an alarm flip-flop circuit 8.

Alarm flip-flop circuit 8 is reset by the front edge of the output of detector 6 and set by the front edge of the output of detector 7.

The output of the detector 6.7 is also the inhibit gate 4,
3 are given respectively.

The Q output of the alarm flip-flop circuit 8 is output as an abnormal signal, and the -Q output is output as a normal signal.

The operation of the device configured in this way is as follows.

An explanatory diagram of the operation is shown in FIG. It is assumed that initially the normal state continues, the count value M of the counter 5 is between zero and N, and the alarm flip-flop circuit 8 has been reset.

The alarm flip-flop circuit 8 produces a normal output by being reset.

At this time, AND gates 32 and 43 are opened by the output of alarm flip-flop circuit 8', and AND gates 33 and 42 are closed.

Since the count value M of the counter 5 is between zero and N, both inhibit gates 3 and 4 are open.

When the alarm scanner 2 generates an abnormal pulse in this state, it is applied to the UP terminal of the counter 5 through the AND gate 32, the OR gate 34, and the inhibit gate 3, so that the count value M increases by one.

The abnormal pulse is simultaneously multiplied by the pulse multiplier 31, but since the AND gate 33 is closed, it is not applied to the counter 5.

While the input status signal indicates an alarm state, abnormal pulses are counted up in the counter 5 and the count value M increases.

Since the alarm flip-flop circuit 8 is not set until the count value M reaches the predetermined value N, a normal output is generated.

In other words, there is a hysteresis corresponding to N for determining an abnormal state.

Here, when the status signal is temporarily reversed due to noise or the like and the alarm apparently disappears, the alarm scanner 2 generates a normal pulse, so this pulse is multiplied by the pulse multiplier 41, and the AND gate 43, It is applied to the DOWN terminal of the counter 5 through the OR gate 44 and the inhibit gate 4.

Therefore, the count value M of the counter 5 is pulled back by K.

This makes the return to the currently established normal state twice as sensitive as reversing it.

When the alarm condition is real, abnormal pulses occur frequently, so despite this pullback,
The count value M of the counter 5 eventually reaches a predetermined value N.

Then, the detector 7 detects it and an alarm is generated.
The flip-flop circuit 8 is set to generate an abnormal output to determine the abnormal state.

When the abnormal state is determined, the AND gates 32, 33,
The open/close states of 42 and 43 are alternated, and an abnormal pulse is given to the UP terminal of the counter 5 after being multiplied by the pulse multiplier 31, and a normal pulse is given to the DOWN terminal without any multiplication factor.

Therefore, the counter 5 counts down by 1 for each normal pulse, but counts up by K for each abnormal pulse.

Therefore, the count value M is K every time an abnormal pulse occurs.
It is pulled back towards the predetermined value N.

That is, once an abnormal state has been determined, returning to that state is performed with twice the sensitivity than reversing the state.

In this way, counting control of the counter 5 is performed with emphasis on the currently determined state.

In this device, the directionality of the hysteresis can be adjusted by the multiplier of the pulse multiplier 31, 41.

When K=1, the hysteresis is non-directional, and when K=N, the hysteresis is strongest.

In this way, even if the reliability of the input status signal is low due to noise contamination, etc., the status is determined based on which of the normal and abnormal states is shown more frequently, so the status judgment can be made accurately without being confused by noise etc. I can do it.

The predetermined value N set in the counter 5 provides hysteresis when changing the established state.

The width of the hysteresis is adjusted by choosing the value of N.

1 By exchanging the control signals of the AND gates 32 and 43 with the control signals of the AND gates 33 and 42, the direction of the hysteresis can be reversed and counter control can be performed with emphasis on the new state.

An explanatory diagram of the operation in this case is shown in FIG.

Although the above is a case where the status signal is an alarm signal, the present invention is generally applicable to status detection when status is expressed by a binary signal.

As described above, according to the present invention, directional hysteresis is provided for status detection, so that dust status detection can be performed with high reliability without being disturbed by noise.

Due to the hysteresis, temporary status reversals due to noise contamination are ignored, so that continuous ν statuses with the same content are not reported over and over again.

Furthermore, since the width and direction of hysteresis can be determined according to the properties of the object to which it is applied, optimal status detection can be performed.

[Brief explanation of drawings]

1 FIG. 1 is a conceptual block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams of the operation of the apparatus shown in FIG. 1. 1...Input terminal, 2...Alarm scanner, 3.4...Inhibit gate, 31
, 41...1 pulse multiplier, 32, 3
3,42.43...and gate, 34.44
...Or gate, 5...Counter, 6
, 7...Detector, 8...Alarm flip-flop circuit, 9, 10...Output terminal.

Claims (1)

[Claims] 1. A scanner that periodically generates two types of output pulses corresponding to the logical values of a human-powered binary signal; an up/down counter that counts up one of the two types of output pulses and counts down the other; First and second detectors detect when the count value of this up/down counter becomes zero or a predetermined value greater than zero, respectively, and emit a signal. The output of the first detector is connected to the reset input terminal. a flip-flop circuit connected to the scanner, the output of the second detuffter being connected to a set input/terminal, and outputting each of the binary signals as a determined status from the set output terminal and the reset output terminal; and two types of outputs of the scanner. two six-pulse multipliers each multiplying the pulses (K>1); a first AND for ANDing one of the two output pulses of the scanner with one of the two outputs of the flip-flop circuit; a second AND gate for ANDing one of the output pulses of the scanner multiplied by the pulse multiplier with the other of the two outputs of the flip-flop circuit; these first and second AND gates; a first OR gate for calculating the logical sum of the output pulses of the first OR gate, the output of the first OR gate is connected to the input terminal, the output terminal is connected to the UP terminal of the up/down counter, and the output of the second detector is connected to the output terminal of the first OR gate; a first inhibit gate that is controlled to be closed by a third AND gate that calculates the logical product of the other of the two types of output pulses of the scanner and the other of the two outputs of the flip-flop circuit; a fourth AND gate for ANDing the other of the output pulses of the scanner multiplied by the pliers with one of the two outputs of the flip-flop circuit; the logic of the output pulses of these third and fourth AND gates; a second OR gate for calculating the sum, and an output of the second OR gate is connected to an input terminal, an output terminal is connected to a DOWN terminal of the up/down counter, and is controlled to be closed by the output of the first detector; A status detection device comprising: a second inhibit gate configured to be inhibited;