JPS5979886A - Motor drive circuit of time piece - Google Patents

Abstract

PURPOSE:To reduce the current consumption of a time piece motor without making the chip area of an integrated circuit too large, by always holding voltage applied to the motor in the vicinity of the min. driving voltage of the motor. CONSTITUTION:Voltage applied to the coil of a motor 10 is detected through a voltage difference circuit 12 and the ON-resistance of MOSFET for amplification of a drive circuit 18 is made variable by the positive and negative of the value obtained by subtracting the min. driving voltage of the motor 10 from the detected voltage to control the voltage applied to the motor 10. By this method, the voltage applied to the motor 10 is always kept constant at the min. driving voltage of the motor 10 and current consumption can be reduced. In addition, it is unnecessary to use a regulator and the formation of an integrated circuit is performed only by dividing the gate in a conventional drive circuit and the increase of a chip area can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention prevents unnecessary increases in current consumption of a watch motor due to fluctuations in the power supply voltage of the watch without significantly increasing the area of the watch integrated circuit.

Great efforts have been made to reduce the current consumption of watch motors, and several proposals have been made.

This is because the current consumption of the watch motor is the largest among the watch circuits, and furthermore, the current consumption of the watch motor is greatly influenced by the magnitude of the power supply voltage.

For this reason, watch motors are designed so that even if the power supply voltage drops to a certain extent, enough current flows to drive the motor, so when the power supply voltage is unavoidably high, the current consumption that flows unnecessarily to the motor increases. I was supposed to do it. As a result, the torque of the motor becomes larger than necessary, causing background noise.

In order to solve these problems, it has been proposed to use a regulator to control the voltage applied to the motor, but when the regulator is integrated into an integrated circuit,
It was expected that the chip area would be the same as that of Kana 9, which was not very desirable.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to eliminate wasteful current consumption of a watch motor without increasing the chip area of an integrated circuit too much.

In order to achieve the above object, the present invention detects the voltage applied to both ends of the coil of a watch motor and compares it with the minimum driving voltage of the motor, and if the voltage applied to both ends of the coil is high, the voltage applied to both ends of the coil? If the voltage is low, the voltage applied to both ends of the coil is increased, and the voltage applied to both ends of the motor coil is controlled to be around the minimum driving voltage of the motor. All features are reduced current consumption.

The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Reference signal generator 29 frequency divider circuit 4. It generates pulses for operating the waveform shaping circuit. Of these, the clock driving pulse 6a from the waveform shaping circuit 6 and 64 from the frequency dividing circuit 4
The Hz signal 4a and the 1281-■z signal 4b are input to the timing signal generation circuit 8.

The timing signal generation circuit 8 outputs a timing signal 8b that determines the operation timing of the voltage difference detection circuit 12 that detects the voltage applied to the motor 1o, and a voltage control signal that outputs a non-voltage control signal 14a that controls the voltage applied to the motor 10. This circuit outputs the pulse signal 8a to the generation circuit 14. The voltage difference detection circuit 12 converts the voltage applied to the motor 10 into a digital signal and inputs the signal 12a to the comparison circuit 16.

The comparison circuit 16 compares the minimum drive voltage value of the motor stored as a digital value with the digital signal from the voltage difference detection circuit 12, and determines whether the voltage applied to the motor 1o is higher or lower than the minimum drive voltage of the motor. To detect. Based on the outputs 16a and 16b from the comparison circuit 16, the voltage control signal generation circuit 14 changes the on-resistance of the FET in the drive circuit 18 to apply voltages 18a and 18b' to the motor 10,
A voltage control signal 14a for changing y is output.

FIG. 2 shows a detailed circuit diagram of the timing signal generation circuit 8 in FIG. 1, and FIG. 3 shows its time chart.

The clock driving pulse 6a from the waveform shaping circuit 6 is input to the D input of a flip-flop knob (hereinafter referred to as FF) 24 via an inverter 20.22. Q output 24 of FF24
b is input to one side of the AND gate 26, and the AND gate 2
6 is also inputted with the output 20a of the inverter 20. The pressure signal 8b of the AND gate 26 is input to the voltage difference detection circuit 12 and the D input of the FF 28. The Q output 28a of the FF 28 is input to the D input of the FF 30 and one of the AND gate 32. The Q output 30b of the FF 30 is also input to the AND gate 32, and the output 8a of the AND gate 32 is input to the voltage control signal generation circuit 14.

On the other hand, the clock input of FF24 is 6 from the frequency divider circuit 4.
A 4Hz signal 4a is input, and a 128Hz signal 4b via an inverter 34 is input to the clock input terminals of the FFs 28 and 30.

The entire operation of this circuit will be explained below.

When the clock driving pulse is generated and the output 6a falls from H to L, the output 20a changes from L to H, and an L signal is input to the D input of the FF 24. After this, when the 64 Hz signal 4a falls, the Q output signal 24b of the FF 24 changes from L to H.

After this, the clock driving pulse disappears and the output 6a changes from L to H.
, the output 20a changes from I-1 to L, and the FF
The signal I() is input to the D input of 24.

After this, when the 64I-1z signal 4a falls, FF2
The Q output signal 24b of FF 24 goes from H to L. As a result, the output 8b of the AND gate 26 has the Q output 24b of the FF 24.
A positive single pulse that goes high is generated from when the output 20a of the AND gate 20 goes low until the output 20a of the AND gate 20 goes low.

The positive single pulse obtained on output 8b is input to the D input of FF28. After this, when the 128 Hz signal 4b rises, the Q output 28a of the FF 28 rises to H, and after the positive single pulse of the output 8b falls, it becomes 128 Hz again.
When the 8 Hz signal 4b rises, the Q output 28a falls to L. As a result, the Q output 28a of the FF 28 has an output of 8
A positive single pulse whose phase lags that of b is generated. This Nokurusu is input to the D input of FF30, and after this 12
When the 8Hz signal 4b rises, the output 30b (l-j:
From I-I to L. As a result, the output 8a of the AND gate 32 shows the F after the Q output 28a of the FF 28 becomes H.
A positive single pulse that becomes H is generated until the output 30b of F30 becomes L.

In this manner, the timing signal generating circuit 8 generates a positive single pulse at the outputs 8a and 8b each time a clock driving pulse is input.

FIG. 4 is a detailed circuit diagram of the voltage difference detection circuit 12 and comparison circuit 16 in FIG. 1.

Both ends 18a and 18b of the motor IO are input to transmission gates 36 and 38 in the voltage difference detection circuit 12, respectively. The output of the transmission gate 36 is input to the A-D converter 40, and the output of the transmission gate 38 and the outputs of the barks 40 and 42 are input to the subtraction circuit 44. This is a circuit that subtracts the digitally converted voltage value from , and outputs the voltage value applied to both ends of the coil of motor 0 as a digital value. The subtraction output 12a of this subtraction circuit 44 is input to subtraction circuits 46 and 48 in the comparison circuit 16. Subtraction circuit 4
6.48 also stores the minimum drive voltage value of motor 0 as a digital value, and the output of motor reference voltage 50 is input, and the subtraction circuit 46 inputs the output from the subtraction circuit 44 to both ends of the coil of motor o. This is a circuit that subtracts the minimum driving voltage value of the digital value from the motor reference voltage 50 from the voltage value converted into a digital signal. This is a circuit that subtracts the drive voltage value and a certain digital value. If the calculation results of both the calculation circuits 46 and 48 are positive, the output signals 16a and 16b become [■], and if the calculation results are negative, the output signals 16a and 16b become L.

On the other hand, the output 8b from the timing signal generation circuit 8 is input to the gates of the transmission gates 36 and 38 via the inverter 51 or directly. Transmission gate 36°38 output 8b signal is H
A-D converters 40 and 42 are activated only when
The voltage value applied to each terminal of the motor IO is made conductive. Therefore, the comparison between the voltage applied to the motor 10 and the lowest drive voltage of the motor 10 in the comparison circuit 16 described above is performed using the output 8.
This is performed only when b rises to H.

FIG. 5 is a detailed circuit diagram of the voltage control signal generation circuit 14 and drive circuit 18 in FIG. 1.

The output 16a from the comparison circuit 16 is input to the up/down counter 54 via the inverter 52 in the voltage control signal generation circuit 14. Also, the output 1 of the comparison circuit 16
6b is input to the down input of the amplifier down counter 54. The output signals 16a and 16b are also input to an exclusive NOR gate 56. The output 56a of this exclusive NOR gate 56 is input to a Nantes gate 58, and an output signal 8a from the timing signal generation circuit 8 is also input to the Nantes gate 58.
The output 58a of the Nant gate 58 is input to the clock input 1 of the up/down counter 54.

Count output 14a+ of this up/down counter 54
, 14a2.14as and 14a+ are input to andmate groups 60.62 within drive circuit 18, respectively.

Further, an initial reset circuit 59 is connected to the set input S of the up/down counter 54, and generates a positive single pulse when a power battery (not shown) is turned on. Count output 14a+ of counter 54.

Signal 14a2.14as, No. 1 of 14a< is (H, H,
tI.

H).

On the other hand, at the input of the AND gate group 60, there is also a waveform shaping circuit 6.
The output 6a from the waveform shaping circuit 6 is input to the AND gate group 62, and the output 61 from the waveform shaping circuit 6 is also input to the AND gate group 62. Each output 60a of the AND gate group 60.

60b, 60c, 60d are each N-MOSFET
64a, 64b, 64c, and 64d, and each output 62a of the AND gate group 62.

62b, 62c, and 62d are each N-MO8F E
T 66 a, 66 b, 66 c, 6
6 Enter in d. This N-MOSFET64a, 64
b, 64c.

64d are connected in parallel, each drain has a P-MOSFE
The drain of T68 is connected and the N-MOSFE
T66a, 66b, 66c, and 66d are also connected in parallel, and the drain of P-MOSFET70 is connected to each drain. The output 6a is input to the gate of the P-MOSFET 68, and the output 18a is input from the drain to the motor 1.
Enter 0.

Output 6b is still input to the gate of P-MOSFET 70, and output 18b is input to motor 10 from its drain.

The operation of this circuit will be explained below using the time charts of FIGS. 6(a) and 6(b).

FIG. 6(a) is a time chart when the voltage applied to both ends of the coil of the motor 1O is high.

When the power supply is turned on, the up/down counter 5
4 outputs 14 a+, 14at, 14as, 14
a+.

The A word is (I(, H, T-1, H). Then, every time a clock driving pulse is generated, a positive single pulse is obtained at the output 8a, and the voltage difference detection circuit 12.
The comparison circuit 16 detects whether the voltage value applied to the motor 10 is higher or lower than a predetermined value, and when the voltage value is high, the output 16a of the subtraction circuit 46 and the output 16b of the subtraction circuit 48 in the comparison circuit 16 are becomes H every time a clock drive pulse is generated. Output 52a of this inverter 52
changes from II to L every time a clock drive pulse is generated, and the signal id II is input to the down input, so the up/down counter 54 becomes a down counter only at this time. At the same time, the output 56a of the exclusive NOR gate 56 becomes I-I, the Nante gate 58 opens, and the up/down counter 54 outputs 8a.
Count on the pulses obtained. As a result, every time the pulse of output 8a rises, output 14a114 a2.14
as+ 14 a4 is ()-I, H, H, H)→ (
L, I-I, I-1, I-I)
→ (1-1, L, H, H) → (L.

L, H, I-I), and along with this, N-MO8F
E 'l'' 64 a and 66a are on → off → on Sakaki off.

The N-MOSFETs 64b and 66b are turned on and off, and the other N-MOSFETs 64b and 66b remain on and do not change. These N MOSFETs64a-64
The ratio of the on-resistance of d is 1/2: 1/4: 1/8: 1/16 when the total sum is 1, and the same is true for N-MOSFETs 66a to 66d. . Therefore, each time the up/down counter 54 counts down, the N-MO'5FET group 64.66
The total on-resistance increases, and the voltage applied to the coil of the motor lO decreases.

When the voltage applied to the coil of the motor 10 reaches a predetermined value, the output 16b no longer generates a pulse even if a clock drive pulse occurs. As a result, when a pulse is generated at the output 8a, the output 56a of the exclusive NOR gate 56 becomes L, which closes the Nant gate 58 and prevents the pulse from the output 8a from being input to the up/down counter 54. Therefore, from this point on, the voltage applied to the motor IO becomes a constant value.

After this, when the voltage of the power supply battery decreases to below the set value, the signals of the outputs 16a and 16b become L as shown in FIG. 6(b). Therefore, the output 52a of the inverter 52 is H
Therefore, the up/down counter 54 becomes an amplifier counter. At this time, the output 56a of the exclusive NOR gate 56 becomes I-1, so the Nants gate 58 is opened and the up/down counter 54 counts the pulses obtained at the output 8a. As a result, each time the pulse of output 8a rises, outputs 14a+, 14a2.14as, 14a4
B (L+L, I(, H) → (H, L, H, H) → (
L, T-1°H, H) → (H, H, H, H) changes,
Along with this, N-MOSFET64a and 66a change from off → on → off → on, and N-MO8FgT64b
and 66b change from off to on, and other N-MOS
The FET remains on and does not change. Therefore, every time the up/down counter 54 is counted up, N-M
The total on-resistance of the O8FET group 64, 66 gradually decreases, and the voltage applied to the coil of the motor 10 increases.

When the voltage applied to the coil of the motor IO reaches a predetermined value, the output 16a becomes H when a clock driving pulse is generated, the output 52a of the inverter 52 becomes L, and the output 56a of the exclusive gate 56 also becomes L. This completely prevents the pulse of the output 8a from being input to the up/down counter 54. As a result, the voltage applied to the motor IO becomes a constant value.

According to this embodiment, the entire voltage applied to the coil of the motor 10 is detected, and depending on whether the value obtained by subtracting the minimum drive voltage of the motor 10 from this voltage is positive or negative, the amplification MOS FET of the drive circuit 18 is turned on. Motor l by varying the resistance
The voltage applied to O is controlled. For this reason, the motor 10
The voltage applied to the motor 10 is always constant at the minimum drive voltage of the motor 10, eliminating unnecessary current consumption, reducing background noise, and extending the life of the battery. In addition, there is no need to use it as a regulator as in the past, and when it is integrated into an integrated circuit, it is only necessary to divide the gate in the conventional drive circuit, so the chip area does not increase much.

As described above, according to the present invention, the voltage applied to the motor is compared with the minimum drive voltage of the motor, and the voltage applied to the motor is always kept close to the minimum drive voltage of the motor, thereby reducing wasteful current consumption of the motor. This also makes it possible to reduce background noise. This also extends the life of the power source battery. Also, as before,
Not only does it not require the use of a regulator, but even if it is integrated into an integrated circuit, it is only necessary to divide the gate in the current drive circuit, which has the advantage that the chip area does not increase significantly.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention. 2 is a detailed circuit diagram of the timing signal generation circuit shown in FIG. 1; and FIG. 4 is a detailed circuit diagram of the voltage difference detection circuit and comparison circuit shown in FIG. FIG. 5 is a circuit diagram of the voltage control signal generation circuit and drive circuit in FIG. 1. 6(a) and 6(b) are time charts of FIG. 5. 8... Timing signal generation circuit, 10... Motor, 12... Voltage difference detection circuit, 1
4... Voltage control signal generation circuit, 16... Comparison circuit, 18... Drive circuit, 40.42.
...A-D converter, 44, 46, 48... Subtraction circuit, 50... Motor reference voltage, 54... Up/down counter. that's all

Claims (1)

[Claims] (1) The time is determined by driving the motor to rotate using the time reference pulse. The display clock includes a voltage detection circuit that detects the voltage applied to the motor coil using a digital signal;
a comparator circuit that compares the digital signal with a digital signal representing a minimum drive voltage of the motor to detect whether the voltage applied to the coil of the motor is higher or lower than the minimum drive voltage of the motor; A voltage control signal generation circuit that outputs a voltage control signal to control the voltage applied to the motor; and a voltage control signal generation circuit that outputs a voltage control signal to control the voltage applied to the motor; a drive circuit that reduces the applied voltage and increases the voltage when it is lower than the minimum drive voltage; and a timing signal generation circuit that generates a timing signal to operate the voltage detection circuit based on the time reference pulse. A clock motor drive circuit characterized by: