JPS5979578A - Low voltage zener diode and manufacture thereof - Google Patents
Low voltage zener diode and manufacture thereofInfo
- Publication number
- JPS5979578A JPS5979578A JP18900182A JP18900182A JPS5979578A JP S5979578 A JPS5979578 A JP S5979578A JP 18900182 A JP18900182 A JP 18900182A JP 18900182 A JP18900182 A JP 18900182A JP S5979578 A JPS5979578 A JP S5979578A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- junction
- type
- zener diode
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 33
- 238000005468 ion implantation Methods 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 238000005245 sintering Methods 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は低電圧ツェナーダイオードおよびその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to low voltage Zener diodes and methods of manufacturing the same.
低電圧ツェナーダイオードは低いツェナー電圧（Ｖ ）
を得るために急峻な不純物濃度勾配構造を必要とする、
このだめ、第１図に示すように、ツェナーダイオードは
ｎ”形のシリコン基板１の主面に設けられた低抵抗のｎ
＋＋形エピタキシャル層２＜ ３／１０００〜４／１０
００Ω−Ｃｒｎ）の表層部に深さが数１００＾と浅いボ
ロン拡散を施してｐ＋形拡散層３を形成し、不純物濃度
勾配が１０ ｃｍ−’以上と急峻となるようにしてい
る。−！だ、この素子は表面および接合周辺でのブレー
クダウンを抑えるためにｐ＋形拡散層３の外周部にｐ＋
＋形のガードリング４を設けている。まだ、ｐ＋形拡散
層３上にはタングステン（Ｗ）、クロム（Ｃｒ）。Low voltage Zener diodes have low Zener voltage (V)
requires a steep impurity concentration gradient structure to obtain
In this case, as shown in FIG. 1, the Zener diode is a low-resistance n
++ type epitaxial layer 2 < 3/1000 to 4/10
The p+ type diffusion layer 3 is formed by shallow boron diffusion to a depth of several 100^ in the surface layer of 00Ω-Crn), so that the impurity concentration gradient becomes steep at 10 cm-' or more. -! However, in order to suppress breakdown on the surface and around the junction, this element has a p+
A +-shaped guard ring 4 is provided. Tungsten (W) and chromium (Cr) are still on the p+ type diffusion layer 3.
銀（Ａｇ）を順次積層形成してアノード電極５が形成さ
れている。なお、露出する接合部分およびｎ＋＋形エピ
タキシャル層２の表面は絶縁膜６で被われている。また
、下面にはカソード電極７が設けられている。The anode electrode 5 is formed by sequentially laminating silver (Ag). Note that the exposed junction portion and the surface of the n++ type epitaxial layer 2 are covered with an insulating film 6. Further, a cathode electrode 7 is provided on the lower surface.
しかし、このような従来の低電圧ツェナーダイオードは
ツェナー電圧の不均一、コンタクト電極の接合突き抜け
によるショート、逆方向電流（工。）不良、サージ電流
匠よる接合破壊等の問題を引き起している。However, such conventional low-voltage Zener diodes cause problems such as uneven Zener voltage, short circuits due to contact electrode junction penetration, reverse current (engineering) defects, and junction breakdown due to surge currents. .
これらの問題について本発明者が検討して見ると、つぎ
のようなことが明らかとなった。When the present inventor studied these problems, the following became clear.
前記ツェナー電圧の不均一は、第２図の従来品における
不純物濃度曲線（縦軸；不純物濃度Ｎ（ｘ）対数軸、横
軸；拡散深さ）に示すように、不純物濃度勾配を大きく
するために、接合深さＸｊを０．０２〜０．０４μｍと
浅くすることに原因がある。The non-uniformity of the Zener voltage is caused by increasing the impurity concentration gradient, as shown in the impurity concentration curve (vertical axis: logarithmic axis of impurity concentration N(x), horizontal axis: diffusion depth) in the conventional product in Figure 2. Another reason is that the junction depth Xj is made shallow to 0.02 to 0.04 μm.
即ち、浅い接合形成のためボロン拡散時間（ボロンデポ
ジット時間）を９００Ｃ前後で数分と極めて短時間にす
る必要があるため、ボロンのデポジット量のばらつきが
相対的に大きくなることによる。ボロンのデポジット量
の均一化を図るにはデポジット時間を長くすればよいが
、時間を長くすると接合深さが深くなシかつ不純物濃度
勾配が緩かになってしまい頭書の目的が果せなくなる。That is, since it is necessary to make the boron diffusion time (boron deposit time) extremely short, such as several minutes at around 900 C, in order to form a shallow junction, the variation in the amount of boron deposited becomes relatively large. In order to make the amount of boron deposited uniform, it is possible to lengthen the deposition time, but if the deposit time is lengthened, the junction depth becomes deep and the impurity concentration gradient becomes gentle, which defeats the purpose mentioned in the introduction.
また、前記コンタクト電極の接合突き抜け、↓８不良、
サージ電流による接合破壊も接合深さを深くすればその
発生は防止できるが、前述のように接合深さを深くする
ことは急峻な不純物濃度勾配が得られなくなることにな
ってしまう。In addition, the contact electrode bond penetration, ↓8 defect,
Junction breakdown due to surge current can be prevented by increasing the junction depth, but as described above, increasing the junction depth makes it impossible to obtain a steep impurity concentration gradient.
このため、従来のツェナーダイオード構造およびその製
造方法では量産安定性が悪く、歩留の低下によるコスト
高騰となってしまう。For this reason, conventional Zener diode structures and manufacturing methods have poor mass production stability, resulting in lower yields and higher costs.
また、前記対策として、ドープド・ポリシリコンを接合
上に設けた構造もあるが、量産安定性の点で問題がつき
まとっている。Further, as a countermeasure to the above, there is a structure in which doped polysilicon is provided on the junction, but this is still problematic in terms of mass production stability.
したがって、本発明の目的は接合深さが従来よシも深く
かつ不純物濃度勾配が急峻となる低電圧ツェナーダイオ
ードおよびその製造方法を提供することによって、特性
の安定１歩留の向上、生産コストの低減を図ることにあ
る。Therefore, an object of the present invention is to provide a low-voltage Zener diode with a deeper junction depth and a steeper impurity concentration gradient than before, and a method for manufacturing the same, thereby stabilizing characteristics, improving yield, and reducing production costs. The aim is to reduce
このような目的を達成するために本発明は、第１導電形
層の表層部に部分的に第２導電形層が設けられてなる低
電圧ツェナーダイオードにおいて、前記第１導電形層と
第２導電形層が作る接合よシも深い位置に不純物濃度ピ
ークが位置する第１導電形からなるイオン打込層が設け
られてなるものであシ、製造にあっては、第２導電形層
の形成前にイオン打込層を形成するものである。また、
よシ具体的には、たとえば接合深さは０．１〜０．２μ
ｍ、イオン打込層の不純物濃度ピークの深さは０１２〜
０．２５μｍである。In order to achieve such an object, the present invention provides a low-voltage Zener diode in which a second conductivity type layer is partially provided on the surface layer of a first conductivity type layer. An ion-implanted layer of the first conductivity type with an impurity concentration peak located deep in the junction formed by the conductivity type layer is provided during manufacturing. An ion implantation layer is formed before the formation. Also,
Specifically, for example, the bonding depth is 0.1 to 0.2μ.
m, the depth of the impurity concentration peak of the ion implantation layer is 012~
It is 0.25 μm.
以下、実施例によυ本発明を説明する。The present invention will be explained below with reference to Examples.
第３図（ａ） 、 （ｂ＋ｉ本発明の一実施例による低
電圧ツェナーダイオードの製造方法を示すワークの断面
図、第４図は同じく不純物濃度曲線を示すグラフである
。FIGS. 3(a) and (b+i) are cross-sectional views of a workpiece showing a method of manufacturing a low-voltage Zener diode according to an embodiment of the present invention, and FIG. 4 is a graph similarly showing an impurity concentration curve.
この実施例における低電圧ツェナーダイオードの製造に
あっては、第３図（ａ）に示すように 、＋形のシリコ
ン基板１を用意する。このシリコン基板１の上面にはｎ
＋＋形のエピタキシャル層２が設けられている。このエ
ピタキシャル層２は、たとえば、３／１０００〜４／１
０００Ω−画と低抵抗の層となっている。そこで、この
エピタキシャル層２の表層部中央にｎ導電形決定不純物
、たとえばイオン打ち込みが深くなる傾向のリン（Ｐ）
をイオン打込みによって打ち込みイオン打込層８を形成
する。この際、イオン打込みを施さないエピタキシャル
層２の底面は絶縁膜９で被っておく。In manufacturing the low-voltage Zener diode in this embodiment, a +-type silicon substrate 1 is prepared as shown in FIG. 3(a). On the upper surface of this silicon substrate 1, n
A ++-type epitaxial layer 2 is provided. This epitaxial layer 2 is, for example, 3/1000 to 4/1
It has a low resistance layer of 000Ω. Therefore, in the center of the surface layer of this epitaxial layer 2, impurities that determine the n conductivity type, such as phosphorus (P), which tends to be deeply ion implanted, are added.
An ion implantation layer 8 is formed by ion implantation. At this time, the bottom surface of the epitaxial layer 2 that is not subjected to ion implantation is covered with an insulating film 9.
つぎに、第３図（ｂ）に示すように、前記イオン打込層
８部分にｐ導電形決定不純物、たとえばボロン（Ｂ）を
デポジションさせて拡散する。この場合、デポジション
は９００ｔＺ’前後で数十分程度性ない、ｐ＋形拡散層
３を形成しｐ、ｎ接合を形成する。Next, as shown in FIG. 3(b), a p conductivity type determining impurity, such as boron (B), is deposited and diffused into the ion implantation layer 8 portion. In this case, the deposition is about 900 tZ', which is about several tens of minutes, to form a p+ type diffusion layer 3 and form a p and n junction.
この両工程において、ｐｎ接合の深さＸｊはイオン打込
層８のイオンの飛程のピーク（不純物濃度ピーク）ＲＰ
よシも浅い位置となるようにイオン打込みエネルギーや
不純物拡散の条件を設定する。In both of these steps, the depth Xj of the pn junction is determined by the peak range of ions (peak impurity concentration) RP
The ion implantation energy and impurity diffusion conditions are set so that the depth is also shallow.
たとえば、イオン打込みエネルギーを１００Ｋｅｙとす
れば、ＲＰば０．１２ ｆｉ ｍ −Ｘ ｊは０１μｍ
程度となシ、２００ Ｋｅｖとすれば、ＲＰは０．２５
μｍ、Ｘｊは０．２μｍ程度となる。For example, if the ion implantation energy is 100Key, RP is 0.12 fi m -X j is 01 μm
If the degree is 200 Kev, RP is 0.25
μm and Xj are approximately 0.2 μm.
つぎに、ｐ＋形拡散層３の表面に、Ｗ ＋ Ｃｒ ＊
Ａ、ｇを順次積層蒸着してアノード電極５を形成すると
ともに、シリコン基板１の下面にはアンチモンを含む金
および銀を順次積層蒸着してカソード電極７を形成する
。なお、図中６は絶縁膜である。Next, on the surface of the p+ type diffusion layer 3, W + Cr*
The anode electrode 5 is formed by sequentially depositing A and g, and the cathode electrode 7 is formed by sequentially depositing gold and silver containing antimony on the lower surface of the silicon substrate 1. Note that 6 in the figure is an insulating film.
このような実施例によれば、ｐｎ接合深さを従来品に比
較して疾に深くすることができる。このため、Ｗのコン
タクト電極のシンタ一時の接合突き抜けによるショート
、逆方向電流不良、サージ電流による接合破壊等の発生
は抑えることができ、信頼度が向上する、また、接合深
さを深くすることができるということは、不純物拡散時
間を従来よりも長くできることになり、拡散の安定化が
図れるため、ツェナー電圧が安定し歩留が向上する。According to such an embodiment, the pn junction depth can be made much deeper than that of conventional products. Therefore, the occurrence of short circuits due to junction penetration during sintering of W contact electrodes, reverse current defects, junction breakdown due to surge currents, etc. can be suppressed, improving reliability and increasing the junction depth. This means that the impurity diffusion time can be made longer than in the past, and the diffusion can be stabilized, which stabilizes the Zener voltage and improves yield.
一方、この実施例では不純物拡散は深く形成されるため
不純物濃度勾配は緩かになるが、接合が形成される領域
には逆導電形決定不純物が打ち込まれていることから、
この打込層の不純物濃度勾配が勾配を大きくするように
作用する。この結果、接合深さが従来よりも深くなって
も、急峻な不純物濃度勾配を維持することができ、低い
ツェナーダイオードを製造することができる。On the other hand, in this example, the impurity concentration gradient is gentle because the impurity diffusion is deep, but since the opposite conductivity type determining impurity is implanted in the region where the junction is formed,
The impurity concentration gradient of this implanted layer acts to increase the gradient. As a result, even if the junction depth becomes deeper than before, a steep impurity concentration gradient can be maintained, and a low Zener diode can be manufactured.
さらに、この実施例によれば、接合が深くできることか
ら、表面およびｐ＋形拡散層周縁でのブレークダウンを
抑えることができ、従来設けていたガードリングは特に
必要ではなくなシ、ガードリング形成工程を廃止できる
。このため、工程の簡略化によって原価低減も図ること
ができる。Furthermore, according to this embodiment, since the junction can be made deep, breakdown at the surface and the periphery of the p+ type diffusion layer can be suppressed, and the guard ring that was conventionally provided is not particularly necessary. can be abolished. Therefore, cost reduction can be achieved by simplifying the process.
なお、本発明は前記実施例に限定されない。Note that the present invention is not limited to the above embodiments.
以上のように、本発明によれば、接合深さが従来よりも
深くかつ不純物濃度勾配が急峻となる低電圧ツェナーダ
イオードおよびその製造方法を提供することができるこ
とから、特性が安定し、信頼度が高い低電圧ツェナーダ
イオードを歩留よくかつ安価に提供することができる。As described above, according to the present invention, it is possible to provide a low-voltage Zener diode with a deeper junction depth and a steeper impurity concentration gradient than conventional ones, and a method for manufacturing the same, resulting in stable characteristics and high reliability. It is possible to provide low-voltage Zener diodes with high yield and low cost.
第１図は従来の低電圧ツェナーダイオードの断面図。
−ダイオードの製造方法を示すワークの断面図、第４図
は同じく不純物濃度曲線を示すグラフである。
１・・・シリコン基板％２・・エピタキシャル層、３・
・・ｐ＋形拡散層、５ ・アノード電極、７・・・カソ
ード電極、８・・・イオン打込層。FIG. 1 is a cross-sectional view of a conventional low-voltage Zener diode. - A cross-sectional view of a workpiece showing a method of manufacturing a diode, and FIG. 4 is a graph showing an impurity concentration curve. 1...Silicon substrate%2...Epitaxial layer,3.
...p+ type diffusion layer, 5. anode electrode, 7. cathode electrode, 8. ion implantation layer.
Claims (1)
けられてなる低電圧ツェナーダイオードにおいて、前記
接合よυも深い位置に不純物濃度ピークが位置する第１
導電形からなるイオン打込層が設けられていることを特
徴とする低電圧ツェナーダイオード。 ２、第１導電形層の表層部に不純物を拡散させて部分的
に第２導電形層を形成することによって浅い接合を有す
る低電圧ツェナーダイオードを製造する方法において、
前記第２導電形層を形成する前に、イオン打込みによっ
て第１導電形層中に不純物濃度ピークを有する第１導電
形のイオン打込層を形成し、その後に不純物を拡散させ
て第２導電形を形成し、前記不純物濃度ピークよシも浅
い位置に接合を形成することを％徴とする低電圧ツェナ
ーダイオードの製造方法。[Claims] 1. In a low voltage Zener diode in which a second conductivity type layer is partially provided on the surface layer of a first conductivity type layer, an impurity concentration peak is located at a position υ deeper than the junction. 1st
A low voltage Zener diode characterized by being provided with an ion implantation layer made of a conductive type. 2. A method for manufacturing a low voltage Zener diode having a shallow junction by diffusing impurities into the surface layer of the first conductivity type layer to partially form a second conductivity type layer,
Before forming the second conductivity type layer, an ion implantation layer of the first conductivity type having an impurity concentration peak is formed in the first conductivity type layer by ion implantation, and then impurities are diffused to form the second conductivity type layer. A method for manufacturing a low-voltage Zener diode, the method comprising forming a shape and forming a junction at a shallower position than the impurity concentration peak.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18900182A JPS5979578A (en) | 1982-10-29 | 1982-10-29 | Low voltage zener diode and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18900182A JPS5979578A (en) | 1982-10-29 | 1982-10-29 | Low voltage zener diode and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5979578A true JPS5979578A (en) | 1984-05-08 |
Family
ID=16233631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18900182A Pending JPS5979578A (en) | 1982-10-29 | 1982-10-29 | Low voltage zener diode and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5979578A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089427A (en) * | 1990-12-03 | 1992-02-18 | Motorola Inc. | Semiconductor device and method |
| FR2776827A1 (en) * | 1998-03-31 | 1999-10-01 | Sgs Thomson Microelectronics | METHOD FOR MANUFACTURING AN AVALANCHE DIODE WITH ADJUSTABLE THRESHOLD |
-
1982
- 1982-10-29 JP JP18900182A patent/JPS5979578A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089427A (en) * | 1990-12-03 | 1992-02-18 | Motorola Inc. | Semiconductor device and method |
| FR2776827A1 (en) * | 1998-03-31 | 1999-10-01 | Sgs Thomson Microelectronics | METHOD FOR MANUFACTURING AN AVALANCHE DIODE WITH ADJUSTABLE THRESHOLD |
| EP0948038A1 (en) * | 1998-03-31 | 1999-10-06 | STMicroelectronics SA | Method of fabricating an avalanche diode with controllable threshold |
| US6306717B1 (en) | 1998-03-31 | 2001-10-23 | Stmicroelectronics S.A. | Method of manufacturing an avalanche diode with an adjustable threshold |
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