KR100305674B1 - Variable capacitance diode and method for fabricating the same - Google Patents
Variable capacitance diode and method for fabricating the same Download PDFInfo
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- KR100305674B1 KR100305674B1 KR1019990050207A KR19990050207A KR100305674B1 KR 100305674 B1 KR100305674 B1 KR 100305674B1 KR 1019990050207 A KR1019990050207 A KR 1019990050207A KR 19990050207 A KR19990050207 A KR 19990050207A KR 100305674 B1 KR100305674 B1 KR 100305674B1
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- 238000000034 method Methods 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims description 10
- 230000007547 defect Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 25
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H01L29/92—Capacitors having potential barriers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
실리콘 기판 표면에서의 격자 결함 유발로 인해 야기되던 누설전류 발생을 막을 수 있도록 한 가변용량 다이오드 및 그 제조방법이 개시된다.Disclosed are a variable capacitance diode and a method of manufacturing the same, which can prevent leakage current caused by lattice defects on a silicon substrate surface.
이를 구현하기 위하여 본 발명에서는, N+형의 실리콘 기판과; 상기 기판 상에 형성된 N형의 에피층과; 상기 에피층 내의 소정 부분에 형성되며, 깊은 정션 깊이를 갖는 N-캐소드 영역과; 상기 N-캐소드 영역과 PN 접합을 이루도록 상기 에피층 내의 소정 부분에 형성되며, 얕은 접합 깊이를 갖는 P-애노드 영역; 및 상기 P-애노드 영역과 접하도록 형성된 '폴리실리콘/Al' 적층 구조의 애노드 전극으로 이루어진 VCD가 제공된다.In order to implement this, in the present invention, an N + -type silicon substrate; An N-type epi layer formed on the substrate; An N-cathode region formed in a predetermined portion of the epi layer and having a deep junction depth; A P-anode region formed in a predetermined portion of the epi layer to form a PN junction with the N-cathode region and having a shallow junction depth; And a VCD comprising an anode electrode having a 'polysilicon / Al' stacked structure formed in contact with the P-anode region.
Description
본 발명은 가변용량 다이오드(variable capacitance diode:이하, VCD라 한다) 및 그 제조방법에 관한 것으로, 특히 실리콘 기판 표면에서의 격자 결함 유발로 인해 야기되던 누설전류 발생을 막을 수 있도록 한 가변용량 다이오드 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance diode (hereinafter referred to as a VCD) and a method of manufacturing the same. In particular, the present invention relates to a variable capacitance diode capable of preventing leakage current caused by lattice defects on a surface of a silicon substrate. It relates to a manufacturing method.
VCD는 인가되는 전압(역방향 전압)에 따라 정전용량이 변화하는 소자로서, 인가전압을 높이면 용량이 감소되는 특성을 지니므로 주로, AFC 회로나 FM, PM 변조, 스위프 발진기, 오토 워쳐(auto watcher) 등에서 널리 사용되고 있다.VCD is a device whose capacitance changes according to the applied voltage (reverse voltage). Since the capacitance decreases when the applied voltage is increased, it is mainly an AFC circuit, FM, PM modulation, swept oscillator, and auto watcher. It is widely used in the back.
이를 도 1에 제시된 종래의 일반적인 VCD 구조를 참조하여 구체적으로 살펴보면 다음과 같다.This will be described in detail with reference to the conventional general VCD structure shown in FIG. 1.
도 1의 단면도에 의하면, 종래의 VCD는 크게 N+형의 실리콘 기판(10) 상에는 N형의 에피층(12)이 형성되고, 상기 에피층(12) 내의 표면쪽에는 깊은 정션 깊이를 갖는 N-캐소드 영역(14)과 얕은 정션 깊이를 갖는 P-애노드 영역(16)이 PN 접합을 이루도록 놓여지며, 상기 에피층(12) 상에는 상기 P-애노드 영역(16)의 표면이 소정 부분 노출되도록 절연막(18)이 형성되고, 상기 P-애노드 영역(16)의 표면 노출부를 포함한 절연막(18) 상의 소정 부분에 걸쳐서는 Al 재질의 애노드 전극(20)이 형성되며, 상기 실리콘 기판(10)의 이면에는 캐소드 전극(22)이 형성되어 있는 구조로 이루어져 있음을 알 수 있다.According to the cross-sectional view of FIG. 1, in the conventional VCD, an N-type epitaxial layer 12 is formed on a large N + type silicon substrate 10, and N− having a deep junction depth on the surface side of the epitaxial layer 12. A cathode region 14 and a P-anode region 16 having a shallow junction depth are placed to form a PN junction, and an insulating layer (eg, a portion of the P-anode region 16 is exposed on the epitaxial layer 12). 18 is formed, and an anode electrode 20 made of Al is formed over a predetermined portion on the insulating film 18 including the surface exposed portion of the P-anode region 16, and on the back surface of the silicon substrate 10. It can be seen that the cathode electrode 22 is formed of a structure.
따라서, 상기 구조의 VCD는 도 2의 공정블럭도에서 알 수 있듯이 다음의 제 3 단계 공정을 거쳐 제조된다.Therefore, the VCD having the above structure is manufactured through the following third step process as can be seen in the process block diagram of FIG.
제 1 단계(50)로서, N+형의 실리콘 기판(10) 상면에 N형의 에피층(12)을 형성하고, 캐소드 형성부에만 선택적으로 상기 에피층(12)보다 도핑 농도가 높은 N형 불순물(예컨대, 인)을 이온주입한 후 확산시켜 에피층(12) 내에 N-캐소드 영역(14)을 형성한다.As the first step 50, an N-type epitaxial layer 12 is formed on the N + -type silicon substrate 10, and an N-type impurity having a higher doping concentration than the epitaxial layer 12 is selectively formed only in the cathode formation portion. (Eg, phosphorus) is implanted and then diffused to form an N-cathode region 14 in the epi layer 12.
제 2 단계(52)로서, 상기 결과물 중, 애노드 형성부에만 선택적으로 P형 불순물(예컨대, 보론)을 이온주입한 후 확산시켜 에피층(12) 내에 P-애노드 영역(16)을 형성한다. 그 결과, N-캐소드 영역(14)과 P-애노드 영역(16)이 PN 접합을 이루게 된다.In a second step 52, P-type impurities (eg, boron) are selectively implanted into the anode formation portion and then diffused to form the P-anode region 16 in the epi layer 12. As a result, the N-cathode region 14 and the P-anode region 16 form a PN junction.
제 3 단계(54)로서, 상기 에피층(12) 상에는 P-애노드 영역(16)과 접하는 Al 재질의 애노드 전극(20)을 형성하고, 상기 기판(10)의 이면에는 캐소드 전극(22)을 형성하므로써, 본 공정 진행을 완료한다.In a third step 54, an anode electrode 20 of Al material is formed on the epi layer 12, and the cathode electrode 22 is formed on the back surface of the substrate 10. By forming, the process progress is completed.
그러나, 상기 구조를 가지도록 VCD를 제조할 경우에는 공정 진행시 다음과 같은 문제가 발생된다.However, when the VCD is manufactured to have the above structure, the following problem occurs during the process.
N-캐소드 영역(14)과 P-애노드 영역(16)을 형성하기 위하여 실시하는 불순물 주입 및 확산 공정으로 인해 실리콘 기판 표면에 격자 결함이 유발되어져, 누설전류가 야기되는 문제가 발생하게 된다. 이러한 문제가 발생될 경우, 스펙(spec.)(또는 정격)을 만족하는 높은 커패시턴스 변동율을 가지도록 VCD를 구현할 수 없게 되므로, 이에 대한 개선책이 시급하게 요구되고 있다.Impurity implantation and diffusion processes to form the N-cathode region 14 and the P-anode region 16 cause lattice defects on the surface of the silicon substrate, resulting in a problem of leakage current. When such a problem occurs, the VCD cannot be implemented to have a high capacitance variation rate that satisfies a spec (or rating). Therefore, there is an urgent need for improvement.
이에 본 발명의 목적은, VCD 제조시 애노드 전극을 Al의 단층 구조가 아닌 '폴리실리콘/Al'의 적층 구조로 형성해 주므로써, N-캐소드 영역과 P-애노드 영역을 형성할 때 실리콘 기판 표면에 격자 결함이 유발되더라도 상기 결함 덩어리들이 애노드 전극을 이루는 폴리실리콘 내로 싱크(sink)될 수 있도록 하여 누설전류 발생을 막을 수 있도록 한 VCD를 제공함에 있다.Accordingly, an object of the present invention is to form an anode electrode as a 'polysilicon / Al' laminated structure instead of an Al single layer structure in manufacturing a VCD, thereby forming an N-cathode region and a P-anode region on a silicon substrate surface. Even if a lattice defect is induced, the defect mass can be sinked into the polysilicon forming the anode to provide a VCD that prevents leakage current generation.
본 발명의 다른 목적은 상기 구조의 VCD를 용이하게 제조할 수 있는 제조방법을 제공함에 있다.Another object of the present invention is to provide a manufacturing method that can easily manufacture the VCD of the above structure.
도 1은 종래의 VCD 구조를 도시한 단면도,1 is a cross-sectional view showing a conventional VCD structure,
도 2는 도 1의 VCD 제조방법을 도시한 공정블럭도,2 is a process block diagram showing a VCD manufacturing method of FIG.
도 3은 본 발명에서 제안된 VCD 구조를 도시한 단면도,3 is a cross-sectional view showing a VCD structure proposed in the present invention;
도4는 도 3의 VCD 제조방법을 도시한 공정블럭도이다.4 is a process block diagram showing the VCD manufacturing method of FIG.
상기 목적을 달성하기 위하여 본 발명에서는, N+형의 실리콘 기판과; 상기 기판 상에 형성된 N형의 에피층과; 상기 에피층 내의 소정 부분에 형성되며, 깊은 정션 깊이를 갖는 N-캐소드 영역과; 상기 N-캐소드 영역과 PN 접합을 이루도록 상기 에피층 내의 소정 부분에 형성되며, 얕은 접합 깊이를 갖는 P-애노드 영역; 및 상기 P-애노드 영역과 접하도록 형성된 '폴리실리콘/Al' 적층 구조의 애노드 전극으로 이루어진 VCD가 제공된다.In order to achieve the above object, in the present invention, an N + -type silicon substrate; An N-type epi layer formed on the substrate; An N-cathode region formed in a predetermined portion of the epi layer and having a deep junction depth; A P-anode region formed in a predetermined portion of the epi layer to form a PN junction with the N-cathode region and having a shallow junction depth; And a VCD comprising an anode electrode having a 'polysilicon / Al' stacked structure formed in contact with the P-anode region.
본 발명의 다른 목적은, N+형의 실리콘 기판 상에 상기 기판과 동일 도전형의 에피층을 형성하는 단계와; 상기 결과물 중, 캐소드 형성부에만 선택적으로 N형 불순물을 이온주입한 후 확산시켜 상기 에피층 내에 N-캐소드 영역을 형성하는 단계와; 상기 결과물 중, 애노드 형성부에만 선택적으로 P형 불순물을 이온주입한 후 확산시켜 상기 에피층 내에 P-애노드 영역을 형성하는 단계; 및 상기 P-애노드 영역과 접하도록 상기 에피층 상의 소정 부분에 '폴리실리콘/Al' 적층 구조의 애노드 전극을 형성하는 단계로 이루어진 VCD 제조방법이 제공된다.Another object of the present invention is to form an epitaxial layer of the same conductivity type as the substrate on an N + type silicon substrate; Forming an N-cathode region in the epitaxial layer by ion implanting and diffusing N-type impurities only into the cathode forming portion of the resultant; Forming a P-anode region in the epitaxial layer by selectively implanting P-type impurities into the anode forming portion and then diffusing them; And forming an anode electrode of a 'polysilicon / Al' stacked structure on a portion of the epi layer so as to contact the P-anode region.
상기 구조를 가지도록 VCD를 제조할 경우, N-캐소드 영역과 P-애노드 영역을 형성하는 과정에서 실리콘 기판 표면에 격자 결함이 유발되더라도 폴리실리콘을 형성할 때 상기 결함 덩어리들이 자동적으로 폴리실리콘의 그레인 바운더리 내로 싱크되어지므로, 실리콘 기판 표면에 결함이 유발되지 않은 것과 동일한 효과를 얻을 수 있게 된다.In the case of manufacturing the VCD having the above structure, even when lattice defects are caused on the surface of the silicon substrate during the formation of the N-cathode region and the P-anode region, the defect masses automatically form grains of polysilicon when the polysilicon is formed. By sinking into the boundary, the same effect as that in which the defect is not caused on the surface of the silicon substrate can be obtained.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3은 본 발명에서 제안된 VCD 구조를 도시한 단면도를 나타낸다.Figure 3 shows a cross-sectional view showing the VCD structure proposed in the present invention.
도 3의 단면도에 의하면, 본 발명에서 제안된 VCD는 크게, N+형의 실리콘 기판(10) 상에는 N형의 에피층(12)이 형성되고, 상기 에피층(12) 내의 표면쪽에는 깊은 정션 깊이를 갖는 N-캐소드 영역(14)과 얕은 정션 깊이를 갖는 P-애노드 영역(16)이 PN 접합을 이루도록 놓여지며, 상기 에피층(12) 상에는 상기 P-애노드 영역(16)의 표면이 소정 부분 노출되도록 절연막(18)이 형성되고, 상기 P-애노드 영역(16)의 표면 노출부를 포함한 절연막(18) 상의 소정 부분에 걸쳐서는 '폴리실리콘(20a)/Al(20b)' 적층 구조의 애노드 전극(20)이 형성되며, 상기 실리콘 기판(10)의 이면에는 캐소드 전극(22)이 형성되어 있는 구조로 이루어져 있음을 알 수 있다.According to the cross-sectional view of FIG. 3, the VCD proposed in the present invention has a large N-type epitaxial layer 12 formed on the N + type silicon substrate 10, and a deep junction depth on the surface side of the epitaxial layer 12. N-cathode region 14 having a P-anode region 16 having a shallow junction depth is placed to form a PN junction, and a surface of the P-anode region 16 is formed on the epi layer 12. An insulating film 18 is formed so as to be exposed, and an anode electrode having a 'polysilicon 20a / Al (20b)' stacked structure over a predetermined portion on the insulating film 18 including the surface exposed portion of the P-anode region 16. 20 is formed, and the back surface of the silicon substrate 10 has a structure in which a cathode electrode 22 is formed.
따라서, 상기 구조의 VCD는 도 4의 공정블럭도에서 알 수 있듯이 다음의 제 3 단계 공정을 거쳐 제조된다.Therefore, the VCD having the above structure is manufactured through the following third step process as can be seen in the process block diagram of FIG.
제 1 단계(150)로서, N+형의 실리콘 기판(10) 상면에 N형의 에피층(12)을 형성하고, 캐소드 형성부에만 선택적으로 상기 에피층(12)보다 도핑 농도가 높은 N형 불순물(예컨대, 인)을 이온주입한 후 확산시켜 에피층(12) 내에 N-캐소드 영역(14)을 형성한다.As the first step 150, an N-type epitaxial layer 12 is formed on the N + -type silicon substrate 10, and an N-type impurity having a higher doping concentration than the epitaxial layer 12 is selectively formed only on the cathode formation portion. (Eg, phosphorus) is implanted and then diffused to form an N-cathode region 14 in the epi layer 12.
제 2 단계(152)로서, 상기 결과물 중, 애노드 형성부에만 선택적으로 P형 불순물(예컨대, 보론)을 이온주입한 후 확산시켜 에피층(12) 내에 P-애노드 영역(16)을 형성한다. 그 결과, N-캐소드 영역(14)과 P-애노드 영역(16)이 PN 접합을 이루게 된다.As a second step 152, the P-anode region 16 is formed in the epitaxial layer 12 by selectively implanting P-type impurities (for example, boron) into the anode forming portion and diffusing them. As a result, the N-cathode region 14 and the P-anode region 16 form a PN junction.
제 3 단계(154)로서, P-애노드 영역(16)의 표면이 소정 부분 노출되도록 에피층 상에 절연막(18)을 형성하고, 상기 결과물 전면에 액체 소스가 코팅된 도전성 재질의 폴리실리콘(20a)과 Al(20b)을 순차 적층한 다음, 상기 절연막(18)의 표면이 소정 부분 노출되도록 이들을 선택식각하여 '폴리실리콘(20a)/Al(20b)' 적층 구조의 애노드 전극(20)을 형성하고, 상기 기판(10)의 이면에 캐소드 전극(22)을 형성해 주므로써, 본 공정 진행을 완료한다. 이때, 상기 폴리실리콘(20a)은 600 ±200℃의 온도 범위 내에서 막질 증착을 이루는 것이 바람직하다.In a third step 154, the insulating film 18 is formed on the epitaxial layer so that the surface of the P-anode region 16 is partially exposed, and the polysilicon 20a of the conductive material is coated with a liquid source on the entire surface of the resultant. ) And Al (20b) are sequentially stacked and then selectively etched to expose a portion of the surface of the insulating film 18 to form an anode electrode 20 having a 'polysilicon 20a / Al (20b)' stacked structure. And the cathode electrode 22 is formed in the back surface of the said board | substrate 10, and this process progress is completed. At this time, the polysilicon 20a is preferably a film quality deposition within a temperature range of 600 ± 200 ℃.
이와 같이 VCD를 제조할 경우, N-캐소드 영역(14)과 P-애노드 영역(16)을 형성하는 과정에서 실리콘 기판(10)의 표면쪽에 격자 결함이 유발되더라도 폴리실리콘(20a) 증착시 가해지는 온도에 의해 상기 결함 덩어리들이 폴리실리콘의 그레인 바운더리 내로 자동 싱크되어져, 마치 결함 발생이 유발되지 않은 것과 같은 기판(10)의 표면 상태를 유지할 수 있게 되므로, 누설전류 발생을 막을 수 있게 될 뿐 아니라 스펙(또는 정격)을 만족하는 높은 커패시턴스 변동율을 갖는 VCD를 구현할 수 있게 된다.When the VCD is manufactured as described above, even when lattice defects are caused on the surface of the silicon substrate 10 in the process of forming the N-cathode region 14 and the P-anode region 16, the polysilicon 20a is applied during deposition. Temperature causes the defect masses to automatically sink into the grain boundaries of the polysilicon to maintain the surface state of the substrate 10 as if no defects have occurred, thereby preventing leakage currents as well as specification. It is possible to implement a VCD having a high capacitance variation rate that satisfies (or ratings).
이상에서 살펴본 바와 같이 본 발명에 의하면, 애노드 전극을 Al의 단층 구조가 아닌 '폴리실리콘/Al'의 적층 구조로 가져가 주므로써, N-캐소드 영역이나 P-애노드 영역을 형성하기 위한 불순물 주입 및 확산 과정에서 실리콘 기판 표면에격자 결함이 유발되더라도 폴리실리콘 내로 상기 결함 덩어리들이 싱크되도록 유도할 수 있게 되므로, 실리콘 기판 표면에서의 누설전류 발생을 막을 수 있게 된다.As described above, according to the present invention, since the anode electrode is not a single layer structure of Al, but a polysilicon / Al layer structure, impurity implantation for forming an N-cathode region or a P-anode region and Even if lattice defects are caused on the surface of the silicon substrate during diffusion, the defect masses can be induced to sink into the polysilicon, thereby preventing the occurrence of leakage current on the surface of the silicon substrate.
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