JPS5979522A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate annealing without outward diffusion by forming SiO2 film having desired thickness on the surface of a semiconductor substrate in advance by heat treatment with specified temperature in N2 gas atmosphere containing O2 of predetermined quantity when annealing the substrate implanted with n<+> type impurity ion. CONSTITUTION:Thick field SiO2 film 2 is formed on circumferencial portion of p type Si substrate 1, and central portion on the surface of the substrate 1 surrounded with said film 2 is provided with gate electrode 5 consisting of polycrystalline Si through gate SiO2 film 4. Then, n type impurity ion such as As and P is implanted into the substrate 1 on both sides of the electrode 5 used as a mask by high concentration to generate an implantation region for source and drain 6. After that, for drive-in diffusion by annealing, the substrate 1 is placed in N2 gas atmosphere containing O2 of 3-100% of volume ratio at first. Next, heat treatment of 100-600 deg.C is made to form SiO2 film 7 of 30-100Angstrom thickness on the entire surface of the substrate 1 and then annealing of 900- 1,100 deg.C for 20-60min is effected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having an N-type impurity region implanted with high ion concentration.

Conventional Si semiconductor devices perform high-temperature annealing in a N2g atmosphere to electrically activate a Si region into which high-concentration N-type impurities have been ion-implanted and to recover crystal defects generated during ion implantation, in order to prevent outward diffusion. 8102 at 400°C in advance.
It was essential to perform the N2 high-temperature annealing after forming the substrate (approximately 1000X).

Here, outward diffusion means that impurities jump out from a region implanted at a high concentration during a heat treatment step, and the impurity concentration in the diffusion region changes, that is, it deviates from the designed value.

The reason for the need for annealing in the N2 atmosphere is that it is well known that secondary defects such as dislocation loops and dislocation networks occur when annealing is performed in the N2 atmosphere, resulting in deterioration of bonding characteristics.

Thus, a drawback of the conventional method is that it requires a step of forming a thick low-temperature CV I) film before the N2 annealing step to prevent outward diffusion. Therefore, the processing time increases.

This invention was made to solve the above-mentioned conventional drawbacks, and it is possible to easily perform N7 annealing of N-type impurity implanted with high concentration ions without out-diffusion, and it is possible to easily perform N7 annealing of N-type impurity implanted with high concentration ions, and to eliminate the need for high concentration ion implantation. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be used in a method for manufacturing a LSI.

Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. Figure 1(a) to Figure 1(
e) is a process explanatory diagram for explaining one example thereof. The embodiments shown in FIGS. 1(a) to 1(e) are shown using an S1/lviO8 type semiconductor integrated circuit as an example.

As shown in FIG. 1(a), LOcoS (LOCal 0oxid4aton
Form a pattern of Si3N film 3 for (ofSilicon), and use it as an oxidation mask to form field S io2
Form g 2 k.

Next, as shown in FIG. 1 α]), the 5isN+ film 3 is removed, and a gate 5in2 film 4 and a PolySi film 5 are sequentially formed on the P-type substrate 1.

Next, as shown in FIG. 1C, an N-type impurity (As) is implanted by ion implantation using the Po1ySi film 5 as a mask.

P) A (H5X 10" ~ 2 X 10"cm-2
, 40 KeV to form source/drain 6'.

Next, the ion-implanted N-type impurity was implanted at a high temperature (900-1100°C) in N2 for total electrical activation and crystal recovery.
Although it is necessary to perform annealing (20 to 60 minutes), As, P
S i 02 to prevent outward diffusion of ON-type impurities
As shown in FIG. 1(d), the method of forming the film 7 with a thermal oxide film is distinctive.

This will be explained in detail using FIG. 2.

FIG. 2(a) is a schematic diagram of the furnace core tube, and shows the temperature profile of the hole in FIG.

In this FIG. 2(a), FIG. 2 [present]), 100 indicates a furnace, and 200 indicates a heater. The heater 200 is disposed at the center of the outer circumferential surface of the furnace 100 with a length d), and the concentration in the furnace 100 is high at this center, reaching T2. When inserted into the furnace 100, as shown in FIG. 2(b), a low temperature region ((( a) When the P-type substrate 1 is in the temperature range (normally in the range of 100 to 600°C), 0202 gas is flowed from the gas inlet at the back of the furnace (part (C)) to thermally grow a thin 5i02 film 7 on the surface. form.

And, if it is 3%, it will be about 30 people, and if it is 100%, it will be about 100A.
I) Si02 film is implanted with As by ion implantation method,
It is formed on the N-type impurity of P.

As shown in Figure 2 (a), the time that Sl waeno exists in the area (a) is approximately 10 to 20 minutes when left at the furnace mouth in a normal diffusion furnace treatment method, and the speed at which the entire area (a) is inserted is approximately 10 to 20 minutes. Approximately 5~
The total time will be 15-30 minutes (10 minutes).

The N2 concentration case of 4% 02 concentration explained above and the conventional method
FIGS. 4 and 5 show the results of a comparative experiment on outward diffusion when low temperature 3i02 was formed at 100 OA before annealing. Figure 4 is 1×10I6crn'', 4QK
As'fr of ev:P (100)Si, ρo=20
This figure shows the results of the sheet resistance after a sample into which ions were implanted into Ωα was placed in the center for 30 minutes in a diffusion furnace at various temperatures.

The processing method is as described above.

CVD without outward diffusion S i 02100f k
It was formed in advance before N2 annealing. (Compared to the conventional method, the sheet resistance of the sample in which a thin thermal oxide film was formed in the low-temperature region at the furnace mouth in an atmosphere with an 02/N2 capacity ratio of 3 to 100% in the method of this invention was The results are the same, and it can be seen that outward diffusion can be prevented even within the above range.

This figure 4 shows 1000 without forming 5102 film.
'ρ when outward diffusion occurs after 30 minutes of treatment during CNt
8 is shown. In this case, since As decreases to 40 to 10 o 10, ρ8 becomes high. For example, the results of analysis using the pack scattering method show that compared to the case of 1000°C (ρ5-18°) where outward diffusion does not occur,
In the case of 50%, it was found that about 40% of As75E was released.

Further, although FIG. 59 shows the case where P is used as the N-type impurity implanted by the ion implantation method, it was found that the case is similar to the case of As shown in FIG. 4.

In this way, as shown in FIG. 1(d), a thin 5
102 film is formed in the low temperature region at the mouth of the furnace, and N2 annealing is sequentially performed in the center of the furnace to form electrically stable source/drain regions 6.

In this case, as shown in FIGS. 4 and 5, if annealing is performed for 10006C30 minutes, the result will be 18°/D in the case of As and 9Ω/in the case of P. In general, a resistance lower than 30°/diffusion layer resistance usage range in a 2 to 3 tt MO8 integrated circuit can be stably obtained.

Thereafter, as shown in FIG. 1(e), a PSG film 8 is formed according to a conventional method, and a contact region 9 is opened.
/=wiring 10 is formed.

The above description has been made using the first embodiment f of the present invention, a method for manufacturing a Si gate MO8 integrated circuit, as an example. However, this method is applicable to general Si substrate integrated circuits in which high concentration P or Si ions are implanted and N2 annealing is performed Naturally, it can be applied to bipolar, metal game-1-MO8, etc.).

As explained above, in the first embodiment, S i
02 film 7 is thermally grown 5102, and can be performed with a much thinner oxide film than conventional techniques, and can be grown as a source without forming a low-temperature CVD film to prevent outward diffusion before N2 annealing. - Since it is possible to prevent outward diffusion of As and 'p from the drain region, there is an advantage that the process can be greatly simplified.

Furthermore, since the 1-8i02 film formed in the quartz furnace core tube can be used in a cleaner state than in the low-temperature CVD equipment, there is also the advantage of stabilization in terms of leakage current and reliability.

In addition, in the first embodiment, (a) in FIG. 2(a)
The method was to change the sequence of gas entering from the gas inlet (section (C)) in order to create a 02 atmosphere in the region (1) and a N2 atmosphere in the (1) region, but the ), the shape of the furnace core tube is such that N2 gas is introduced from the gas inlet at the back of the furnace, and 02 gas is introduced from the region (a) below the temperature T, with an inlet 101. (shown as a furnace 100), it is possible to completely form the thin S+02 film 7 in the region (a) without changing the gas sequence and anneal it in a complete N2 atmosphere in the center of the furnace 100. , has the same advantages as the first embodiment.

As described above, according to the method of manufacturing a semiconductor device of the present invention, a thin (SiO2 film) is implanted in an atmosphere of a mixture of N2 and 02 after a high concentration of N-type impurity is implanted onto a semiconductor substrate by ion implantation. This has the advantage that the N-type impurity implanted at a high concentration can be easily annealed without outward diffusion. It can be used in manufacturing methods.

[Brief explanation of drawings]

FIG. 1(a) to FIG. 1(e) are process explanatory diagrams for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention, respectively, and FIG. A schematic diagram of the furnace core tube for explanation, FIG. 2(1)) is a diagram showing the temperature profile of the furnace core tube of FIG. 2(a), and FIG. FIG. 4 is a diagram schematically showing a reactor core tube applied to the above embodiment, and FIG. 4 shows N2 annealing with and without an S+02 film when Asi is used as the N-type impurity implanted by the ion implantation method in the semiconductor device manufacturing method described above. Figure 5 shows the relationship between temperature and sheet resistance. Figure 5 shows the relationship between annealing temperature and sheet resistance depending on the presence or absence of a 5in2 film when Pk is used as an N-type impurity implanted by the ion implantation method in the manufacturing method of the same semiconductor device. FIG. 1...P-type substrate, 2...Field S+02 film, 3゛. Si, N4 film, 4... Gate 5102 film, 5...
polySi film, 6...source/drain, 7...l
) 102 N, 8...]) S G film, 9... Contact region, ]0... At wiring. Figure 2 □ `` ; □ Figure 3 1 = Procedural amendment 1958) 1) Month;, 1'' Director General of the Patent Office Wakasugi Oro 1, Indication of the case Showa, 7, Patent Application No. 189097 2, Name of the invention: Method for manufacturing semiconductor devices 3. Relationship with the amended case Patent Applicant (029) Oki'
1tI-Kogyo Co., Ltd. 4, Agent 5, Amendment Order No. 171 dated 1920/1999 IE
I (Voluntary) 6. Details subject to amendment! 41'jd7 of Detailed Explanation of the Invention of No. 1, Contents of Amendment As shown in Attachment 7, Contents of Amendment 1) "Concentration" on page 4, line 19 of the specification is corrected to "temperature." 2) On page 5, line 15, 1 or more, please correct "explain/ko" to "explained above." 3) Correct page 6, line 3 r CVD 5102100 A J to r CVD5iO□ to 100OAJ. 4) On page 6, line 9, "Figure 4 is" is corrected to "Figure 4 is". 5) On page 6, line 11, “indicates ρ8.” was changed to “also indicates ρ.”
I am corrected. 6) On page 6, line 16, change “I got it.” to “I got it.”
The mark indicates low temperature CV D S 10271i: 1000 A, and the Δ mark indicates 02/N at the furnace mouth, and 5i02 at 4%.
It shows the case where ``W'' is corrected. 7) On page 9, line 3, ``Shita no de'' is corrected to ``Shita mo de''.

Claims (4)

[Claims] (1) Step of forming a highly concentrated N-type impurity region on the surface of the semiconductor substrate by ion implantation, and forming a thin (Si02 film entirely) on the surface of the N-type impurity region in a mixed atmosphere of oxygen gas and nitrogen gas. A method for manufacturing a semiconductor device, comprising a step of forming the S + 02 film, and annealing the semiconductor substrate after forming the S + 02 film. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the oxygen gas has a volume ratio of 3 to 100% to nitrogen gas. (3) The temperature at which the entire 5i02 film is formed is 100 to 600.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature is .degree. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the SiO2 film has a thickness of 30 to 100X.