JPS59791B2 - Micro-hakiyori-sokutei-souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microwave distance measuring device that measures distance from the phase difference of interference using a two-frequency microwave interferometer. It relates to compensation or warning devices.

Conventionally, when an obstacle is present in the measurement path between the antenna and the object to be measured, this type of device measures the distance to the obstacle and outputs erroneous information.

Therefore, there was a problem that the control system was disturbed. The present invention was made in order to eliminate the above-mentioned drawbacks, and the control system is not disturbed by the presence of obstacles, and the microwave distance is such that it is possible to warn of the presence of obstacles. The purpose is to provide a measuring device.

An object of the present invention is to detect the presence of an obstacle between the measuring device and the object to be measured from a steep change in the signal proportional to the distance in a device that measures distance from the phase difference of interference using a two-frequency microwave interferometer. This is accomplished by detecting and maintaining the output of the measuring device at the measurement signal immediately before the obstacle exists while the obstacle is present.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention.

The output signal 50 of the microwave distance measuring device IB, which measures the distance from the device to the object to be measured using microwaves, is separated into three signals. One is sent to the analog switch ISW, one to the time delay circuit IDEL, and one to the subtracter ISVB.

The subtracter ISUB subtracts the output 50 of the device IB and the output S of the time delay circuit IDEL and sends the output 52 to the comparator I.
Give to COM, 2COM.

The output 51 of the time delay circuit IDEL is sent to the analog switch ISW via the sample and hold circuit ISH.
The comparator ICOM outputs a logic signal when the subtraction output 52 exceeds the set value V1, and sets the flip-flop IFF.

In addition, the comparator 2COM outputs a logic signal when the subtraction output 52 is less than the set value V2, performs OR logic with the initial signal or manual reset signal MS using the OR circuit IOR, and resets the flip-flop IFF. .

Time t1 when the output S3 of flip-flop 1FF exists
During the period from T2 to T2, the sample and hold circuit 1SH is in a holding state, and the analog switch 1SW operates to select the output of the sample and hold circuit 1SH to provide an output S4.

In addition, the output S3 of the flip-flop 1FF drives the analog switch 2SW by 1, and the constant power supply (voltage or current) V
O is selected and input to the integrator 11NT.

The output of this integrator 1NT and the set value 3 are connected to the comparator 3C0M.
A warning signal S5 is given to a signal exceeding a certain value. The operation of the present invention will be explained below with reference to FIG.

1B output S of the measuring device. and the output S1 of the time delay circuit 1DEL are as shown in FIG. 2a, and the distance signals become discontinuous during the time T when there is an obstacle.

This signal S.

By taking the difference between and S1 using a subtractor 1SVB, a signal S2 corresponding to the amount of change in the signal before and after the presence of the obstacle is obtained (FIG. 2b). Signal S2 is connected to comparator 1C0M,2
Comparing with the C0M set values Vl and V3, the signal value is set to 1.
When the set value V2 is exceeded, the flip-flop 1FF is set, and when the set value V2 is exceeded, the flip-flop 1FF is set.
into the reset state. The time t1 to T2 during which the flip-flop 1FF is set is the time when an obstacle exists (c in the same figure), and this signal S3 causes the sample-and-hold circuit 1SH, which is currently sampling the time-delayed signal, to be held in a holding state. The analog switch 1SW is driven to select the circuit 1SH, and the distance signal before the presence of the obstacle is provided as the output signal S4 (d in the figure).

After removing the obstacle, the output S3 of flip-flop 1FF
Since the signal disappears, the analog switch 1SW becomes the signal S. is directly driven as the output signal S4. Furthermore, if an obstacle exists for a long time, the distance between the held signal and the actual object to be measured may become too large.

Furthermore, the presence of obstacles for a long period of time may lead to danger. Therefore, if an obstacle exists for a certain period of time, a warning signal will be issued. That is, the switch 2SW is driven by the output S3 of the flip-flop 1FF to maintain a constant power supply V.
. is selected and sent to the integrator 11NT to obtain an output proportional to time. Comparator 3C0M compares this output with set value V3.
When the set value V3 is exceeded, an alarm signal S5 is given. In the present invention, various modifications can be considered in addition to the above embodiments.

FIG. 3 shows a modification in which the analog switch 2SW is omitted.

In the embodiment of the present invention shown in FIG. 1, the time-delayed signal is held and output only when there is an obstacle, but the analog switch 1SW may be omitted if it is sufficient to detect the delayed signal even in normal times. In the modification shown in the figure, since the sample and hold circuit 1SH is normally in the sampling state, it outputs a signal delayed by the time delay circuit 1DEL.

When an obstacle enters, the sample and hold circuit 1SH enters a holding state, and when the obstacle is removed, it switches to a sample state, but since there is a delay in the time delay circuit 1DEL, the obstacle signal remains by the amount of the delay. To remove this, comparator 2C
A second time delay circuit 2DEL is inserted after 0M to delay the arrival of the flip-flop 1FF reset signal and extend the holding time of the sample and hold circuit 1SH until the obstruction signal disappears. FIG. 4 shows another modification in which the time delay circuit 1DEL is omitted.

In this modification, the clock 1CL causes the sample and hold circuit 1SH to periodically repeat sampling and holding during normal operation. The output of this sample hold circuit 1SH and the output S of the measuring device. The amount of change in the signal is detected by subtracting the Comparator 1C0 when an obstacle exists
M outputs a signal and provides an inverted input Q to the NAND gate 1NA via the inverter 11NV.

This inverting input prevents the clock signal of clock 1CL from going to sample and hold circuit 1SH. At the same time, circuit 1SH holds the signal before the obstacle entered.
At this time, since the analog switch 1SW is switched to the circuit 1SH side by the output of the comparator 1C0M, the held signal is used as the output signal S4. Additionally, comparator 1C0M provides a signal while an obstacle is present.

Therefore, the flip-flop 1FF in FIGS. 1 and 3 becomes unnecessary. In this method, when the sample hold circuit 1SH detects an obstacle during sampling, the subtracter 1SU
Since there is no deviation in the B output, there is a possibility that an obstacle may not be detected.

For this reason, as shown in FIG. 5, two sample and hold circuits 1SH and 2SH may be used to alternately sample. FIGS. 6 and 7 show modified examples in which the calculations in FIGS. 1 and 4 are digitized, respectively.

The output signal of the measuring device 1B is digitized by an AD converter 1AD and then passed through a shift register 1SR to form a delayed signal. The delayed signal is subtracted from the output signal of the AD converter 1AD by a subtracter 1SVB, and outputs are provided to comparators 1C0M and 2C0M. In the modified example shown in FIG.
is in the set state. Further, the reset is performed by detecting the point where the obstacle disappears with the comparator 2C0M and performing an OR logic between this detection signal and the initial or manual reset signal MS in the OR circuit 10R. flipflop 1
The output of the FF reads the register 1REG and converts the contents of the register 1REG into analog via the DA converter 1DA to obtain a desired signal.

In the modified example shown in FIG. 7, the output of the subtracter 1SVB is set to 1.
Since a state exceeding 1C0 indicates the presence of an obstacle, the comparator 1C0
The output of M is inverted by an inverter 11NV and inputted to a NAND gate 1NA to block the clock 1CL and stop the shift operation of the shift register 1SR.

As described above, the present invention detects the presence of an obstacle from a sharp change in a signal obtained by subtracting a delayed distance signal and a current distance signal, and detects the presence of an obstacle using a sample and hold circuit. By retaining the measurement signal just before an obstacle exists, the intervention of the obstacle can be detected or a warning can be given, and the presence of the obstacle can prevent the control system from being significantly disturbed. A distance measuring device can be provided.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of the embodiment in FIG. FIG. 7 is an explanatory diagram of a modification of the digital type. 1B...Measuring device, 1DEL, 2DEL...
...Time delay circuit, 1SUB...Subtractor, 1
C0M, 2C0M, 3C0M...Comparator, 1S
H, 2SH...Sample hold circuit, 1FF
...Flip-flop, 1SW, 2SW, 3S
W...Analog switch, 11NT...
・Integrator, 10R...OR circuit, KL...
...Clock, 1NA, 2NA...NAND gate, 11NV...Inverter, 1AD...A
D converter, 1SR...Shift register, 1RE
G...Lujistar, 1DA...DA converter.

Claims (1)

[Claims] 1. In a device that measures distance from the phase difference of interference using a two-frequency microwave interferometer, there is a delay circuit that delays a distance signal that is the output of the measurement position for a certain period of time, and a delay circuit that delays the distance signal that is the output of the measurement position, and a delay circuit that delays the output signal of the delay means and the distance signal. A subtracter for obtaining a signal difference, a comparator for comparing the subtracter output with a separately given set value, and an output of the delay circuit that is given when the subtracter output exceeds the set value. A microwave distance measuring device comprising: a holding circuit for holding.