JPS5975662A - Thyristor - Google Patents

Thyristor

Info

Publication number
JPS5975662A
JPS5975662A JP18562482A JP18562482A JPS5975662A JP S5975662 A JPS5975662 A JP S5975662A JP 18562482 A JP18562482 A JP 18562482A JP 18562482 A JP18562482 A JP 18562482A JP S5975662 A JPS5975662 A JP S5975662A
Authority
JP
Japan
Prior art keywords
region
gate
thyristor
junction
vicinity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18562482A
Other languages
Japanese (ja)
Inventor
Toshihiko Aimi
相見 俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18562482A priority Critical patent/JPS5975662A/en
Publication of JPS5975662A publication Critical patent/JPS5975662A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839Cathode regions of thyristors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012Base regions of thyristors
    • H01L29/102Cathode base regions of thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To enable to reduce the gate sensitivity of the titled thyristor while it is being controlled by a method wherein a metal having a high potential such as gold, platinum, copper and the like is implanted in the region in the vicinity of the P2-N2 junction located between a gate electrode and a cathode electrode. CONSTITUTION:An N type substrate 1 of 30-40OMEGA/cm in specific resistance is thinned off to the thickness of 250mum or thereabout by performing a chemical polishing method. Then, layers P1 and P2 are provided by diffusing gallium from both sides. A silicon oxide film is provided by oxidizing a wafer at a high temperature, and after the part to be turned to a cathode region has been removed by performing an optical method, the region to be turned to a diffusion layer N2 is provided using phosphorus. An ion implantation is selectively performed in the region 8 located in the vicinity of junction P2-N2 using photoresist, and the gas obtained by evaporating an aqueous solution, and a sintering is performed. As a result, the low current characteristics of current amplification factor of transistors P1, N1 and P2 can be reduced, thereby enabling to reduce the gate sensitivity of the thyristor.

Description

【発明の詳細な説明】 この発明はP L −N 1−P 2−N 24層構造
を持つサイリスクのゲート特性の改善に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvement of the gate characteristics of a silice having a P L -N 1 -P 2 -N 24 layer structure.

従来J’1−N)−P2−N2構造を持つサイリスクに
おいては)’ IF5層の形成の為、にN1型基板の両
面よりポロンガリウム等の不純物を拡散した後さらにリ
ン等を用いて12層上にN2層を拡散してPl−Nl−
P2−N2構造を形成する。N2層よシ注入されP2層
を横切る少数キャリアであるエレクトロンの寿命は拡散
技術の向上とを共に重金属汚染によるライフタイムの減
少がなくなシ、基板及び拡散層のライフタイムに近ずく
。この為にN2−P2−Nl  よシなるトランジスタ
は基板の再結合の影響がなく、又表面においてもフレー
ナ接合となっている為に影響が少ないので電流増[1]
率の電流依存性は非常に少く、低札、流領域に於ても低
下しない。この41はサイリスクとしてみた場合には非
常に高感用となり一般的には望ましいが、特殊な用途殊
にノイズによる誤点弧のおそれのある回路には不向きで
、ゲート感度(IUT)を上げることがしばしば要求さ
れている。
Conventionally, in SIRISK with J'1-N)-P2-N2 structure, to form 5 layers of IF, impurities such as poron gallium are diffused from both sides of the N1 type substrate, and then 12 layers are formed using phosphorus, etc. Diffuse N2 layer on top to form Pl-Nl-
Forms a P2-N2 structure. The lifetime of electrons, which are minority carriers injected through the N2 layer and crossing the P2 layer, will approach the lifetime of the substrate and the diffusion layer as diffusion technology improves and the lifetime is no longer shortened due to heavy metal contamination. For this reason, N2-P2-Nl transistors are not affected by recombination of the substrate, and since the surface is also a flaner junction, the effect is small, so the current increases [1]
The current dependence of the rate is very small and does not decrease even in the low charge and current range. This 41 is very sensitive in terms of silicon risk and is generally desirable, but it is not suitable for special applications, especially circuits where there is a risk of false firing due to noise, and it is necessary to increase the gate sensitivity (IUT). is often required.

本発明はこの様な要求に対応する仁とを目的としている
The present invention is aimed at meeting such demands.

本発明はゲート感度をコントロールしながら低下させる
ことを目的としている。Pl−Nl−P2−N2サイリ
スクはPI−Nl−P2トランジスタとN1−P2−N
2)ランリスクのベース共通の回路として一般的には説
明される。この為にゲート感度を低下させる為にはPl
−Nl−P2 )ランリスク又はN1=P27N2 +
−ランジスタの電流増巾率の電流特性を、低電流レベル
領域で低下させitば良い。
The present invention aims to reduce gate sensitivity while controlling it. Pl-Nl-P2-N2 transistor is PI-Nl-P2 transistor and N1-P2-N
2) It is generally explained as a common circuit based on run risk. Therefore, in order to reduce the gate sensitivity, Pl
-Nl-P2) Run risk or N1=P27N2 +
- It is sufficient to reduce the current characteristic of the current amplification rate of the transistor in a low current level region.

すなわちゲート[極とカソード電極の設けられる間のP
2−N2接合近傍にイオンインプランテーション法によ
シ金、白金、銅尋の深い準位を持った金属を打ち込むこ
とによシ表面再結合速度が上昇し、Pt−N1−P2)
ランジ、スタの電流増「1〕率の低η1流特性を低下さ
せることができ、ゲート感度を低下させることができる
That is, the gate [P between the electrode and the cathode electrode]
By implanting metals with deep levels, such as gold, platinum, and copper, near the 2-N2 junction using the ion implantation method, the surface recombination rate increases, and the Pt-N1-P2)
It is possible to reduce the low η1 current characteristics of the lunge and star current increase rate, and the gate sensitivity can be reduced.

次に本発明の一実施例を図面を、用いながら説明する。Next, one embodiment of the present invention will be described with reference to the drawings.

まず基板の比抵抗30〜40Ω鑞のN型基板1を化学的
に研磨して厚さ250μm程度とする0次にシリコン基
板10両面よシガリウムを用いて拡散しPl、p2層を
設ける、ウェハーを高温で酸化し、シリコン酸化膜を設
け、公知の光学的方法によりカソード領域となる部分の
みをとシ去った同様にフォトレジストを用いて選択的に
P2−N2接合近傍8に金を含む水溶液を蒸気化したガ
スを用いてイオンインプランテーションを行い、シンタ
ーを行う。この様な工程を用いてケート感度を1μA〜
1mA程度にコントロールすることができた0
First, an N-type substrate 1 with a specific resistance of 30 to 40 Ω is chemically polished to a thickness of about 250 μm.Next, cigallium is used to diffuse the silicon substrate 10 on both sides to form Pl and p2 layers. A silicon oxide film was formed by oxidation at high temperature, and only the portion that would become the cathode region was removed using a known optical method. Similarly, a photoresist was used to selectively apply an aqueous solution containing gold to the vicinity of the P2-N2 junction 8. Perform ion implantation using vaporized gas and perform sintering. Using this process, the cell sensitivity can be increased to 1 μA or more.
I was able to control it to around 1mA.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のサイリスタの断面を示している。 尚、図において、1  シリコン基板、2 ・・P型ゲ
ート領域、計・・・・・2重アノード領域、4・・・・
・・カソード領域、5・・・・・アノード電極、6・・
・ カソード電極、7  ・・ゲート電極、8・・・ 
・イオンイングランチージョン領域、である。
FIG. 1 shows a cross section of a thyristor according to the invention. In the figure, 1: silicon substrate, 2: P-type gate region, total: double anode region, 4:
...Cathode region, 5...Anode electrode, 6...
・Cathode electrode, 7...Gate electrode, 8...
-Ion-injection region.

Claims (1)

【特許請求の範囲】[Claims] 一導電型半導体基板の面図よシ逆導電型の不純物を拡散
し、さらにその片面より一導電型不純物を拡散してなる
P 1−N ] −P 2−N 2構造を有するツイリ
スタにおいて、グー)[極とカソード■極の設けられる
間のP2−N2接合近傍にイオンインプランテーション
法により金、白金9例等の深い準位を持った金属を打ち
込んだことを特徴とするサイリスク。
In a Twiristor having a P 1-N ] -P 2-N 2 structure in which an impurity of an opposite conductivity type is diffused from one side of a semiconductor substrate of one conductivity type, and an impurity of one conductivity type is further diffused from one side of the semiconductor substrate, ) [Sirisk characterized by implanting a metal with a deep level such as gold or platinum by ion implantation method into the vicinity of the P2-N2 junction between the pole and the cathode.
JP18562482A 1982-10-22 1982-10-22 Thyristor Pending JPS5975662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18562482A JPS5975662A (en) 1982-10-22 1982-10-22 Thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18562482A JPS5975662A (en) 1982-10-22 1982-10-22 Thyristor

Publications (1)

Publication Number Publication Date
JPS5975662A true JPS5975662A (en) 1984-04-28

Family

ID=16174042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18562482A Pending JPS5975662A (en) 1982-10-22 1982-10-22 Thyristor

Country Status (1)

Country Link
JP (1) JPS5975662A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0488440A2 (en) * 1990-11-29 1992-06-03 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process of introduction and diffusion of platinum ions in a slice of silicon
US6093955A (en) * 1994-08-05 2000-07-25 Garnham; David A. Power semiconductor device
CN111307913A (en) * 2020-03-29 2020-06-19 复旦大学 Semiconductor ion sensor without reference electrode and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0488440A2 (en) * 1990-11-29 1992-06-03 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process of introduction and diffusion of platinum ions in a slice of silicon
US5227315A (en) * 1990-11-29 1993-07-13 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process of introduction and diffusion of platinum ions in a slice of silicon
US6093955A (en) * 1994-08-05 2000-07-25 Garnham; David A. Power semiconductor device
CN111307913A (en) * 2020-03-29 2020-06-19 复旦大学 Semiconductor ion sensor without reference electrode and preparation method thereof

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